阅读说明：本技术 生成集成电路布局图的方法 (Method for generating integrated circuit layout ) 是由 彭士玮 赖志明 曾健庭 于 2020-08-14 设计创作，主要内容包括：一种生成集成电路布局图的方法包括在单元区域中布局第一导电特征布局图案。第一导电特征布局图案在第一方向上延伸,且单元区域具有在第二方向上延伸的相对第一及第二单元边界。在单元区域中,布局第二导电特征布局图案在第一方向上延伸。交替地布局第一及第二导电特征布局图案。在单元区域的第一单元边界上及第一导电特征布局图案的端部上,布局第一切割特征布局图案。第一切割特征布局图案中的一个在第一方向上偏移了第一切割特征布局图案中的另一个。生成包含第一、第二导电特征布局图案及第一切割特征布局图案的集成电路布局图。(A method of generating an integrated circuit layout includes laying out a first conductive feature layout pattern in a cell region. The first conductive feature layout pattern extends in a first direction, and the cell region has opposing first and second cell boundaries extending in a second direction. In the cell region, the second conductive feature layout pattern is laid out to extend in the first direction. The first and second conductive feature layout patterns are alternately arranged. A first cut feature layout pattern is laid out on a first cell boundary of the cell region and on an end of the first conductive feature layout pattern. One of the first cut feature layout patterns is offset from another of the first cut feature layout patterns in the first direction. An integrated circuit layout including first and second conductive feature layouts and a first cut feature layout is generated.)

1. A method of generating an integrated circuit layout, the method comprising:

laying out a first conductive feature layout pattern in a cell region, wherein the first conductive feature layout pattern extends in a first direction, and the cell region has opposing first and second cell boundaries extending in a second direction different from the first direction;

laying out a second conductive feature layout pattern in the cell region, wherein the second conductive feature layout pattern extends in the first direction, and the first conductive feature layout pattern and the second conductive feature layout pattern are alternately laid out in the second direction;

laying out a plurality of first cut feature layout patterns on the first cell boundary of the cell region and on ends of the first conductive feature layout patterns, wherein one of the first cut feature layout patterns is offset in the first direction by another one of the first cut feature layout patterns; and

generating an integrated circuit layout including the first conductive feature layout pattern, the second conductive feature layout pattern, and the first cut feature layout pattern.

Technical Field

The present disclosure relates to an integrated circuit and a design system thereof and a method for forming a layout diagram thereof.

Background

The semiconductor integrated circuit industry has produced a variety of digital devices that address problems in many different areas. Some of these digital devices (such as memory macros) are configured to store data. As bulk integrated circuits become smaller and more complex, the resistance of conductive lines within these digital devices also changes, affecting the operating voltage of these digital devices and the overall integrated circuit performance.

Disclosure of Invention

According to some embodiments of the present disclosure, a method for generating an integrated circuit layout comprises: laying out a first conductive feature layout pattern in a cell region, wherein the first conductive feature layout pattern extends in a first direction, and the cell region has opposing first and second cell boundaries extending in a second direction different from the first direction; laying out a second conductive feature layout pattern in the cell region, wherein the second conductive feature layout pattern extends in the first direction, and the first conductive feature layout pattern and the second conductive feature layout pattern are alternately laid out in the second direction; laying out a plurality of first cut feature layout patterns on the first cell boundary of the cell region and on ends of the first conductive feature layout patterns, wherein one of the first cut feature layout patterns is offset in the first direction by another one of the first cut feature layout patterns; and generating an integrated circuit layout including the first conductive feature layout pattern, the second conductive feature layout pattern, and the first cut feature layout pattern.

Drawings

Aspects of the present disclosure are best understood from the following description when read with the accompanying drawing figures. It is noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1A is a diagram of a layout design according to some embodiments;

FIG. 1B is a diagram of a top view of an integrated circuit according to some embodiments;

FIG. 2A is a top view illustrating an exemplary metal 1 pattern having a first conductive structure and a first isolation portion, according to various embodiments of the present disclosure;

FIG. 2B illustrates a top view of an exemplary first patterning method, in accordance with various embodiments of the present disclosure;

FIG. 2C illustrates a top view of an exemplary second patterning method, in accordance with various embodiments of the present disclosure;

FIG. 3 is a flow diagram of a method of generating an IC layout diagram in accordance with some embodiments of the present disclosure;

FIG. 4 is a flowchart of a method M20 of designing an IC layout according to some embodiments of the present disclosure;

FIG. 5A is a diagram of a layout design according to some embodiments;

FIG. 5B is a top view of an exemplary cut feature layout pattern in accordance with a desired multi-position, in accordance with various embodiments of the present disclosure;

FIG. 5C is a top view of an exemplary cut feature layout pattern conforming to a desired multi-position, an exemplary metal 0 via pattern, an exemplary metal 1 via pattern, an exemplary M1 conductive feature layout pattern, and an M2 conductive feature layout pattern, in accordance with various embodiments of the present disclosure;

FIG. 6 is a cross-sectional view of an exemplary semiconductor structure, in accordance with various embodiments of the present disclosure;

FIG. 7 is an enlarged view of the area in FIG. 1A;

FIG. 8 is a diagram of a layout design in accordance with some embodiments;

FIGS. 9A and 9B are top views of exemplary layout designs having a plurality of standard cells, according to some embodiments;

FIG. 10A is a diagram of an exemplary layout design in accordance with some embodiments;

FIG. 10B is an enlarged view of the area in FIG. 10A;

FIG. 11 is a diagram of an exemplary layout design in accordance with some embodiments;

FIG. 12 is a block diagram of an IC device design system according to the present disclosure;

FIG. 13 is a block diagram of an IC manufacturing system and IC manufacturing processes associated therewith, in accordance with some embodiments of the present disclosure.

[ notation ] to show

A1, A2, B1, B2, ZN, A1', A2', B1', B2', ZN ', channels (patterns)

CM1A first cut feature layout Pattern set

CM1 Aa-CM 1Ae first cut feature layout pattern

CM1Aa 'to CM1Ac' first isolated fraction

CM1B second cutting feature layout Pattern group

CM1 Ba-CM 1Be second cutting feature layout pattern

CM1Ba 'to CM1Bc' second isolated fraction

D. d is the distance between

F. G is the area

L1, L2 Length

M1A' first conductive structure

M1B' second conductive structure

M10, M20 methods

H. H1-H5 height

P1, PA 1-PA 3, Pa-Pc, Pa '-Pc' with intervals

S12-S24, S32-S44

V0 a-V0 c channel (pattern)

V1 a-V1 d, V1a': channel (pattern)

W is width

100A, 300A, 500A, 700A, 800A layout design

100B integrated circuit

102 mesh wire group

102 a-102 d, 302, 502, 702, 802: grid lines

110 a-110 c, 710a, 710b, 810a, 810b standard cell layout pattern

110a '-110 c', 310a, 310b, 610 standard cells

111a, 111b, 311, 511, 711 cell boundaries

130a, 130a' a first conductive feature layout pattern group

130b, 130b' a second conductive feature layout pattern group

132a' end first conductive feature layout pattern group

140a、140a':

140b, 140b' a first conductive feature layout pattern group

150a, 150a' first conductive feature layout pattern group

150b, 150b' a second conductive feature layout pattern group

M1 Pattern 210

220 first patterning method

222. 224, 362, 364 holes

230 second patterning method

330. 430: M1 conductive feature layout pattern

330 aa-330 ad conductive feature patterns

360a, 360b, 660a, 660b, 662a, 662b, 760a, 760b, 860a, 860b to conform to the desired position

366. 566 top edge

368. 568, 876 bottom edge

372. 472, 772 channel closure

374. 474, 774 ballast bed

380. 480, 780: M2 conductive feature layout pattern

392. 396 distance

394. 398 size

400 semiconductor structure

455 structure

1200 design System

1202 processor

1204 storage medium

1206 instruction

1208 bus

1210I/O interface

1212 network interface

1214 network

1220 IC layout design

1222 design criteria

1224 producing tool

1300 IC manufacturing system

1320 design company

1322 IC design layout

1330 mask manufacturing Ltd

1332 data prepare operation

1344 manufacture of shadow mask

1345 mask

1350 IC manufacturer/factory

1352 wafer production operation

1353, wafer

1360 manufacturing IC device

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, the formation of a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, in various instances, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Also, for convenience of description, spatially relative terms such as "below," "lower," "above," "higher," and the like may be used herein to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of an element in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, "about," "approximately," or "approximately" generally means within twenty percent, or within ten percent, or within five percent of a given value or range. Numerical values set forth herein are approximate, meaning that the term "about", "approximately", or "approximately" can be inferred if not expressly stated.

In various embodiments of the present disclosure, a dual pattern layout design with offset cut patterns in a single shadow mask is provided. The offset cut pattern in the single mask allows for increased metal 2(M2) stitch access capability of the circuit layout, thereby increasing routing flexibility, as illustrated by the non-limiting examples provided below. A pin access point is a location where a conductive feature (e.g., the M2 line) may be connected to another conductive feature (e.g., the M1 line). The number of access points plays a role in determining the wiring capability, such as wiring density, and wiring flexibility.

Devices having cell structures incorporated therein are provided below according to various embodiments. Some variations of some embodiments are discussed. Like elements are designed with like reference numerals throughout the various views and illustrative embodiments for ease of understanding.

FIG. 1A is a diagram of a layout design 100A according to some embodiments. Layout design 100A is a layout diagram of integrated circuit 100B of FIG. 1B, which is a simplified diagram of a top view of integrated circuit 100B according to some embodiments. The layout design 100A may be used to fabricate an integrated circuit, such as the integrated circuit 100B of FIG. 1B. In some embodiments, layout design 100A includes other elements not illustrated in FIG. 1A. In addition to the layout design 100A, FIG. 1A also depicts the X-axis and Y-axis directions.

The layout design 100A includes a standard cell layout pattern 110A, and portions of the standard cell layout patterns 110b and 110 c. The standard cell layout pattern 110a is between the standard cell layout patterns 110b and 110c, and the standard cell layout patterns 110b, 110a, and 110c are laid out in the Y-axis direction. The cell boundary 111a is between the standard cell layout patterns 110a and 110b, and the cell boundary 111b is between the standard cell layout patterns 110a and 110 c. A cell area is defined between cell boundaries 111a and 111b, and a standard cell layout pattern 110a is in the cell area. The standard cell layout patterns 110a, 110B, and 110c may be used to fabricate the corresponding standard cells 110a ', 110B ', and 110c ' of the integrated circuit 100B of fig. 1B. In some embodiments, the term "standard cell" as discussed above is referred to as an electrical component configured to provide logic-based functionality, storage functionality, or the like.

In some embodiments, one or more of the standard cell layout patterns 110a, 110b, and 110c are layout designs of logic gate cells. In some embodiments, the logic gate units include AND, OR, NAND, NOR, XOR, INV, AND-OR-Invert (AOI), OR-AND-Invert (OAI), MUX, flip-flop, BUFF, latch, delay, OR clock units. In some embodiments, one or more of the standard cell layout patterns 110a, 110b, and 110c are a layout design of memory cells. In some embodiments, the memory cell comprises Static Random Access Memory (SRAM), dynamic ram (dram), resistive ram (rram), magnetoresistive ram (mram), or Read Only Memory (ROM). In some embodiments, one or more of the standard cell layout patterns 110a, 110b, and 110c include a layout design of one or more active or passive components. Examples of active elements include, but are not limited to, transistors and diodes. Examples of transistors include, but are not limited to: metal Oxide Semiconductor Field Effect Transistors (MOSFETs), Complementary Metal Oxide Semiconductor (CMOS) transistors, Bipolar Junction Transistors (BJTs), high voltage transistors, high frequency transistors, p-channel and/or n-channel field effect transistors (PFETs/NFETs), etc.), finfets, and planar MOS transistors with high source/drain. Examples of passive components include, but are not limited to, capacitors, inductors, fuses, and resistors.

In some embodiments, the layout design 100A includes the set of grid lines 102, the first set of cut feature layout patterns CM1A, the second set of cut feature layout patterns CM1B, the first set of conductive feature layout patterns 130A, the second set of conductive feature layout patterns 130b, the first set of conductive feature layout patterns 140A, the first set of conductive feature layout patterns 140b, the first set of conductive feature layout patterns 150A, and the second set of conductive feature layout patterns 150 b. For example, as shown in fig. 1A, CM1A corresponds in part to first cut feature layout patterns CM1Aa, CM1Ab, CM1Ac, CM1Ad, and CM1Ae, and CM1B corresponds in part to second cut patterns CM1Ba, CM1Bb, CM1Bc, CM1Bd, and CM1Be, M1A corresponds in part to first conductive feature layout patterns 130a, 140a, and 150a, and M1B corresponds in part to second conductive feature layout patterns 130b, 140b, and 150 b. The standard cell layout pattern 110a includes a first conductive feature layout pattern 130a and a second conductive feature layout pattern 130b, the standard cell layout pattern 110b includes a first conductive feature layout pattern 140a and a second conductive feature layout pattern 140b, and the standard cell layout pattern 110c includes a first conductive feature layout pattern 150a and a second conductive feature layout pattern 150 b.

Each grid line 102 extends in the X-axis direction. The grid line group 102 includes at least grid lines 102a, 102b, 102c, and/or 102 d. Each mesh line in the mesh line group 102 is separated from the adjacent mesh line of the mesh line group 102 in the Y-axis direction by an interval P1. In some embodiments, each grid line 102a, 102b, 102c, 102d in the set of grid lines 102 defines an area in which a respective conductive feature layout pattern extending in the X-axis direction is located. In some embodiments, the grid line groups 102 are also referred to as wire trace groups. In some embodiments, the conductive feature layout pattern 102 on the grid line group corresponds to a metal 2(M2) conductive feature layout pattern. The M2 conductive feature layout pattern is located on a second layout level. In some embodiments, the second layout level is the M2 layout level.

The first and second conductive feature layout pattern groups 130, 130b, 140a, 140b, 150a, and 150b extend in the Y-axis direction. The first conductive feature layout pattern group 130a, 140a, and 150a will be formed on the same mask of the mask groups, and the second conductive feature layout pattern group 130b, 140b, and 150b will be formed on different masks of the mask groups. Accordingly, the first and second conductive feature layout patterns 130a, 130b, 140a, 140b, 150a, and 150b are referred to as sub-patterns. Each of the first and second conductive feature layout pattern groups 130a, 130b, 140a, 140b, 150a, and 150b includes at least one conductive feature layout pattern. The first and second conductive feature layout pattern groups 130a, 130b, 140a, 140b, 150a, and 150b are located at a first layout level. In some embodiments, the first layout level is a metal 1(M1) layout level. In some embodiments, the M1 layout level is below the M2 layout level. The first and second sets of conductive feature layout patterns 130a, 130B, 140a, 140B, 150a, and 150B may be used to fabricate respective first and second sets of conductive structures 130a ', 130B', 140a ', 140B', 150a ', and 150B' of the integrated circuit 100B (fig. 1B).

In some embodiments, the first and second conductive feature layout patterns (130b or 130a) pass through at least the grid lines 102a, 102b, 102c, or 102 d. In some embodiments, the first set of conductive feature layout patterns 130A and the second set of conductive feature layout patterns 130b intersect other underlying layout patterns (not shown) of other layout levels (e.g., MD, M0, or the like) of the layout design 100A.

In some embodiments, each first conductive feature layout pattern 130a is separated from an adjacent first conductive feature layout pattern 130a by a pitch Pa in the X-axis direction, and each second conductive feature layout pattern 130b is separated from an adjacent second conductive feature layout pattern 130b by a pitch Pb in the X-axis direction. The pitch Pb may be substantially the same as the pitch Pa. In some embodiments, for an EUV mask, the spacing Pa and/or Pb is in a range from about 24 nanometers to about 60 nanometers. In the X-axis direction, the first conductive feature layout patterns 130a and the second conductive feature layout patterns 130b are alternately arranged such that a pitch Pc between adjacent first conductive feature layout patterns 130a and second conductive feature layout patterns 1130b is smaller than a pitch pa (pb). For example, pitch Pc is about half of pitch Pa (Pb). In some embodiments, pitch Pc is in the range of about 18 nanometers to about 30 nanometers. Other arrangements or numbers of patterns in the first set of conductive feature layout patterns 130a and the second set of conductive feature layout patterns 130b are within the scope of the present disclosure.

The first cut feature layout pattern group CM1A extends in the X-axis direction. The first cut feature layout pattern group CM1A includes at least first cut feature layout patterns CM1Aa, CM1Ab, CM1Ac, CM1Ad, and CM1 Ae. Each center of the first cut feature layout patterns CM1Aa, CM1Ab, CM1Ac, CM1Ad, and CM1Ae is spaced apart from an adjacent first cut feature layout pattern in the X-axis direction by a distance substantially equal to n times the pitch Pa, where n is a positive integer. For example, the center of the first cut feature layout pattern CM1Aa is separated from the center of the first cut feature layout pattern CM1Ab by about 2 times Pa in the X-axis direction, and the center of the first cut feature layout pattern CM1Aa is separated from the center of the first cut feature layout pattern CM1Ac by about 3 times Pa in the X-axis direction. The first cut feature layout pattern group CM1A is located on a first layout level. In some embodiments, the first cut feature layout patterns CM1Aa and CM1Ab are located on the cell boundary 111a, but are offset from each other in the Y-axis direction. That is, the first cut feature layout patterns CM1Aa and CM1Ab are misaligned. Similarly, the first cut feature layout patterns CM1Aa and CM1Ac are located on the cell boundary 111a, but are offset from each other in the Y-axis direction. In addition, the first cut feature layout patterns CM1Ad and CM1Ae are located on the cell boundary 111b and are aligned with each other.

The first cut feature layout pattern CM1Aa is separated from the first cut feature layout pattern CM1Ad by a pitch PA1 in the Y-axis direction, and the first cut feature layout pattern CM1Ac is separated from the first cut feature layout pattern CM1Ae by a pitch PA2 in the Y-axis direction. In some embodiments, as shown in FIG. 1A, pitch PA2 is different from pitch PA 1. For example, pitch PA2 is greater than pitch PA 1. For example, the difference between the pitches PA1 and PA2 is smaller than the width W of the first cut feature layout pattern CM1Aa (see fig. 7). That is, the first cut feature layout pattern CM1Ab is offset from the first cut feature layout pattern CM1Aa in the Y-axis direction by an offset distance (PA 2-PA1) that is smaller than the width W of the first cut feature layout pattern CM1 Aa.

The second cutting feature layout pattern group CM1B extends in the X-axis direction. The second cut feature layout pattern group CM1B includes at least second cut feature layout patterns CM1Ba, CM1Bb, CM1Bc, CM1Bd, and CM1 Be. The second cutting feature layout pattern group CM1B is located on the first layout level. In some embodiments, the second cut feature layout patterns CM1Ba, CM1Bb, and CM1Bc are located on the cell boundary 111a and aligned with each other. That is, the second cut feature layout patterns CM1Ba, CM1Bb, and CM1Bc are aligned along the X-axis direction. In addition, the second cut feature layout patterns CM1Bd and CM1Be are located on the cell boundary 111b and aligned with each other.

The second cut feature layout patterns CM1Ba, CM1Bb, and CM1Bc may be substantially aligned with the first cut feature layout pattern CM1 Aa. That is, the second cut feature layout patterns CM1Ba, CM1Bb, and CM1Bc may be shifted (misaligned) in the Y-axis direction by the first cut feature layout patterns CM1Ab and CM1 Ac. In some embodiments, the second cut feature layout pattern CM1Bc overlaps the first cut feature layout pattern CM1Ab and/or CM1Ac, as shown in fig. 1A. The second cut feature layout pattern CM1Bb is separated from the second cut feature layout pattern CM1Bd in the Y-axis direction by a pitch PA 3. In some embodiments, pitch PA3 is different from pitch PA2, but substantially the same as pitch PA 1.

The first cut feature layout pattern group CM1A is to be formed on the same mask of the plurality of mask groups, and the second cut feature layout pattern group CM1B is to be formed on another mask of the plurality of mask groups. Therefore, the first and second cut feature layout patterns CM1A and CM1B are referred to as sub-patterns. In some embodiments, the first cut feature layout pattern CM1a, CM1Ab, CM1Ac, CM1Ad, and CM1Ae identifies respective locations of the respective first isolation portions CM1Aa ', CM1Ab', CM1Ac ', CM1Ad', and CM1Ae 'of the first conductive structures 130a', 140a ', and/or 150a' (see fig. 1B) that were removed in the cut metal process. In some embodiments, the second cut feature layout pattern CM1a, CM1Bb, CM1Bc, CM1Bd, and CM1Be identifies respective locations of the respective second isolation portions CM1Ba ', CM1Bb', CM1Bc ', CM1Bd', and CM1Be 'of the second conductive structures 130B', 140B ', and/or 150B' (see fig. 1B) that were removed in the cut metal process. For example, at least one of the first conductive structures 130a 'has an end 132a' facing the standard cell 110b ', and the first isolation portion CM1a' abuts the end 132a 'of the first conductive structure 130 a'.

In some embodiments, the layout design 100A further includes metal 0 via patterns a1, a2, B1, B2, and ZN, and metal 1 via patterns V1a (only one labeled for clarity). For example, as shown in fig. 1A, a portion V0 corresponds to metal 0 channel patterns a1, a2, B1, B2, and ZN, and a portion V1 corresponds to metal 1 channel pattern V1A. The metal 0 channels a1, a2, B1, B2, and ZN identify the respective locations of the respective metal 0 channels a1', a2', B1', B2', and ZN 'in fig. 1B, and the metal 1 channel patterns a1, a2, B1, B2, and ZN identify the respective locations of the respective metal 1 channels V1 a'. For example, as shown in fig. 1B, the V0 'portion corresponds to metal 0 channel patterns a1', a2', B1', B2', and ZN', and the V1 'portion corresponds to metal 1 channel V1 a'. Each of the metal 0-channel patterns a1', a2', B1', B2', and ZN 'is configured to interconnect the first or second conductive structures 130a', 130B ', 140a', 140B ', 150a', or 150B 'and an underlying structure (e.g., MD, M0, or the like), and each of the metal 1-channels V1a' is configured to interconnect the first or second conductive structures 130a ', 130B', 140a ', 140B', 150a ', or 150B' and the M2 conductive structures.

Refer to fig. 1B. In fig. 1B, the same or similar components as one or more of fig. 1A, 2A to 2C, and 5A to 11 are assigned the same or similar reference numerals (as shown below), and thus detailed descriptions thereof are omitted. The integrated circuit 100B is fabricated by the layout design 100A of fig. 1A. The structural relationships, including the positioning and alignment, of the integrated circuit 100B of fig. 1B are similar to the corresponding structural relationships and corresponding configurations of the layout design 100A of fig. 1A, and for the sake of brevity, similar detailed descriptions will not be described again in fig. 1B, 2A-2C, and 5A-11.

The integrated circuit 100B includes standard cells 110a ', 110B ', and 110c '. In some embodiments, one or more of the standard cells 110a ', 110b ', and 110c ' are logic gate cells. In some embodiments, one or more of the standard cells 110a ', 110b ', and 110c ' are memory cells. In some embodiments, one or more of the standard cells 110a ', 110b ', and 110c ' include active or passive elements.

In some embodiments, the integrated circuit 100B includes a first set of isolation portions CM1A ', a second set of isolation portions CM1B', a first set of conductive structures 130a ', a second set of conductive structures 130B', a first set of conductive structures 140a ', a second set of conductive structures 140B', a first set of conductive structures 150a ', and a second set of conductive structures 150B' (described below). For example, as shown in fig. 1B, CM1A 'corresponds in part to first isolation portions CM1Aa', CM1Ab ', CM1Ac', CM1Ad ', and CM1Ae', CM1B 'corresponds in part to second isolation portions CM1Ba', CM1Bb ', CM1Bc', CM1Bd ', and CM1Be', and M1A 'corresponds in part to first conductive structures 130a', 140a ', and 150a', and M1B 'corresponds in part to second conductive structures 130B', 140B ', and 150B'.

In some embodiments, the integrated circuit 100B further includes cell boundaries 111a 'and 111B'. In some embodiments, the cell boundaries 111a ' and 111b ' do not overlap the gate structures of the standard cells 110a ', 110b ', and/or 110c '. The cell boundaries 111a ' and 111b ' extend in the X-axis direction, while the gate structures of the standard cells 110a ', 110b ', and/or 110c ' extend in the Y-axis direction.

Each of the first conductive structures 130a 'and the second conductive structures 130b' includes a plurality of conductive structures. Each of the first conductive structure group 140a 'and the second conductive structure group 140b' includes a plurality of conductive structures. Each of the first conductive structure group 150a 'and the second conductive structure group 150b' includes a plurality of conductive structures. In some embodiments, the first and second conductive structures 130a ', 130B', 140a ', 140B', 150a ', and 150B' are on the M1 layer of the integrated circuit 100B.

Each first conductive structure 130a is spaced apart from an adjacent first conductive structure 130a by a spacing Pa 'in the X-axis direction, and each second conductive structure 130b is spaced apart from an adjacent second conductive structure 130b by a spacing Pb' in the X-axis direction. The pitch Pb 'may be substantially the same as the pitch Pa'. In some embodiments, for an EUV mask, the spacing Pa 'and/or Pb' is in a range from about 24 nanometers to about 60 nanometers. In the X-axis direction, the first conductive structures 130a ' and the second conductive structures 130b ' are alternately arranged such that a pitch Pc ' between adjacent first conductive structures 130a ' and second conductive structures 130b ' is smaller than a pitch Pa ' (Pb '). For example, the pitch Pc ' is about half of the pitch Pa ' (Pb '). In some embodiments, pitch Pc is in the range of about 18 nanometers to about 30 nanometers. Other arrangements or numbers of patterns in the first set of electrical structures 130a 'and the second set of electrical structures 130b' are within the scope of the present disclosure.

The first conductive structure 130a ' is separated from the first conductive structure 140a ' by a first isolation portion CM1Aa ', CM1Ab ', or CM1Ac '. In some embodiments, first isolation portions CM1Aa ' and CM1Ab ' are on opposite sides of cell boundary 111a '. The first conductive structure 130a 'is separated from the first conductive structure 150a' by a first isolation portion CM1Ad 'or CM1 Ae'. The second conductive structure 130b ' is separated from the second conductive structure 140b ' by a second isolation portion CM1Ba ', CM1Bb ', or CM1Bc '. The second conductive structure 130b 'is separated from the second conductive structure 150b' by a second isolation portion CM1Bd 'or CM1 Be'.

In fig. 1A and 1B, because the first and second cut feature layout patterns correspond to separate mask sets, the first cut feature layout pattern CM1A defines a first isolation portion CM1A 'of the first conductive structure M1A' (e.g., 130a ', 140a', and/or 150a '), such first conductive structure M1A' is independent of the second isolation portion CM1B 'of the second conductive structure M1B', and the second cut feature layout pattern CM1B defines a second isolation portion CM1B 'of the second conductive structure M1B' (e.g., 130B ', 140B', and/or 150B '), such second isolation portion CM1B' is independent of the first isolation portion CM1A 'of the first conductive structure M1A'.

In some embodiments, at least one of the first and second conductive structure groups 130a ', 130b', 140a ', 140b', 150a ', and 150b' comprises one or more layers of metallic material, such as aluminum, copper, tungsten, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, other suitable conductive materials, or combinations thereof. In some embodiments, at least one of the first and second isolation portion groups CM1A ', CM1B' includes one or more layers of dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric material, other suitable dielectric material, or combinations thereof. In some embodiments, at least one of the vias a1', a2', B1', B2', ZN ', and/or V1a' comprises one or more layers of metallic material, such as aluminum, copper, tungsten, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, other suitable conductive materials, or combinations thereof.

According to various embodiments of the present disclosure, fig. 2A illustrates a top view of an exemplary M1 pattern 210, the exemplary M1 pattern 210 having a first conductive structure 130a 'and a first isolation portion CM 1A'. The closer the first isolated portions CM1A' are in contact with each other, the greater the number of access points for the wiring, without contact (because of electrical shorts caused by contact of these conductive structures). Fig. 2B illustrates a top view of an exemplary first patterning method 220, according to various embodiments of the present disclosure. In some embodiments, the first patterning method is square hole push (square hole). In other words, a plurality of holes (or circles) are generated on one end of each first conductive structure 130a' (e.g., holes 222, 224, respectively) using an Ultraviolet (UV) mask or Extreme Ultraviolet (EUV) lithography process. The spacing D (e.g., center-to-center spacing between the holes 222, 224) may be minimized to increase the number of routing access points for the integrated circuit 100B (see fig. 1B). In some embodiments, the minimum separation D may be between about 35 nanometers and about 45 nanometers. The spacing D may be specified by the type of mask used during etching and/or the etch design rules. Fig. 2C illustrates a top view of an exemplary second patterning method 230, in accordance with various embodiments of the present disclosure. In some embodiments, the second patterning method is directional or lateral etching. Lateral etching is performed on each side of the holes 222, 224 to laterally increase the size of the holes (e.g., the X-axis direction shown in fig. 1B and the horizontal direction illustrated in fig. 2C). The combination of the square push hole etch in fig. 2B with the directional or lateral etch in fig. 2C may achieve the M1 pattern 210 in fig. 2A. It should be noted that the processes shown in fig. 2A to 2C can be applied to the second conductive structure 130B 'and the second isolation portion CM1B' shown in fig. 1B.

In fig. 1A, the first cut feature layout patterns CM1A may be offset from each other, thus increasing the stitch access capability of M2 on the cell boundary. For example, since the first cut feature layout pattern CM1Ab is offset from the first cut feature layout pattern CM1Aa, an additional metal 1 channel pattern V1a may be placed on the grid lines 102a to increase the access points of the M2 pin. For example, the pin access points of layout design 100A have increased utilization by about 2% compared to a layout design that does not use an offset feature layout pattern. In addition, multiple positions of the first cut feature layout pattern CM1A may be used, and the space between two positions in the Y-axis direction may be small, even overlapping. In fig. 1B, since the first isolation portion CM1A ' is formed by directional etching, adjacent first isolation portions CM1A ' are not merged, and the corner rounding problem at the edge of the first conductive structure 130a ' (e.g., the edge 132 shown in fig. 2A) may be improved or avoided. In some other embodiments, the configuration of the second cut feature layout pattern CM1B, the second isolation portion CM1B ', and/or the second conductive structure 130b' (e.g., fig. 8) is similar to the configuration of the first cut feature layout pattern CM1A, the first isolation portion CM1A ', and/or the first conductive structure 130a', and thus, a description related thereto will not be repeated later.

Fig. 3 is a flowchart of a method M10 of generating an IC layout diagram, according to some embodiments of the present disclosure. In some embodiments, the step of generating the IC layout includes generating one of the layouts 100A, 300A, 500A, 700A, and 800A corresponding to an IC structure, such as one of the layout structures 100B fabricated based on the generated IC layout discussed above with reference to fig. 1A and 1B and below with reference to fig. 5A-5C, 7-8, and 10A-11. In some embodiments, the step of generating the IC layout is operating a portion of an IC manufacturing system as part of manufacturing an IC device (e.g., a memory circuit, a logic device, a processing device, a signal processing circuit, or the like).

In some embodiments, some or all (steps) of method M10 are performed by a processor of a computer. In some embodiments, discussed below with reference to fig. 12, some or all (steps) of method M10 are performed by processor 1202 of IC device design system 1200. Some or all of the operations of method M10 may be performed as part of a design program that is performed in a design company, such as design company 1320 discussed below with reference to fig. 13.

In some embodiments, the operations of method M10 are performed in the order depicted in FIG. 3. In some embodiments, the operations of method M10 are performed simultaneously and/or in an order other than the order depicted in FIG. 3. In some embodiments, one or more operations are performed before, during, and/or after performing one or more operations of method M10.

At operation S12, a first conductive feature layout pattern is laid out in the cell region. In some embodiments, the step of laying out the first conductive feature layout pattern includes laying out the first conductive feature layout pattern corresponding to the first conductive feature layout patterns 130a, 140a, and/or 150 discussed above with reference to fig. 1A in the region of the standard cell layout patterns 110a, 110b, and/or 110 c. In some embodiments, for an EUV mask, the first conductive feature layout pattern has a pitch in a range of about 24 nanometers to about 60 nanometers.

At operation S14, a second conductive feature layout pattern is laid out in the cell region. In some embodiments, the step of laying out the second conductive feature layout pattern includes laying out a second conductive feature layout pattern corresponding to the second conductive feature layout patterns 130b, 140b, and/or 150b discussed above with reference to fig. 1A. In some embodiments, for an EUV mask, the second conductive feature layout pattern has a pitch in a range of about 24 nanometers to about 60 nanometers. In some embodiments, the first conductive feature layout pattern and the second conductive feature layout pattern are alternately laid out such that a pitch in a range of about 18 nanometers to about 30 nanometers is formed between adjacent first conductive feature layout patterns and second conductive feature layout patterns.

At operation S16, first cut feature layout patterns are laid out on cell boundaries of the cell region, wherein at least two first cut feature layout patterns are offset from each other. In some embodiments, the step of laying out the first cut feature layout pattern includes laying out the first cut feature layout pattern corresponding to the first cut feature layout pattern CM1A on the cell boundary 111A corresponding to that discussed above with reference to fig. 1A.

At operation S18, a second cut feature layout pattern is laid out on the cell boundary of the cell region. In some embodiments, the step of laying out the second cut feature layout pattern includes laying out the second cut feature layout pattern corresponding to the second cut feature layout pattern CM1B on the cell boundary 111A corresponding to the cell boundary discussed above with reference to fig. 1A. In some embodiments, the at least two second cut feature layout patterns may be offset from each other.

At operation S20, in some embodiments, an IC map is generated. The IC layout includes a first conductive feature layout pattern, a second conductive feature layout pattern, a first cut feature layout pattern, and a second cut feature layout pattern laid out as discussed above with reference to operations S12-S18.

In some embodiments, the step of generating the IC layout comprises storing the IC layout in a storage device. In various embodiments, storing the IC layout in the storage device includes storing the IC layout in a non-volatile, computer-readable memory or cell library (e.g., a database), and/or storing the IC layout on a network. In some embodiments, discussed below with reference to fig. 12, the step of storing the IC layout in the storage device comprises storing the IC layout on the network 1214 of the IC device design system 2700.

At operation S22, in some embodiments, at least one of the one or more semiconductor masks, or at least one component in a semiconductor IC layer, is produced based on the IC layout. The step of producing at least one semiconductor mask of the one or more semiconductor masks or at least one component in a semiconductor IC layer is discussed below with reference to fig. 13.

At operation S24, in some embodiments, one or more manufacturing operations are performed based on the IC layout. In some embodiments, performing one or more manufacturing operations includes performing one or more lithographic exposures based on the IC layout. The following discusses, with reference to fig. 13, (steps of) performing one or more (e.g., one or more lithographically exposed) fabrication operations based on the IC layout.

By performing some or all of the operations of method M10, an IC layout and corresponding IC device are generated (e.g., as discussed above with reference to fig. 1A-1B), with various embodiments including stacked transistors with source/drain offset along the gate direction, thereby improving access to the gate/gate and increasing routing flexibility compared to the manner in which source/drain are not offset along the gate direction.

FIG. 4 is a flowchart of a method of designing an IC layout M20 according to some embodiments of the present disclosure. In some embodiments, the step of designing the IC layout includes designing one of the layouts 100A, 300A, 500A, 700A, and 800A corresponding to an IC structure, based on the generated IC layout, such as one of the layout 100B fabricated based on the generated IC layout discussed above with reference to fig. 1A and 1B and below with reference to fig. 5A-5C, 7-8, and 10A-11. In some embodiments, the step of designing the IC layout is operating a portion of an IC manufacturing system as part of manufacturing an IC device (e.g., a memory circuit, a logic device, a processing device, a signal processing circuit, or the like).

In some embodiments, some or all (steps) of method M20 are performed by a processor of a computer. In some embodiments, discussed below with reference to fig. 12, some or all of method M20 (step) is performed by processor 1202 in IC device design system 2700. Some or all of the operations of method M20 may be performed as part of a design program that is performed in a design company (e.g., design company 1320 discussed below with reference to fig. 13).

In some embodiments, the operations of method M20 are performed in the order depicted in FIG. 4. In some embodiments, the operations of method M20 are performed simultaneously and/or in an order other than the order depicted in FIG. 4. In some embodiments, one or more operations are performed before, during, and/or after performing one or more operations of method M20.

FIG. 5A is a diagram of a layout design 300A according to some embodiments. Method M20 of FIG. 4 may be used to design layout design 300A of FIG. 5A. In FIG. 5A, the layout design 300A includes standard cells 310A and 310b that are adjacent to each other. Cell boundary 311 is located between standard cells 310a and 310 b.

At operation S32 of method M20 of fig. 4, parameters of the IC layout are determined. In fig. 5A, the parameters include the cell height H1 of the standard cell 310a and the cell height H2 of the standard cell 310b, the metal pitch (e.g., M1 pitch Pa, and/or M2 pitch P1 shown in fig. 5A), and/or the width W of the first cut feature layout pattern and/or the second cut feature layout pattern (e.g., the first cut feature layout pattern CM1 Af).

At operation S34 of method M20 in fig. 4, M2 trajectory planning is performed to find possible pin access problems. In this operation, the positioning of the M2 conductive feature layout pattern (i.e., the M2 routing traces) is determined, and the locations of the pin accesses of the M2 conductive feature layout pattern are also designed. The M2 conductive feature layout pattern is located on the grid line 302, and the pin access location is the location where the metal 1 channel pattern falls on the first conductive feature layout pattern (i.e., the M1 conductive feature layout pattern).

In fig. 5A, a pin access problem may occur in region E, which is located at cell boundary 311 of standard cells 310a and 310 b. The possible stitch access problem may arise because the predetermined position of the cut feature layout pattern (e.g., the cut feature layout pattern CM1Af) overlaps the predetermined position of the metal 1 channel pattern, such that the metal 1 channel pattern cannot fall on the predetermined position. If the metal 1 via pattern falls on other locations, the chip area of layout design 300A may be increased. To solve this problem, the cut feature layout pattern CM1Af may be offset at a predetermined position in the Y-axis direction, and the metal 1 channel pattern may fall at its predetermined position.

At operation S36 of method M20 of fig. 4, a multi-position of the cut feature layout pattern is determined based on the etch mask rules. In particular, this operation checks whether the cut feature layout pattern can be moved (shifted) in the Y-axis direction according to the etch mask rules. Referring to fig. 5B, an exemplary cut feature layout pattern is conformed to a top view of a desired multi-position according to various embodiments of the present disclosure. In fig. 5B, it is assumed that the cut feature layout pattern has two desired locations 360a and 360B, i.e., the cut feature layout pattern can be positioned on the desired locations 360a or 360B. The desired position 360a is a predetermined position and the desired position 360b is offset by a new position corresponding to the desired position 360 a. For example, as shown in fig. 5B, a cut feature layout pattern CM1Af is positioned on the conforming desired position 360a, and another cut feature layout pattern CM1Ag is positioned on the conforming desired position 360B. The cut feature layout pattern CM1Af is at an end of the conductive feature layout pattern 330aa, while the cut feature layout pattern CM1Ag is at an end of another conductive feature layout pattern 330ab adjacent to the conductive feature pattern 330 aa. The conductive feature layout patterns 330aa and 330ab have a pitch Pa.

According to the process shown in fig. 2B, two holes 362 and 364 are formed at the desired locations 360a and 360B, respectively, in order to form isolation portions corresponding to the cut feature layout patterns CM1Af and CM1 Ag. A spacing D is formed between the two holes 362 and 364 such that the holes 362 and 364 do not merge together. In some embodiments, the spacing D is about 35 nanometers to about 45 nanometers, or about 39 nanometers to about 42 nanometers for an EUV mask. Since the pitch Pa and the width W of the cut feature layout patterns CM1Af and CM1Ag are determined in operation S32, and the pitch D is determined by the (EUV) etching limit, the cutting space D between the two desired positions 360a and 360b can be determined by the following equation:

wherein the desired cutting space d corresponds to the distance between the desired positions 360a and 360 b. In particular, the desired cutting space d is defined by a top edge 366 corresponding to the desired position 360a and a bottom edge 368 corresponding to the desired position 360 b. If the cutting space required is positive, the positions 360a and 360b required are spaced from each other; if the coincidence required cutting space d is a negative value, the coincidence required positions 360a and 360b overlap each other. If equation (1) is satisfied, the cut feature layout pattern may be offset from the predetermined position.

At operation S38 of method M20 of fig. 4, a multi-position location is determined based on the parameters of the metal 1 via, the metal 0 via, and the IC layout. In particular, this operation determines the positioning in multiple positions in the presence of metal 1 channels and metal 0 channels. Referring to fig. 6, a cross-sectional view of an exemplary semiconductor structure 400 according to various embodiments of the present disclosure is shown. In fig. 6, the semiconductor structure includes a M1 conductive structure 430, a metal 0 via V0b, and a metal 1 via V1 b. Metal 0 via V0b is below M1 conductive structure 430, and metal 1 via V1b is above M1 conductive structure 430. Metal 0 via V0b is configured to interconnect M1 conductive structure 430 with a structure 455 (such as MD, M0, or the like) underlying M1 conductive structure 430, while metal 1 via V1b is configured to interconnect M1 conductive structure 430 with M2 conductive structure 480. In some embodiments, the vias V1b and V0b are sloped downward due to the etching process. To ensure sufficient etch space on the top side, channel closures 472 are defined on either side of the metal 0 channel V0 b. In addition, to ensure sufficient etch space on the bottom side, channel mesas 474 are defined on either side of the metal 1 channel V1 b.

Fig. 5C is a diagram of a desired multi-position of an exemplary cut feature layout pattern CM1Ah, an exemplary metal 0 channel pattern V0C, an exemplary metal 1 channel pattern V1C, exemplary M1 conductive feature patterns 330ac and 330ad, and an M2 conductive feature layout pattern 380, according to various embodiments of the present disclosure. The metal 0 via pattern V0c is separated from the cell boundary 311 by a distance 392, the distance 392 being determined by the distance between the cell boundary 311 and the underlying structure (such as MD, M0, or the like) of the M1 conductive structure 330 ad. Metal 0 via pattern V0c has dimension (length, width, or diameter) 394 and via closure 372. The metal 1 via pattern V1c is separated from the cell boundary 311 by a distance 396, the distance 396 is determined by the distance between the cell boundary 311 and the M2 conductive feature layout pattern 380. Metal 1 channel pattern V1c has a dimension (length, width, or diameter) 398 and channel lands 374. The sum of distances 392 and 396 is equal to the sum of half of the dimension 394 of channel V0c, channel closure 372, width W of conforming desired location 360b (i.e., the width of cut feature pattern CM1 Ah), channel landing 374, and half of the dimension 398 of channel V1 c. Since parameters 392, 396, 394, 398, and W are known, the sum of channel closure 372 and channel plateau 374 is obtained from the above relationship. The desired cutting space d may be obtained from the sum of the channel closure 372 and the channel platform 374, as will be described in fig. 7. The fit-to-desired cutting space d is a parameter for adjusting the proper position for the channel closure 372 and the channel platform 374 to fit-to-desired positions 360a and 360 b.

After it is decided by operation S38 that the required cutting space d is met, this value is substituted into equation (1) to check whether equation (1) is satisfied. This rule works if equation (1) is satisfied. In other words, two desired locations with the desired cutting spaces d are determined in the layout design 300A.

At operation S40 of method M20 in fig. 4, the positioning of standard cells of the IC layout is determined according to the required cutting space obtained above. At operation S42 of method M20 in fig. 4, clock tree synthesis is performed after operation S40. For example, in this operation, the positioning of the clock elements of the IC layout is determined. At operation S44 of method M20 in fig. 4, routing of an IC layout is performed. For example, in this operation, wirings for connecting the standard cells and the clock elements to each other are designed/determined. After operation S44, an IC layout is generated as shown in operation S20 of fig. 3.

The method M20 in FIG. 4 can be applied to the layout 100A in FIG. 1A to find the location corresponding to the desired cutting space and the desired position. Referring to fig. 1A and 7, fig. 7 is an enlarged view of a region F in fig. 1A. In some embodiments, the cell height H of the standard cell layout pattern 110a is about 110 nm, the pitch Pa (or Pb) is about 52 nm, the pitch P1 is about 24 nm, and the width W of the first cut feature layout pattern CM1A is about 12 nm. In this case, the distance 192 between the metal 0 channel a2 and the cell boundary 111a is about 28 nanometers, the distance 196 between the metal 1 channel V1a and the cell boundary 111a is about 13 nanometers, the dimension (length, width, or diameter) 194 of the metal 01 channel V1a is about 9 nanometers, and the dimension (length, width, or diameter) 198 of the metal 01 channel V1a is about 13 nanometers. The sum of the channel closures 172 and channel plateaus 174 is approximately 18.5 nanometers, according to the relationship shown in operation S38. In some embodiments, channel closures 172 are set at about 12 nanometers (such that channel plateaus 174 are about 6.5 nanometers) and distance 199 is about 28.5 nanometers. Comparing distance 199 (i.e., about 28.5 nanometers) to distance 192 (i.e., about 28 nanometers) yields a desired cutting space d of about-0.5 nanometers. This value (-0.5 nm) is then substituted into equation (1) and equation (1) is satisfied.

The result means that the cut feature layout pattern CM1Ab can be moved from the level aligned with the cut feature layout pattern CM1Aa in the Y-axis direction to the orientation shown in fig. 1A, and the channel V1A can be positioned on the grid lines 102a with sufficient channel plateau 174 (about 6.5 nanometers). In addition, the first conductive feature layout pattern 130a has a minimum length L1 of about 83.5 nanometers, which is L1 greater than the minimum length requirement of the metal traces.

FIG. 8 is a diagram of a layout design 500A, according to some embodiments. The difference between the layout design 500A in fig. 8 and the layout design 100A in fig. 1A is related to the positioning of the first cut feature layout pattern and the second cut feature layout pattern. In fig. 8, one of the second cut feature layout patterns (e.g., CM1Bg) is offset from another one of the second cut feature layout patterns (e.g., CM1Bf) in the Y-axis direction. The top edge 566 of the second cut feature layout pattern CM1Bf is substantially aligned with the cell boundary 511, and the bottom edge 568 and the cell boundary 511 form a desired cut space d of about-0.5 nm. So configured, the metal 1 channel pattern V1d can be positioned on the cell boundary 511 adjacent to the grid lines 502 to save chip area. Other relevant structural details of layout design 500A are similar to layout design 100A, and therefore, the description hereafter will not be repeated.

Fig. 9A and 9B are top views of exemplary layout designs having a plurality of standard cells 610 according to some embodiments. A first cutting feature layout pattern (e.g., the first cutting feature layout pattern CM1A in fig. 1A) may be positioned on the desired locations 660a and 660B in fig. 9A, and a second cutting feature layout pattern (e.g., the second cutting feature layout pattern CM1B in fig. 8) may be positioned on the desired locations 662a and 662B in fig. 9B. The desired locations 660a and 660b overlap by about-0.5 nm through the desired cutting space, and the desired locations 662a and 662b overlap by about-0.5 nm through the desired cutting space. The layout design in fig. 9A and 9B may be used to design the positioning of the first cut feature layout pattern CM1A and the second cut feature layout pattern CM 1B.

Fig. 10A is a diagram of an exemplary layout design 700A, and fig. 10B is an enlarged view of region G in fig. 10A, according to some embodiments. In some embodiments, layout design 700A includes additional elements not shown in FIGS. 10A and 10B. Layout design 700A has two standard cell layout patterns 710A and 710b, and cell boundary 711 between standard cell layout patterns 710A and 710 b. Each of the standard cell layout patterns 710a and 710b has a cell height H3 of about 120 nm. The grid lines 702 extend in the X-axis direction, and the pitch P1 of the grid lines 702 is approximately 24 nanometers. The M2 conductive feature layout pattern 780 may be positioned on the gridlines 702. Stitch access problems may occur in the area G such that two desired locations 760a and 760B may be designed as shown in fig. 10B. For example, the width W of each of the desired locations 760a and 760b is approximately 12 nanometers and the spacing Pa is approximately 52 nanometers. After the calculating operations S36 and S38 of the method M20 in fig. 4, the required cutting space d between the required positions 760a and 760b is about 9 nm, so that the required positions 760a and 760b are separated from each other. In addition, the channel closure 772 is approximately 12 nanometers, the channel plateau 774 is approximately 10.5 nanometers, and the minimum length L2 of the first conductive feature layout pattern 730a is approximately 87 nanometers.

FIG. 11 is a diagram of an example layout design 800A, according to some embodiments. In some embodiments, layout design 800A includes additional elements not shown in FIG. 11. Layout design 800A has two standard cell layout patterns 810A and 810b, and cell boundary 811 is between standard cell layout patterns 810A and 810 b. The standard cell layout pattern 810a has a cell height H4 of about 169 nm, and the standard cell layout pattern 810b has a cell height H5 of about 117 nm. The grid lines 802 extend in the X-axis direction, and the pitch P1 of the grid lines 802 is approximately 26 nanometers. Pin reception problems may occur near the cell boundary 811 such that two conforming locations 860a and 860b may be designed as shown in fig. 11. For example, each of the desired locations 860a and 860b has a width W of about 14 nanometers and a spacing Pa of about 60 nanometers. After the calculating operations S36 and S38 of the method M20 in fig. 4, the required cutting space d between the required positions 860a and 860b is about 10 nm, so that the required positions 860a and 860b are separated from each other. In some embodiments, one of the edges that fits into the desired locations 860a and 860b may be aligned to the cell boundary 811 to reduce layout difficulties. For example, in FIG. 11, bottom edge 876 that conforms to desired position 860a is aligned with cell boundary 811.

Fig. 12 is a block diagram of an IC device design system 1200 in accordance with some embodiments of the present disclosure. As discussed above with reference to fig. 3 and 4, one or more operations of methods M10 and M20 may be carried out using IC device design system 1200.

In some embodiments, the IC device design system 1200 is a computing device that contains a hardware processor 1202 and a non-transitory computer-readable storage medium 1204. Among other things, the non-transitory computer-readable storage medium 1204 is encoded with (i.e., stores) computer program code, i.e., the first set of conductive structures executable instructions 1206. Execution of the instructions 1206 by the hardware processor 1202 represents, at least in part, an IC device design system that performs a portion or all of methods M10 and M20 (hereinafter referred to simply as "processes" and/or "methods"), such as those discussed above with reference to fig. 3 and 4.

The processor 1202 is electrically coupled to a non-transitory computer readable storage medium 1204 via a bus 1208. The processor 1202 is also electrically coupled to an I/O interface 1210 via bus 1208. The network interface 1212 is also electrically connected to the processor 1202 via the bus 1208. The network interface 1212 is coupled to the network 1214 so that the processor 1202 and the non-transitory computer-readable storage medium 1204 can be coupled to external devices via the network 1214. The processor 1202 is configured to execute instructions 1206 encoded in a non-transitory computer-readable storage medium 1204, such that the IC device design system 1200 may be used to perform a portion or all of the processes and/or methods (steps). In one or more embodiments, processor 1202 is a Central Processing Unit (CPU), multiprocessor, distributed processing system, application specific ic (asic), and/or processing unit if applicable.

In one or more embodiments, the non-transitory computer readable storage medium 1204 is an electronic, magnetic, optical, electromagnetic, infrared, and/or semiconductor system (or apparatus or device). For example, the non-transitory computer-readable storage medium 1204 includes semiconductor or solid state memory, magnetic tape, removable computer disks, Random Access Memory (RAM), read-only memory (ROM), rigid magnetic disks, and/or optical disks. In one or more embodiments using optical disks, the non-transitory computer-readable storage medium 1204 includes a compact disk-read only memory (CD-ROM), a compact disk-read/write (CD-R/W), and/or a Digital Video Disk (DVD).

In one or more embodiments, the non-transitory computer-readable storage medium 1204 stores instructions 1206, the instructions 1206 configured to make the IC device design system 1200 available to perform a portion or all of the processes and/or methods (steps). In one or more embodiments, the non-transitory computer readable storage medium 1204 also stores data that facilitates performing a portion or all (steps) of the processes and/or methods. In various embodiments, the non-transitory computer-readable storage medium 1204 stores an IC layout 1220 or a combination of IC layout 1220 or at least one design specification 1222, all discussed above with reference to fig. 1A and 5A-11.

The IC device design system 1200 includes an I/O interface 1210. The I/O interface 1210 is coupled to external circuitry. In different embodiments, the I/O interface 1210 includes one or a combination of a keyboard, keypad, mouse, trackball, trackpad, display, touch screen, and/or mouse directional keys for communicating data and commands to the processor 1202 and/or for communicating commands from the processor 1202.

The IC device design system 1200 also includes a network interface 1212 coupled to the processor 1202. The network interface 1212 allows the IC device design system 1200 to communicate with a network 1214 that interfaces with one or more other computer systems. The network interface 1212 includes a wireless network interface, such as bluetooth, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, some or all of the processes and/or methods (steps) are performed in two or more integrated circuit device design systems 1200.

IC device design system 1200 is configured to receive data via I/O interface 1210. The data received via the I/O interface 1210 includes one or a combination of at least one design rule instruction, at least one set of conditions, at least one design rule, at least one DRM, and/or other parameters processed by the processor 1202. Data is transferred to the processor 1202 via the bus 1208. IC device design system 1200 is configured to send and/or receive information related to a user interface via I/O interface 1210.

The IC device design system 1200 also includes one or more production tools 1224 coupled to the network 1214. Production tool 1224 is configured to produce an IC layout designed by IC device design system 1200. Production tools 1224 include deposition tools (e.g., Chemical Vapor Deposition (CVD) apparatus, Physical Vapor Deposition (PVD) apparatus, etching tools (e.g., dry etching apparatus, wet etching apparatus), planarization tools (e.g., CMP apparatus), or other tools for producing IC devices, including IC layouts designed by IC device design system 2300.

In some embodiments, some or all of the mentioned processes and/or methods are implemented in the form of a stand-alone software application executed by a processor. In some embodiments, some or all of the referenced processes and/or methods are implemented in the form of a software application that is part of an additional software application. In some embodiments, some or all of the mentioned processes and/or methods are implemented in the form of a plug-in to a software application. In some embodiments, at least one of the mentioned processes and/or methods is implemented in the form of a software application that is part of an EDA tool. In some embodiments, the IC layout is generated using a tool such as that available from CADENCE design systems, Inc., or VIRTUOSO, or another suitable layout generation tool.

In some embodiments, the process is implemented as a function of a program stored on a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external/removable and/or internal/internal building memories or memory units such as optical disks, DVDs, magnetic disks, hard disks, semiconductor memories, ROMs, RAMs, memory cards, and the like.

As discussed above with reference to fig. 3 and 4, the IC device design system 1200 and a non-transitory computer-readable storage medium (e.g., the non-transitory computer-readable storage medium 1204), by being operable to carry out one or more operations of the methods M10 and M20, may realize the benefits discussed above with reference to methods 3 and 4 with respect to methods M10 and M20.

Fig. 13 is a block diagram of an IC manufacturing system 1300 and an IC manufacturing flow associated therewith, in accordance with some embodiments of the present disclosure. In some embodiments, at least one of (a) one or more semiconductor masks or (B) at least one component in a semiconductor IC layer is fabricated using IC fabrication system 1300 based on a layout design.

In fig. 13, an IC manufacturing system 1300 includes entities, such as a design company 1320, a mask manufacturing company 1330, and an IC factory/manufacturer/producer 1350, that interact with each other in the design, development, and manufacturing cycle, and/or services associated with manufacturing an IC device 1360. The entities in the IC manufacturing system 1300 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the internet. The communication network includes wired and/or wireless communication channels. Each entity interacts with and provides services to and/or receives services from one or more of the other entities. In some embodiments, two or more of the design company 1320, mask manufacturing company 1330, and IC factory 1350 are owned by a single larger company. In some embodiments, two or more of the design company 1320, the mask manufacturing company 1330, and the IC factory 1350 are co-located in a common facility and use common resources.

The design company (or design team) 1320 generates an IC design layout (or design) 1322 based on the methods M10 and M20 as discussed above with reference to fig. 3 and 4 and above with reference to fig. 1A and 5A-11. The IC design layout 1322 comprises various geometric patterns corresponding to the patterns of the metal, oxide, or semiconductor layers that make up the various components of the IC device 1360. The various layers are combined to form various IC features. For example, a portion of the IC design layout 1322 comprises various IC features such as active areas, gates, source and drains, metal lines or vias interconnecting layers, and openings for bond pads to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers deposited on the semiconductor substrate. Design company 1320 performs an appropriate design process, which includes methods M10 and M20 discussed above with reference to FIGS. 3 and 4 and above with reference to FIGS. 1A and 5A-11, to form IC design layout 1322. The design program contains one or more logical designs, physical designs, or place-and-route. The IC design layout 1322 is presented in one or more data files having geometry data. For example, the IC design layout 1322 may be represented in a GDSII file format or a DFII file format.

Mask manufacturing company 1330 includes data preparation operations 1332 and mask production operations 1344. The mask manufacturing company 1330 uses the IC design layout 1322 to manufacture one or more masks 1345 to be used for the various layers of the fabricated IC device 1360, according to the IC design layout 1322. The mask manufacturing company 1330 performs a mask data preparation operation 1332 in which the IC design layout 1322 is translated into a representative data file ("RDF"). The mask data preparation operation 1332 provides the RDF to the mask production 1344. The mask creation operation 1344 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 1345 or a semiconductor wafer 1353. The design layout 1322 is manipulated by a mask data preparation operation 1332 to conform to the particular features of the mask writer and/or the requirements of the IC fab 1350. In FIG. 13, the mask data preparation operation 1332 and the mask production operation 1344 are illustrated as separate elements. In some embodiments, the mask data preparation operation 1332 and the mask creation operation 1344 are collectively referred to as a mask data preparation operation.

In some embodiments, mask data preparation operation 1332 includes Optical Proximity Correction (OPC) using lithography enhancement techniques to compensate for image errors that may be caused by scattering, interference, other process effects, and the like. The OPC adjusts the IC design layout 1322. In some embodiments, the mask data preparation operation 1332 includes further Resolution Enhancement Techniques (RET), such as off-axis illumination, sub-resolution assist features, phase shift masks, other suitable techniques, and the like or combinations thereof. In some embodiments, Inverse Lithography Technology (ILT) is also used, which treats OPC as an inverse imaging problem.

In some embodiments, mask data preparation operation 1332 includes a Mask Rule Checker (MRC) for checking IC design layouts 1322 that have undergone processing in OPC using mask creation rules that include certain geometric and/or connectivity constraints to ensure sufficient space to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout 1322 to compensate for limitations during mask creation 1344, which may revert to the partial modifications performed by OPC to comply with mask creation rules.

In some embodiments, the mask data preparation operation 1332 includes lithography process inspection (LPC) modeling the processes to be performed by the IC factory 1350 to produce the IC devices 1360. Based on the IC design layout 1322, the LPC models this process to create a simulated fabricated device, such as IC device 1360. The processing parameters in the LPC simulation may include parameters associated with various processes of an IC manufacturing cycle, parameters associated with a tool used to manufacture the IC, and/or other aspects of the manufacturing process. LPC accounts for various factors such as aerial image contrast, depth of focus ("DOF"), coverage error enhancement factor ("MEEF"), other suitable factors, and the like or combinations thereof. In some embodiments, after the simulated fabricated device is created by LPC, if the simulated device shape is not close enough to satisfy the design rules, OPC and/or MRC will be repeated to further refine the IC design layout 1322.

It should be appreciated that the above description of the mask data preparation operation 1332 is simplified for clarity. In some embodiments, the mask data preparation operation 1332 includes additional features, such as Logic Operations (LOPs), to modify the IC design layout 1322 according to manufacturing rules. Additionally, the processes applied to the IC design layout 1322 during the mask data preparation operation 1332 may be performed in a variety of different orders.

After the mask data preparation 1332 operation and during a mask creation operation 1344, a mask 1345 or a set of masks 1345 is created based on the modified IC design layout 1322. In some embodiments, the mask production operation 1344 includes performing one or more lithographic exposures based on the IC design layout 1322. In some embodiments, an electron beam (e-beam) or multiple electron beam (e-beam) mechanism is used to pattern a mask (photomask or reticle) 1345 based on the modified IC design layout 1322. The mask 1345 may be formed by various techniques. In some embodiments, the mask 1345 is formed using binary techniques. In some embodiments, the masking pattern includes opaque regions and transparent regions. A radiation beam, such as an Ultraviolet (UV) beam, used to expose a layer of image sensitive material (e.g., photoresist) that has been coated on the wafer is blocked by the opaque regions and transmitted through the transparent regions. In one example, a binary mask version of mask 1345 comprises a transparent substrate (e.g., fused silica) and an opaque material (e.g., chrome) coated in the opaque region of the binary mask. In another example, mask 1345 is formed using a phase shift technique. In a Phase Shift Mask (PSM) version of mask 1345, various features in the pattern formed on the phase shift mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase shift mask may be an attenuated PSM or an alternating PSM. The mask generated by the mask manufacturing 1344 is used for a variety of processes. Such masks are used, for example, in ion implantation processes to form various doped regions in semiconductor wafer 1353, in etching processes to form various etched regions in semiconductor wafer 1353, and/or other suitable processes.

IC fab 1350 includes wafer fabrication operations 1352. IC factory 1350 is an IC manufacturing business that includes manufacturing facilities for manufacturing one or more different IC products. In some embodiments, IC fab 1350 is a semiconductor foundry. For example, there may be multiple manufacturing facilities (front end of line, FEOL) for front end of line (front end of line) manufacturing of IC products, while a second manufacturing facility may provide back end of line (back end of line, BEOL) for interconnection and packaging of IC products, and a third manufacturing facility may provide other services for foundry business.

The IC factory 1350 manufactures the IC devices 1360 using masks 1345 manufactured by the mask manufacturing company 1330. Thus, the IC foundry 1350 at least indirectly manufactures the IC device 1360 using the IC design layout 1322. In some embodiments, semiconductor wafer 1353 is produced by an IC fab 1350 that uses a shadow mask 1345 to form IC devices 1360. In some embodiments, IC manufacturing includes performing one or more lithographic exposures based at least indirectly on the IC design layout 1322. Semiconductor wafer 1353 comprises a silicon substrate or other suitable substrate having a layer of material formed thereon. Semiconductor wafer 1353 further includes one or more various doped regions (formed in subsequent fabrication steps), dielectric features, multi-layer interconnects, and the like.

According to some embodiments, a method of generating an Integrated Circuit (IC) layout includes laying out a first conductive feature layout pattern in a cell region. The first conductive feature layout pattern extends in a first direction, and the cell region has opposing first and second cell boundaries extending in a second direction. In the cell region, a second conductive feature layout pattern is laid out. The second conductive feature layout pattern extends in the first direction, and the first conductive feature layout pattern and the second conductive feature layout pattern are alternately arranged. A first cut feature layout pattern is laid out on a first cell boundary of the cell region and on an end of the first conductive feature layout pattern. One of the first cut feature layout patterns is offset in a first direction from another one of the first cut feature layout patterns. An integrated circuit layout including a first conductive feature layout pattern, a second conductive feature layout pattern, and a first cut feature layout pattern is generated.

According to some embodiments, a plurality of second cut feature layout patterns are laid out on the first cell boundary of the cell region and on the ends of the second conductive feature layout patterns. One of the second cut feature layout patterns is offset from another of the second cut feature layout patterns in the first direction. The second cutting feature layout patterns are substantially aligned with the other of the first cutting feature layout patterns. The one of the first cut feature layout patterns is offset from another of the first cut feature layout patterns by an offset distance that is less than a width of the one of the first cut feature layout patterns. The first conductive feature layout patterns have a first pitch, and one first cut feature layout pattern and another first cut feature layout pattern of the first cut feature layout patterns have a second pitch that is substantially n times the first pitch, where n is a positive integer. And laying out a metal single-through hole pattern on a grid line of the cell area, wherein the grid line is adjacent to the first cell boundary and extends in the second direction. Another of the first conductive feature layout patterns is between the first cell boundary and the grid line of the cell region. A pitch of the first conductive feature layout patterns is substantially the same as a pitch of the second conductive feature layout patterns. A distance between one of the first cut feature layout patterns and the second cell boundary of the cell region is different from a distance between another one of the first cut feature layout patterns and the second cell boundary of the cell region. An offset distance of one of the first cut feature layout patterns is determined based on a pitch of the first conductive feature layout patterns. An offset distance of one of the first cut feature layout patterns is determined based on a via closure.

According to some embodiments, an integrated circuit includes a first cell, a second cell, and a first isolation portion. The second cell is adjacent to the first cell. In a first direction, a first unit and a second unit are arranged, and the first unit comprises a first conductive structure and a second conductive structure. The first conductive structure extends in a first direction. Each first conductive structure has a first end facing the second cell. The second conductive structure extends in a first direction. The first conductive structures and the second conductive structures are alternately arranged in a second direction different from the first direction. The first isolation portions respectively abut the first end portions of the first conductive structures. Two of the first isolated portions are misaligned with each other in the second direction.

According to some embodiments, the first conductive structures have a pitch, and centers of two of the first isolation portions have a distance substantially n times the pitch, where n is a positive integer. A cell boundary is between the first and second cells, and two of the first isolated portions are on opposite sides of the cell boundary. A pitch of the first conductive structures is substantially the same as a pitch of the second conductive structures. The integrated circuit device further includes second isolation portions abutting second ends of the second conductive structures, respectively. The integrated circuit device further includes a first via underlying and in direct contact with one of the first conductive structures. The integrated circuit device further includes a second via over and in direct contact with one of the first conductive structures.

According to some embodiments, a system for designing an integrated circuit includes a non-transitory computer-readable medium and a processor. The non-transitory computer-readable medium is configured to store executable instructions. The processor is coupled to a non-transitory computer readable medium. The processor is configured to execute the following instructions for: laying out a first conductive feature layout pattern in a cell region, wherein the first conductive feature layout pattern extends in a first direction, and the cell region has opposing first and second cell boundaries extending in a second direction different from the first direction; laying out a second conductive feature layout pattern in the cell region, wherein the second conductive feature layout pattern extends in a first direction, and the first conductive feature layout pattern and the second conductive feature layout pattern are alternately laid out in a second direction; first cut feature layout patterns are laid out on first cell boundaries of the cell regions and on ends of the first conductive feature layout patterns, wherein one of the first cut feature layout patterns is offset from another one of the first cut feature layout patterns in the first direction.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such effective constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.