阅读说明：本技术 命令延迟 (Command delay ) 是由 B·邓洛普 G·J·卢卡斯 E·C·麦克格劳赫林 于 2020-08-27 设计创作，主要内容包括：本申请涉及一种命令延迟。一种设备包括存储器组件、延迟组件和耦合到所述延迟组件的命令组件。所述命令组件可以被配置成将接收到的与访问所述存储器组件中的物理地址相关联的命令输入到执行队列中并且将所述命令标记为活动。所述命令组件可以被配置成将所述活动命令发送到所述存储器组件以被执行。所述命令组件可以被配置成响应于经由所述延迟组件从所述存储器组件接收到指示所述活动命令已被执行的消息而从所述执行队列中清除所述活动命令。所述延迟组件可以被配置成在将所述消息发送到所述命令组件之前将来自所述存储器组件的所述消息延迟特定的时间段。(The present application relates to command delay. An apparatus includes a memory component, a delay component, and a command component coupled to the delay component. The command component may be configured to input a received command associated with accessing a physical address in the memory component into an execution queue and mark the command as active. The command component may be configured to send the active command to the memory component to be executed. The command component may be configured to clear the active command from the execution queue in response to receiving a message from the memory component via the delay component indicating that the active command has been executed. The delay component may be configured to delay the message from the memory component for a particular period of time before sending the message to the command component.)

1. An apparatus, comprising:

a memory device (140, 240);

a delay component (181, 281, 481, 581); and

a command component (113, 213, 413, 513, 613) coupled to the delay component (181, 281, 481, 581), wherein the command component (113, 213, 413, 513, 613) is configured to:

entering a received command (223, 225) associated with accessing a physical address in the memory device (140, 240) into an execution queue and marking the command as active;

sending an active command to the memory device (140, 240) to be executed; and

responsive to receiving a message from the memory device (140, 240) via the delay component (181, 281, 481, 581) indicating that the active command has been executed, clearing the active command from the execution queue;

wherein the delay component (181, 281, 481, 581) is configured to:

delaying the message from the memory device (140, 240) for a specific period of time before sending the message to the command component (113, 213, 413, 513, 613).

2. The device of claim 1, wherein the command component (113, 213, 413, 513, 613) is configured to:

inputting additional commands (223, 225) associated with the physical address and received after the command into the execution queue;

marking the additional command pending; and

changing the additional command from pending to active in response to clearing the active command from the execution queue.

3. The apparatus of claim 1, wherein:

the command component (113, 213, 413, 513, 613) is configured to input a write command (223, 225) as an activity into the execution queue; and

the delaying component (181, 281, 481, 581) is configured to delay the message indicating that an active write command has been executed.

4. The apparatus of claim 1, wherein:

the command component (113, 213, 413, 513, 613) is configured to input a read command (223, 225) as an activity into the execution queue; and

the delaying component (181, 281, 481, 581) is configured to not delay the message indicating that the active write command has been executed.

5. The device of any of claims 1 to 4, wherein the command component (113, 213, 413, 513, 613) is configured to:

inputting the read command (223, 225) as an activity into the execution queue; and

receiving a message associated with the read command being executed directly from the memory device (140, 240) rather than via the delay component (181, 281, 481, 581).

6. The device according to any of claims 1 to 4, wherein the command component (113, 213, 413, 513, 613) is a content addressable memory, CAM, component.

7. A method, comprising:

receiving a command (223, 225) associated with a physical address of a memory device (140, 240);

tracking the command and its associated physical address and whether the command has been executed using an execution queue;

receiving a message from the memory device (140, 240) indicating that the command has been executed, wherein the message includes a command identification, ID, for identifying the command in the execution queue;

delaying, by the processing device (117), receipt of the message for a particular period of time before clearing the command from the execution queue.

8. The method of claim 7, further comprising:

determining expiration of the particular time period; and

the command is cleared from the execution queue (223, 225).

9. The method of claim 7, further comprising sending the message to a host (120) before sending the message to a command (223, 225) component (113, 213, 413, 513, 613), wherein the command component (113, 213, 413, 513, 613) comprises the execution queue.

10. The method of claim 7, further comprising:

synchronously sending the message to the host (120) and the delay component (181, 281, 481, 581); and

delaying clearing the command (223, 225) from the execution queue by an amount of time approximately equal to a time period between sending the message from the host (120) to the delay component (181, 281, 481, 581) sending the message to the command component (113, 213, 413, 513, 613).

11. The method of claim 7, further comprising sending the message to a host (120) prior to clearing the command (223, 225) from the execution queue.

12. The method of claim 7, further comprising:

determining whether the received additional command is associated with the physical address; and

responsive to the received additional command (223, 225) being associated with the physical address, entering the received command into an execution queue and marking it as pending; and

responsive to the received additional command being associated with a physical address different from the physical address, inputting the received additional command into the execution queue and sending the received additional command to the memory device (140, 240) to be executed.

13. The method of claim 12, wherein the additional command (223, 225) is changed from pending to active in response to the additional command being marked as pending and in response to the command being cleared from the execution queue.

14. The method of claim 7, wherein the particular time period is different for a write command (223, 225) that has been executed and a read command (223, 225) that has been executed.

15. The method of claim 7, wherein the particular period of time that the write command (223, 225) has been executed is longer than the particular period of time that the read command (223, 225) has been executed.

16. A system, comprising:

a memory device (140, 240); and

processing means (117) coupled to the memory means (140, 240) to perform operations including:

receiving a command (223, 225), the command associated with a physical address in a memory device (140, 240);

tracking which of the received commands are:

a pending command, wherein the pending command indicates that a physical address associated with a previously received command is the same as a physical address associated with the pending command; or

Active commands, wherein an active command indicates that no commands to be executed with the same physical address have been received before the respective active command, and each of the commands is associated with a command identification, ID, identifying the respective command in the command component (113, 213, 413, 513, 613);

receiving a response sent from the memory device (140, 240), the response having a command ID corresponding to an active command that has been executed; and

in response to receiving a response from the memory device (140, 240), clearing the active command associated with the command ID from the command component (113, 213, 413, 513, 613);

wherein a time period between the memory device (140, 240) sending a response and the command component (113, 213, 413, 513, 613) clearing the active command is different with respect to write commands and read commands.

17. The system of claim 16, further comprising a delay component (181, 281, 481, 581), wherein the delay component (181, 281, 481, 581) receives the response from the memory device (140, 240) and delays sending the response to the command component (113, 213, 413, 513, 613) by a particular period of time.

18. The system of claim 16, wherein the command component (113, 213, 413, 513, 613) is configured to receive the response and change the active command (223, 225) to a delay command.

19. The system of claim 16, further comprising a time counter, wherein:

the time counter is configured to send time data to the command component (113, 213, 413, 513, 613); and

the command component (113, 213, 413, 513, 613) is configured to determine a time period for delaying clearing of the active command (223, 225) based on the time data.

Technical Field

Embodiments of the present disclosure relate generally to memory subsystems and, more particularly, to command latency.

Background

The memory subsystem may include one or more memory components that store data. The memory components may be, for example, non-volatile memory components and volatile memory components. Typically, a host system may utilize a memory subsystem to store data at and retrieve data from a memory component.

Disclosure of Invention

An embodiment relates to an apparatus, comprising: a memory device; a delay component; and a command component coupled to the delay component, wherein the command component is configured to: inputting a received command associated with accessing a physical address in a memory device into an execution queue and marking the command as active; sending the active command to the memory device to be executed; and responsive to receiving a message from the memory device via the delay component indicating that the active command has been executed, clearing the active command from the execution queue; wherein the delay component is configured to: messages from the memory device are delayed for a particular period of time before being sent to the command component.

Another embodiment relates to a method comprising: receiving a command associated with a physical address of a memory device; tracking the command and its associated physical address and whether the command has been executed using the execution queue; receiving a message from the memory device indicating that the command has been executed, wherein the message includes a command Identification (ID) for identifying the command in the execution queue; the delay by the processing means on receipt of the message is a specific period of time before the command is cleared from the execution queue.

Another embodiment relates to a system, comprising: a memory device; and a processing device coupled to the memory device to perform operations comprising: receiving a command, the command associated with a physical address in a memory device; track which of the received commands are: a pending command, wherein the pending command indicates that a physical address associated with a previously received command is the same as a physical address associated with the pending command; or active commands, wherein an active command indicates that no commands to be executed with the same physical address have been received before the respective active command, and each of the commands is associated with a command Identification (ID) that identifies the respective command in the command component; receiving a response sent from the memory device, the response having a command ID corresponding to the active command that has been executed; and responsive to receiving a response from the memory device, clearing the active command associated with the command ID from the command component; wherein the time period between the memory device sending the response and the command component clearing the active command is different with respect to the write command and the read command.

Drawings

The present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure.

FIG. 1 illustrates an example computing environment including a memory subsystem in accordance with some embodiments of the present disclosure.

FIG. 2 illustrates an example of a command pipeline associated with command tracing in accordance with some embodiments of the present disclosure.

FIG. 3 is a flow diagram of an example method of using a command component in accordance with some embodiments of the present disclosure.

4A-D are each example computing environments corresponding to methods of using a command component, according to some embodiments of the present disclosure.

FIG. 5 is an example computing environment corresponding to a method of using a command component in accordance with some embodiments of the present disclosure.

6A-6C are each example computing environments corresponding to methods of using a command component, according to some embodiments of the present disclosure.

FIG. 7 is a flow diagram of an example method of command tracking according to some embodiments of the present disclosure.

FIG. 8 is a block diagram of an example computer system in which embodiments of the present disclosure may operate.

Detailed Description

Aspects of the present disclosure are directed to a memory subsystem that includes command latency. The memory subsystem may be a memory device, a memory module, or a mixture of memory devices and memory modules. Examples of memory devices and memory modules are described below in connection with FIG. 1. In general, a host system may utilize a memory subsystem that includes one or more memory components (e.g., memory devices that store data). The host system may provide data to be stored in the memory subsystem and may request that the data be retrieved from the memory subsystem.

The memory component may include a non-volatile memory device that stores data from the host system. A non-volatile memory device is a package of one or more dies. The die in the package may be assigned to one or more channels for communication with the memory subsystem controller. Non-volatile memory devices include cells (i.e., electronic circuits that store information) that are grouped into pages to store data bits. The non-volatile memory device may include a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory that may perform bit storage based on changes in bulk resistance in conjunction with a stackable cross-meshed data access array. Such non-volatile memory devices may group pages across dies and channels to form Management Units (MUs). The MU may include user data and corresponding metadata. The memory subsystem controller may send and receive user data and corresponding metadata to and from the memory devices as a management unit. Another example of a non-volatile memory device is a NAND (NAND) memory device. For NAND type memories, pages may be grouped to form blocks. Other examples of non-volatile memory devices are described below in connection with FIG. 1.

The host system may send access requests (e.g., write commands, read commands) to the memory subsystem, such as storing data on and reading data from memory devices at the memory subsystem. The data specified by the host request to be read or written is hereinafter referred to as "host data". The host request may include logical address information (e.g., Logical Block Address (LBA), namespace) of the host data, the logical address information being a location of the host system associated with the host data. The logical address information (e.g., LBA, namespace) may be part of the metadata of the host data.

The memory subsystem may map logical address information to physical addresses (e.g., physical MU addresses, physical block addresses) associated with one or more memory devices on the memory subsystem, and write and/or read host data to and/or from the physical addresses. A memory subsystem (e.g., SSD) may include a compute component that may track commands and/or prevent access to physical addresses associated with memory devices. In some conventional approaches, accesses to a particular physical address location may not be tracked, and the order of accesses may overlap or be too close in time, resulting in incorrect data being accessed and stored back to the memory device.

Aspects of the present disclosure address the above and other deficiencies by introducing a delay in accessing the same physical access in memory using subsequent commands. More specifically, to execute a subsequent command associated with the physical address, a previously received command associated with the physical address is purged from the command component. The clearing of tracked commands that have been executed may be intentionally delayed, thereby prolonging the blocking of accesses to associated physical addresses by subsequent commands. This delay introduced after the execution of the command may prevent overlap of multiple accesses or prevent multiple accesses that are too close in time and avoid errors in the data.

FIG. 1 illustrates an example computing environment 100 including a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

Memory subsystem 110 may be a memory device, a memory module, or a mixture of memory devices and memory modules. Examples of storage devices include Solid State Drives (SSDs), flash drives, Universal Serial Bus (USB) flash drives, embedded multimedia controller (eMMC) drives, Universal Flash (UFS) drives, and Hard Disk Drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and non-volatile dual in-line memory modules (NVDIMMs).

The computing environment 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, host system 120 is coupled to different types of memory subsystems 110. FIG. 1 shows one example of a host system 120 coupled to one memory subsystem 110. Host system 120, for example, uses memory subsystem 110 to write data to memory subsystem 110 and to read data from memory subsystem 110. As used herein, "coupled to" generally refers to a connection between components that may be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including, for example, electrical, optical, magnetic, etc.

The host system 120 may be a computing device, such as a desktop computer, a laptop computer, a web server, a mobile device, a vehicle (e.g., an airplane, drone, train, automobile, or other transport), an internet of things enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or networked business device), or such computing device including a memory and a processing device. The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, peripheral component interconnect express (PCIe) interfaces, Universal Serial Bus (USB) interfaces, fibre channel, Serial Attached SCSI (SAS), and the like. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. Host system 120 may also utilize an NVM Express (NVMe) interface to access memory components (e.g., memory device 130) when memory subsystem 110 is coupled with host system 120 over a PCIe interface. The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120.

The memory devices may include any combination of different types of non-volatile memory devices and/or volatile memory devices. Volatile memory devices, such as memory device 140, may be, but are not limited to, Random Access Memory (RAM), such as Dynamic Random Access Memory (DRAM) and Synchronous Dynamic Random Access Memory (SDRAM).

Some examples of non-volatile memory devices, such as memory device 130, include NAND (NAND) type flash memory and write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory. A cross-point array of non-volatile memory may perform bit storage based on changes in bulk resistance in conjunction with a stackable cross-grid data access array. In addition, in contrast to many flash-based memories, cross-point non-volatile memories may perform in-place write operations in which non-volatile memory cells may be programmed without pre-erasing the non-volatile memory cells.

Although non-volatile memory devices such as 3D cross-point and NAND type memories are described, memory device 130 may be based on any other type of non-volatile memory, such as Read Only Memory (ROM), Phase Change Memory (PCM), self-selection memory, other chalcogenide based memories, ferroelectric random access memory (FeRAM), Magnetic Random Access Memory (MRAM), NOR (NOR) flash memory, and Electrically Erasable Programmable Read Only Memory (EEPROM).

One type of memory cell, e.g., a Single Level Cell (SLC), can store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), Triple Level Cells (TLC), and quad-level cells (QLC), may store multiple bits per cell. In some embodiments, each of memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include SLC and MLC portions of memory cells, a TLC portion, or a QLC portion. The memory cells of memory device 130 may be grouped into pages or codewords that refer to logical units of the memory device for storing data. For certain types of memory (e.g., NAND), pages may be grouped to form blocks. Certain types of memory (e.g., 3D cross-point) may group pages across grains and channels to form a Management Unit (MU).

Memory subsystem controller 115 (or controller 115 for simplicity) may communicate with memory device 130 to perform operations such as reading data, writing data, or erasing data at memory device 130, and other such operations. Memory subsystem controller 115 may include hardware, such as one or more integrated circuits and/or discrete components, cache memory, or a combination thereof. The hardware may comprise digital circuitry having dedicated (i.e., hard-coded) logic to perform the operations described herein. Memory subsystem controller 115 may be a microcontroller, special purpose logic circuitry (e.g., a Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), etc.), or other suitable processor.

Memory subsystem controller 115 may include a processor (processing device) 117 configured to execute instructions stored in local memory 103. In the illustrated example, the local memory 115 of the memory subsystem controller 103 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

In some embodiments, local memory 103 may include memory registers that store memory pointers, fetched data, and the like. The local memory 103 may also include, for example, a Read Only Memory (ROM) for storing microcode. While the example memory subsystem 110 in fig. 1 has been shown as including a memory subsystem controller 115, in another embodiment of the present disclosure, the memory subsystem 110 may not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

In general, memory subsystem controller 115 may receive commands or operations from host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to memory devices 130. Memory subsystem controller 115 may be responsible for other operations associated with memory device 130, such as wear leveling operations, garbage collection operations, error detection and correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., Logical Block Addresses (LBAs), namespaces) and physical addresses (e.g., physical MU addresses, physical block addresses). Memory subsystem controller 115 may also include host interface circuitry to communicate with host system 120 over a physical host interface. Host interface circuitry may convert commands received from a host system into command instructions to access memory device 130 and convert responses associated with memory device 130 into information for host system 120.

Memory subsystem 110 may also include additional circuits or components not shown. In some embodiments, memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that may receive addresses from memory subsystem controller 115 and decode the addresses to access memory devices 130.

In some embodiments, memory device 130 includes a local media controller 135, which local media controller 135 operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory units of memory device 130. An external controller (e.g., memory subsystem controller 115) may manage memory device 130 externally (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device that is an original memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. One example of a managed memory device is a managed NAND (MNAND) device.

Memory subsystem controller 115 includes a command component 113 that may be configured to track physical addresses of memory associated with command instructions for execution. Command component 113 can enter the command and its associated physical address into the execution queue and indicate in the entry whether the command is active (indicating that the associated command is being sent to the memory component for execution), pending (indicating that the associated command is waiting in the execution queue until permission is granted or allowed to be sent for execution), and/or clear the command entry from the execution queue when the associated command completes. The indication may comprise a set bit, a set flag, or another indicator that may be referenced. As shown in FIG. 1, command component 113 may include various circuitry 119 to facilitate tracking of commands and their associated physical addresses associated with the commands. For example, circuitry 119 may include special purpose circuitry in the form of ASICs, FPGAs, state machines, and/or other logic circuitry that may allow command component 113 to track and/or monitor commands and corresponding physical addresses.

In one embodiment, command component 113 comprises a Content Addressable Memory (CAM) component. In a CAM, the search data may be compared to a stored data table, whereby an address of matching data may be returned. In this case, entries in the CAM may be searched using "hits" indicating that a command for a particular address is already present in the CAM (e.g., the physical address targeted by an incoming command matches the physical address of a command already present in the CAM), and "misses" indicating that a command for a particular address is not present in the CAM (e.g., the physical address targeted by an incoming command does not match the physical address of a command already present in the CAM). As further described herein, in various embodiments, a CAM miss results in an incoming command being marked as "active" (e.g., ready to be sent to a memory component for execution), and a CAM hit results in an incoming command being marked as "pending," and a delay is introduced to prevent the state of the pending command from changing to active until a particular period of time after completion of a previously active command to the same address.

Memory subsystem controller 115 may include a delay component 181. In some embodiments, delay component 181 is a first-in-first-out (FIFO) buffer. Delay component 181 may receive data from memory device 140 and may delay the data from being transmitted to command component 113 for a particular period of time. In some embodiments, responding to data associated with a write command may be delayed longer than responding to data associated with a read command. For example, in response to memory device 140 sending a message or response indicating that the write command has completed in memory device 140, delay component 181 may delay the message or response longer than if the read command completed. In some embodiments, a message or response indicating that a read command has been executed may bypass delay component 181 entirely and be passed directly to command component 113, as will be described further below.

As described in more detail in connection with FIG. 2, data may be transferred to command circuitry 119 prior to execution of multiple commands in order to verify that a physical address location in memory is not targeted by another command. For example, command circuitry 119 may be used to track and/or monitor the execution of multiple commands by maintaining a list of received commands and determining whether a command is pending or active, and may clear a command entry when a command has been executed. In contrast to methods in which execution of commands is not blocked even though another command associated with the same physical address may not have completed execution, blocking access to physical addresses may be used to prevent overlap of more than one command associated with the same physical address before execution of at least one of the commands is completed, as described below. Thus, only one command to a particular physical address is executed at a time, with the next pending command held (or blocked) until a response from memory returns the command ID associated with the command executed at the particular physical address.

In some previous approaches, as an example, the host 120 may access a physical location in the memory 140, and the firmware (e.g., of the controller) may make subsequent requests to access the memory that are so close in time that the access by the host 120 is still occurring or just occurring, the memory may have some hysteresis from the accessed access that may affect the access by the firmware. Likewise, the host 120 may access the memory 140 and store intermediate results of the processing back to the memory, while the firmware wants to access the host's processing results, even if the processing is not yet complete. These conditions may cause errors in the data considered as the final result and in intermediate results. For example, the host 120 may access data to perform multiple read operations, write operations, analysis operations, etc. on the data, and the final data of such operations may be corrupted due to overlapping data accesses. For example, the firmware may access the data to refresh the data, perform multiple clock cycle operations, etc., and desire to refresh or perform operations on the final data.

As described below, to avoid overlapping accesses to the same data at the same physical location in memory, commands and their associated addresses may be tracked, and subsequent access attempts to the same physical address may be blocked if the initial access has not been completed. Further, attempts to access the same physical access may be delayed beyond completion of the previous command. For example, the host may request access to a particular physical address to perform a command (e.g., a write operation to data stored in a first physical address). The command component may track a particular physical address in the execution queue and mark the command entry associated with the particular physical address as "active". The valid designation may indicate that a request to access data at a particular physical address has been received and sent to the memory component storing the data. Once a command has been executed on data at a particular physical address, a response indicating that the command has been executed may be delayed before being sent to the command component, and removal of the "active" state of the command entry associated with the particular physical address may be delayed and/or removal of the command entry from the execution queue may be delayed. Once the delay is complete, subsequent requests to access the data at the particular physical address are allowed.

If a subsequent request to access data at a particular physical address is received at the command component while the command entry of the first request is still "active," the command component may compare the physical address of the subsequent request to the physical addresses in the execution queue (which would result in a match of the physical address of the subsequent request to the particular physical address of the initial request). Since there is already an "active" state for the command at that physical address, subsequent requests may be marked "pending", may be entered into the execution queue, and linked with the previous command entry associated with the particular physical address entry. A response indicating that the initial command has been executed may be sent to a delay component (e.g., a FIFO component), and once a particular time period, referred to as a delay, has been completed, the initial command entry may be cleared from the execution queue and subsequent command entries (due to the linkage in the execution queue) may be sent to the memory component for execution. After each execution of a command, the execution queue may be searched for a link to a subsequent command entry to be executed (which would include any request to execute a command associated with the same physical address that has been received when the command instruction that has been received was first processed).

In this manner, although the command is listed as "pending" and waiting to execute a previously received command, a subsequently received command, but associated with a different physical address in the memory component, may be executed until the next linked command is allowed to be executed. The ordering of command execution may be time-based until the physical addresses match, in which case the timing may be re-ordered based on an acknowledgement of execution of commands associated with the same physical addresses, as described above.

FIG. 2 illustrates an example of a command pipeline 201 associated with command tracing in accordance with some embodiments of the present disclosure. Pipeline 201 may include a medium, such as memory device 240 (e.g., a memory component), which may be similar to memory device 140 illustrated in fig. 1. Additionally, the command pipeline 201 may include a command component 213, which may be similar to the command component 113 shown in FIG. 1. Command component 213 may receive host commands (e.g., commands received from a host) 223 and/or firmware commands (e.g., firmware that may be executed to perform functions associated with the firmware commands) 225 through multiplexer ("mux") 224 and logical-to-physical ("L2P") component 226. For example, a host (e.g., host 120) may send a request including host command 223 to perform a read operation on data stored in memory 240. The host may send a request including a host command 223 to perform a write operation on data stored in memory 240. For example, firmware may be executed to send a request including firmware command 225 to refresh data stored in memory 240. The firmware may be executed to send a request including firmware commands 225 to perform an operation associated with a particular clock cycle on data stored in memory 240. In the event that both host commands 223 and firmware commands 225 are received in tandem, memory 240 may be accessed in such close proximity in time that effects on data stored in the memory may occur, changing values stored in the data and/or generating errors in the data and in subsequent operations performed on the data.

The host may send or the firmware may be executed to send a request including a host command 223 or a firmware command 225 to perform an operation on data in memory 240 by sending the request through multiplexer 224. A simple round robin priority may be performed if commands are received simultaneously from the host and/or through firmware. The request streams for commands from one interface (e.g., host 120 or firmware) may be processed in a first-in-first-out (FIFO) order, and requests from any of the interfaces may also be processed as if the individual streams were in FIFO order with respect to each other. In some embodiments, a component may be between multiplexer 224 and L2P component 226 and may split a command having multiple identified physical address locations into a single command identifying a single physical address location. The L2P component 226 maps logical addresses to physical addresses.

The transmitted request may initially be sent to the L2P component 226 to translate data associated with the logical address into data associated with the physical address. For example, host command 223 may be sent to multiplexer 224 and may be associated with a logical address in memory 240, and L2P component 226 may associate data with a physical address. In one example, the address associated with the execution of firmware command 225 may already be a physical address. Firmware commands 225 may be sent from L2P component 226 to command component 213 using a logical-to-physical translation. In some embodiments, a splitting component (not shown) may be between the command component 213 and the memory 240. The splitting component may split a command identifying multiple channels and/or dies into a single command identifying a single channel and/or die. In this example, the command component 213 may first send a command to be executed to the split component, which then transfers the processed command to the memory 240 for execution.

When a command is received from the host or by executing firmware at the command component 213, the command component 213 determines whether the physical address associated with the command is also associated with the received command. The execution queue in the command component 213 may list entries indicating all received commands along with their corresponding physical addresses. Each of the entries in the execution queue may indicate whether the command is active (indicating that the command has been sent to memory for execution) or pending (indicating that the command is delayed or blocked from being sent to memory until a response indicating that all previously received commands associated with the same physical address have been executed).

To avoid overlap of accesses to the memory 240, the command component 213 may prevent an access of one command to data stored in the same physical address of the memory 240 (because other commands may have been used to access the same physical address) until the initial access has been completed. For example, a command associated with a particular physical address can be received at the command component 213. A particular physical address may be compared to entries in the execution queue to determine whether the particular physical address is already in the execution queue and associated with a previously received command. An entry is generated in the execution queue for the received command and, if there is an entry for a previously received command associated with a particular physical address, the entry is indicated as pending. In the case of a pending command, a link is entered into the active command entry such that when the active command is executed, the link is accessed and instructs the command component 213 to process subsequently received commands associated with the same physical address.

Each entry in the execution queue includes a command Identification (ID) to identify the particular entry in the queue, a particular physical address associated with the received command, and the state of the entry (which state would be pending in this example). In one example, there may have been previously received commands, but if a previously received command has been executed and cleared from the execution queue, the received command may be indicated as active and sent for execution. If the particular physical address does not match another physical address associated with the command in the execution queue, an entry for the received command is indicated as active and the command is sent to memory for execution.

In the event that a previously received command is active and yet to be executed, the pending command entry may be delayed or maintained until a response is received from memory 240 indicating that an active command has been executed, as illustrated by arrow 232. Upon receiving the response 232, the link in the active command entry (of the previously received command that has now been executed) may instruct the command component 213 to process the received command next. In addition, a response, as shown by arrow 233, may be sent to the host or additional firmware to be executed, which verifies that the command has been executed. The active command entry (of a previously received command) may be cleared and the pending command entry (of the received command) may be updated to the active command entry. However, if an intermediate command is sent after a previously received command but before the received command, the received command will be delayed until the intermediate command is executed. In this example, the previously received command entry would be linked to an intermediate command entry, and the intermediate command entry would be linked to the received command entry. In this manner, the order of commands associated with the same physical address may be tracked to avoid repeated accesses to the physical address.

In some embodiments, as will be described further below in conjunction with fig. 3-7, the response from memory 240 may be sent to delay component 281 (e.g., delay component 181 of fig. 1) and delayed for a particular period of time as indicated by arrow 234. Upon completion (or expiration) of the particular time period, as indicated by arrow 236, a response may be sent to the command component 213. In some embodiments, when the command is a write command, the response may be delayed at delay component 281, and when the command is a read command, the response may bypass delay component 281. In some embodiments, the response associated with the write command may be delayed by delay component 281 and the response associated with the read command may be sent to delay component 281, but may not be delayed by delay component 281.

In the event a command is received that corresponds to a different physical address and does not correspond to another physical address in the execution queue, the command may be indicated as active and executed in a conventional FIFO manner (e.g., in the chronological order in which it was received). In this way, commands are delayed relative to other commands having the same physical address, but commands having different physical addresses are executed in the chronological order in which they were received, without there being a different physical address already in the execution queue and associated with another command.

In some embodiments, the write blocking FIFO may be used for Firmware Write (FW) commands. The logic that writes the blocking FIFO may ensure that a blocked write (marked pending due to a conflict with an active command) will also cause subsequent writes to be blocked thereafter in FIFO order. Because the FW data buffer may provide only FIFO access and not random access, this may align all FW write commands to be forwarded in the same order as write data arriving from the host (e.g., host commands 223) or as firmware (e.g., firmware commands 225).

For example, using a write block FIFO in this manner may keep all writes performed in the order they were received. In this example, the FW writes may be performed in order, as the write data arrives from the firmware in the same order as the commands. Thus, if one of the FW writes is blocked due to a collision with an earlier command, it is input into the write block FIFO and becomes pending, and all subsequent write commands from the firmware will also be input into the write block FIFO in FIFO order after the first write command. Once the active state of the earlier command is cleared from the command component, the first pending write in the write block FIFO will be released and loaded into the command component and become active. Any subsequent write at the top of the write block FIFO will also be released (if it does not conflict in the command component) and will become active in the command component. This process may continue until the write blocking FIFO is empty or one of the writes hits a conflict in the command component. If a write command at the top of the write block FIFO happens to hit a conflict in the command section, it will not be released at that time, and all subsequent write commands following it will also be held. This may preserve the order of the write commands. In some instances, a write command may be received from one input port (e.g., from firmware) and entered into the write block FIFO, and all writes from a different input port (e.g., from the host) may bypass the write block FIFO and enter the command component directly. This may allow write commands from the host to be executed out of order, while write commands from the firmware are executed only in order.

FIG. 3 is a flow diagram 340 of an example method of using a command component in accordance with some embodiments of the present disclosure. Method 340 may be performed by processing logic that may comprise hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuits, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, method 340 is performed by command component 113 in FIG. 1 and/or command component in FIG. 2. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise indicated. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are also possible.

At block 351, the method begins and at 352, a command is received. The command may be received at a command component (e.g., command components 113, 213 in fig. 1 and 2, respectively). At block 354, in response to receiving the command, the method 340 may include determining whether another active or pending command directed to or corresponding to the same physical address has been previously received and listed in the execution queue. In one example, the execution queue may include entry locations for a list of 128 commands. When commands are received, each command may be entered into the execution queue at one of these entry locations. Each of the entries in execution may be identified by a corresponding command Identification (ID) indicating a particular command used to locate the particular command in a subsequent operation (e.g., to clear the command from the execution queue). The determination may include comparing the received command and the associated physical address to each of the entries in the execution queue. At block 362, the method 340 may include, in response to no entry in the execution queue matching the received command (indicating that no command in the execution queue is associated with the same physical address as the received command), the received command and its associated physical address may be entered as an activity in the execution queue and sent to memory for execution.

At block 356, method 340 may include, in response to an entry in the execution queue matching the received command (indicating that the previously received command is associated with the same physical address in memory as the currently received command), entering the received command and its associated physical address as pending into the execution queue and linking the received command to the matching previous command. In this way, a pending entry in the execution queue indicates that a command has been received but is delayed until a previously received command (having the same physical address) has been executed. In some embodiments, entries associated with all of the same physical address may also be ordered based on time of receipt to maintain the order of command execution (which will also be maintained based on the links between commands having the same physical address).

At block 358, it is determined whether a previous command has been executed. If the previous command has been executed (as indicated by the received response), the entry for the previous command is cleared from the execution queue, as shown in block 360. The response sent to the command component may be delayed, as will be described below in connection with fig. 4A-4D. For example, a write command may be executed by the memory, and the memory may send a response to the command component. However, the response may be delayed at a delay component between the memory and the command component. In this way, the response is delayed for a particular period of time, thereby delaying the clearing of the associated write command in the execution queue of the command component. The received command may be delayed and remain pending until a response is received from the memory indicating that the previously received command has been executed. The response from memory may include a command ID associated with the entry so that the entry for the executed command may be located in the execution queue and cleared. At block 362, in response to clearing the previously received command entry, the received command entry may be entered as an active command and sent to memory for execution.

In response to no entry in the execution queue matching the received command (indicating that the previously received command is associated with a different physical address in memory), the received command and its associated physical address are entered as an activity in the execution queue and the received command is sent to memory for execution, as shown in block 362 of method 340. The received command may also be marked as the "oldest" entry in the execution queue to maintain the chronological order of the commands.

At block 364, it may be determined whether a response is received from memory indicating that the received command has been executed. The received command may remain as an active entry in the execution queue until a response is received from memory indicating that the received command has been executed. At 366, when a response is received indicating that the received command has been executed, the entry in the execution queue corresponding to the previously received command may be cleared. At 368, in response to clearing the received command entry, the execution queue may be checked for the next command to be executed.

While performing the method of flowchart 340 described above, if an additional command associated with the same physical address is received (after receiving the received command but before executing the received command), the additional command will have been linked to the received command and indicated as pending. It is checked whether the next command in the execution queue will recognize a link to an additional command, and the additional command will be changed to an active command and sent to memory for execution. However, if subsequent commands associated with different physical addresses are received while the method of flowchart 340 is being performed, then a check of the execution queue will identify the subsequent commands to be sent to the memory for execution in the order in which the subsequent commands were received in time. For example, if one of the subsequent commands is received after receiving the received command but before executing the previously received command, then the one of the subsequent commands is sent to the memory for execution (since the received command will still be a pending command).

4A-D are each example computing environments corresponding to methods of using a command component, according to some embodiments of the present disclosure. FIG. 4A is an example computing environment 405-1 corresponding to a method of using a command component 413. The command component 413 may include a plurality of entries 471-1, 471-2, …, 471-N (hereinafter collectively referred to as entries 471). Entry 471 may be used to input a write request (and thus a write or read command) and its associated physical address and status indicator (e.g., status indicator 473-1 of first entry 471-1). The command component 413 may act as a Content Addressable Memory (CAM) to determine whether the physical address of the received request matches the corresponding physical address of one of the entries 471 (referred to as a CAM "hit" when there is a match and a CAM "miss" when there is no match).

The command component 413 may receive a first write request, indicated by arrow 472, that includes a first write command associated with a first physical address in memory. The first write request may be input into a first entry 471-1 of the command component. First entry 471-1 may include a status portion 473-1, the status portion 473-1 indicating whether first entry 471-1 is active or pending. Since this is the first write request and there are no other active commands associated with the same physical address, the first entry 471-1 is indicated as "active". In response to the first write request being an active entry in the command component 413, a first write request (e.g., a first write command) may be sent to the memory, as indicated by arrow 474.

FIG. 4B is an example computing environment 405-2 corresponding to a method of using the command component 413. After the first write request is sent to the memory (as shown in FIG. 4A), a second write request may be sent to the command component 413 as indicated by arrow 476. The physical address of the second write request is compared to the current entry in the command component 413, as indicated by block 475, to determine whether there is a match of the physical address associated with the received second write request and the physical address already stored as an entry in the command component 413, as illustrated by arrow 477. In this example, the physical address associated with the second write request matches the physical address associated with the first write request, so there is a match. As a result of this match, a second write request is entered as a second entry 471-2, and its status indicator 473-2 is "pending".

FIG. 4C is an example computing environment 405-3 corresponding to a method of using the command component 413. After the second write request is input into the execution queue of the command component 413 as a pending entry, a response indicating that the write command is complete ("responsive write complete") may be sent to the host and/or firmware, as indicated by arrow 482, and also sent to a delay component (e.g., delay FIFO)481, as indicated by arrow 484. The response may be sent to the host/firmware and delay component 481 simultaneously or synchronously. The delay component 481 can delay the response for a particular period of time and prevent the response from going to the command component 413 while the host/firmware can receive the response. The particular time period may be between about 0-5 microseconds, between about 20-30 microseconds, about 25 microseconds, 2 microseconds, etc. For example, a particular memory cell technology may be prone to errors if read or written after a previous write operation within a particular period of time. For example, if a memory cell was written to within 0-5 microseconds of a previous write operation, an error may occur because the memory cell does not have enough time to equilibrate or reach a desired voltage indicative of a particular value.

In some embodiments, the delay component 481 may be an SRAM delay FIFO, which is a rotating FIFO that holds command IDs for write completions. The depth of the FIFO may determine the delay. The read and/or write pointer may be incremented periodically (e.g., at each clock cycle). For example, the write pointer may follow the read pointer, and after executing the write command, the read pointer may hit the same location after the entire depth of the SRAM FIFO is read. For example, if the SRAM is 8,192 deep and the period equals 5 nanoseconds, the delay may be 40.9 microseconds (e.g., 8,129 x 5ns-40.9 microseconds).

When the write completion response reaches the latency FIFO, the write completion response may include the command ID (identifying the write command in the command component 413) entered into the SRAM latency FIFO. When the command ID is sent out of the SRAM latency FIFO, the command ID is used as a lookup for the command component 413 and is cleared from the command component 413. The purging of active write commands from the command component 413 may cause the command component 413 to go to the next write/read command in the execution queue, or in the order in which it was received, through the link of the purged write command (if the write command has the same physical address as the next write command), or to the next write command (if the next write command is associated with a different physical address).

In some embodiments, the response associated with the read command being executed may not be delayed in the delay component 481, or may bypass the delay component 481 and go directly to the command component 413 (as shown and described in connection with FIG. 5).

FIG. 4D is an example computing environment 405-4 corresponding to a method of using the command component 413. After sending the response to the command component 413 (via the delay component 481), the first write request entry 471-1 may be cleared (as shown in fig. 4D). A second write request entry 471-2 is the next write command with the same physical address, and status indicator 473-2 is changed to "active". The "active" state allows the command component 413 to send a second write request (for a second write command) to the memory, as indicated by arrow 488. The second write command is executed in memory and the method is repeated (sending a response back to the host/firmware and delay component 481, etc.).

FIG. 5 is an example computing environment 507 corresponding to a method of using a command component in accordance with some embodiments of the disclosure. The example shown in fig. 5 is associated with the execution of a read command in memory. As shown in FIG. 5, a response indicating that the read command has been completed (a "response read complete"), indicated by arrow 582, is sent to host/firmware and 586 to command component 513 either simultaneously or synchronously. The delay component 581 is shown as being bypassed so the response is not delayed in this example.

Regardless of whether the delay of the response (indicating that execution of the command has occurred) is caused by bypassing of the delay component 581 or by the delay component 581 not delaying the response, the delay shown occurs after the write-to-write (W2W) command and/or the write-to-read (W2R) command, and does not occur after the read-to-write (R2W) command or the read-to-read (R2R) command. The initial read operation is treated differently in these cases, for example, because the memory cell is less prone to errors if read or write immediately after read than if read or write immediately after write operation. The nature of the write operation may have a hysteresis effect on the cell (which does not occur after the read operation), and if the cell is accessed in a subsequent time that is too close to the time at which the write operation occurs, it may have a negative impact on subsequent read or write operations performed by the cell.

6A-6C are each example computing environments corresponding to methods of using a command component, according to some embodiments of the present disclosure. The method associated with fig. 6A-6C includes delaying a response from memory indicating command execution using a counter instead of a delay FIFO (as described in fig. 4A-4D). FIG. 6A is an example of a computing environment 609-1. The computing environment 609-1 includes a command component 613.

The command component 613 may include a plurality of entries 671-1, 671-2, …, 671-N in which commands are input along with corresponding physical addresses and associated status indicators 673-1, 673-2, etc. As shown, a first write request associated with a first write command may be received and input as a first entry 671-1 in the command component 613. The first entry 671-1 may have a status indicator 673-1 indicating "active" because, in this example, no command having the same physical address was previously received. A subsequent second write request may be received and input as a second entry 671-2. Because this second write request is associated with the same physical address as the first write request in this example, the second entry is associated with a status indicator 673-2 of "pending" and will remain pending until the first write request completes.

FIG. 6B is an example computing environment 609-2 corresponding to a method of using a command component in accordance with some embodiments of the present disclosure. In this example, in response to receiving a "first write complete" from memory, time counter 690 is used to determine whether the delay has expired and the write command may be cleared. Status indicator 673-1 is changed to "delay" and several inputs are used to determine whether a delay hit occurred in delay device 695. This "delay" may be a third state that is juxtaposed to the "active" and "pending" states. A 3-bit time delay field 696 (using bits 9:7) is used for each entry. The value of the time counter 690 in the 3-bit timestamp 696 may be added to a constant value in an adder 697 and stored to the time delay field 691 of the command component 613. In response to receiving the first write complete response, a 3-bit time delayed timestamp 696 is captured from the time counter 690 and added, and a one hundred (100) bit time delay 694 is added to the adder 697 of the 3-bit timestamp 696. For example, if the time counter 690 increments every 5 nanoseconds (for a core clock cycle), then 7 bits may toggle every 0.64 microseconds. If bits 9:7 are captured as timestamp 696, a 100-bit time delay 694 is added and saved in time delay field 691. The saved time delay field 691 may be compared to the runtime counter 690, and a comparison hit (at delay hit 695) will occur at 1.92 microseconds after approximately 2.56 microseconds. The "+ 1" input 692 may be input to the multiplexer 693 to cause the time counter 690 to increment by +1 per cycle, which may maintain relative "real time".

FIG. 6C is an example computing environment 609-3 corresponding to a method of using a command component in accordance with some embodiments of the present disclosure. Once a delayed hit occurs, as shown and described in connection with FIG. 6B, the second write request entry 671-1 may be changed to the "active" status indicator 673-1 and sent to memory, as indicated by arrow 688.

FIG. 7 is a flow diagram of an example method 711 corresponding to a command component in accordance with some embodiments of the present disclosure. The method 711 may be performed by processing logic that may comprise hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuits, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, method 711 is performed by command component 113 in FIG. 1 and/or command component 213 in FIG. 2. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise indicated. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are also possible.

At operation 742, the method 711 includes receiving (e.g., at a command component) a command associated with a physical address of a memory device. The method 711 may further include determining whether the received additional command is associated with a physical address. In response to receiving the additional command being associated with the physical address, the method may include entering the received command into an execution queue and marking pending. In response to the received additional command being associated with a physical address different from the physical address, the method may include inputting the received additional command into an execution queue and sending the received additional command to the memory component to be executed. The method may include changing the additional command from pending to active in response to the additional command being marked as pending and in response to the command being cleared from the execution queue.

At operation 744, the method 711 includes tracking (e.g., by the command component) the command and its associated physical address, and whether the command has been executed using the execution queue.

At operation 746, the method 711 includes receiving (e.g., at the delay component) a message from the memory device indicating that the command has been executed, wherein the message includes a command Identification (ID) for identifying the command in the execution queue. The method 711 may also further include receiving a command Identification (ID) for identifying the command in the execution queue, and the command ID is for the flush command.

At operation 748, the method 711 includes delaying clearing of the command from the execution queue for a particular period of time upon receipt of the message. The method 711 may further include sending a message to the command component via the delay component upon expiration of the particular time period. In some instances, the particular time period may be different for an executed write command and an executed read command. In some examples, the particular period of time for the write command to be executed is longer than the particular period of time for the read command to be executed.

The method may further include clearing the command from the execution queue upon receiving the message. The method may further include sending the message to a host sending the command via the memory component before sending the message to the command component via the delay component. The method may further include sending the message to a host sending the command via the memory component. The method may further include sending the message to a delay component at the same time the message is sent to the host. The receipt of the message may be delayed in the delay component en route to the command component. The method may further include sending a message to the host sending the command via the memory component prior to clearing the command from the execution queue.

In some embodiments of the present disclosure, the method 711 further comprises designating the received command as an active command in response to the received command being associated with a physical address that is not associated with another command. The method 711 further includes designating the received command as a pending command in response to the received command being associated with a physical address, the physical address being associated with an active command, wherein the active command is a command that has not yet been executed. The method 711 further includes, in response to designating the received command as a pending command, linking the active command with the pending command. The link can direct the command component to execute the pending command in response to the active command being executed. The method 711 further includes, in response to the active command being executed, designating the pending command as a next active command and sending the next active command to the memory component to be executed.

Fig. 8 illustrates an example machine of a computer system 841 within which a set of instructions, for causing the machine to perform one or more of the methodologies discussed herein, may be executed. In some embodiments, computer system 841 may correspond to a host system (e.g., host system 120 in fig. 1) that includes, is coupled to, or utilizes a memory subsystem (e.g., memory subsystem 110 in fig. 1) or may be used to perform operations of a controller (e.g., execute an operating system to perform operations corresponding to command component 113 in fig. 1). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and/or the internet. The machine may operate in the capacity of a server or a client in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client in a cloud computing infrastructure or environment.

The machine may be a Personal Computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, switch or bridge, or another machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include a collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

An example computer system 841 includes a processing device 802, a main memory 604 (e.g., Read Only Memory (ROM), flash memory, Dynamic Random Access Memory (DRAM) such as Synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), a static memory 806 (e.g., flash memory, Static Random Access Memory (SRAM), etc.), and a data storage system 818, which communicate with each other via a bus 830.

The processing device 802 represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, Reduced Instruction Set Computing (RISC) microprocessor, Very Long Instruction Word (VLIW) microprocessor, or processor implementing other instruction sets, or processors implementing a combination of instruction sets. The processing device 802 may also be one or more special-purpose processing devices such as an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Digital Signal Processor (DSP), network processor, or the like. The processing device 802 is configured to execute instructions 826 for performing the operations and steps discussed herein. The computer system 841 may also include a network interface device 808 to communicate over the network 820.

The data storage system 818 may include a machine-readable storage medium 824 (also referred to as a computer-readable medium) having stored on the readable storage medium 824 one or more sets of instructions 826, or software, embodying one or more of the methodologies or functions described herein. The instructions 826 may also reside, completely or at least partially, within the main memory 804 and/or within the processing device 802, the main memory 804 and the processing device 802 also constituting machine-readable storage media during execution thereof by the computer system 841. The machine-readable storage medium 824, data storage system 818, and/or main memory 804 may correspond to memory subsystem 110 of fig. 1.

In one embodiment, instructions 826 include instructions for implementing functionality corresponding to a compute component (e.g., compute component 113 in FIG. 1). The instructions may include command instructions 813 and/or delay instructions 881, the command instructions 813 being associated with performing operations with command components (e.g., command component 113 in fig. 1), the delay instructions 881 being associated with performing operations with delay components (e.g., delay components 181, 281, 481 in fig. 1, 2, and 4A-4D, respectively). While the machine-readable storage medium 824 is shown in an example embodiment to be a single medium, the term "machine-readable storage medium" should be taken to include one or more media that store one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include media capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

Some portions of the preceding detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may relate to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

The present disclosure also relates to apparatus for performing the operations herein. The apparatus may be specially constructed for the intended purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but is not limited to, various types of disks including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), Random Access Memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or the type of media suitable for storing electronic instructions, each of which is coupled to a computer system bus.

The algorithms and displays presented herein are not inherently related to a particular computer or other apparatus. Various general-purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear from the description below. In addition, the present disclosure is not described with reference to a particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the disclosure as described herein.

The present disclosure may be provided as a computer program product or software which may include a machine-readable medium having stored thereon instructions which may be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes a mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) -readable storage medium such as read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory components, and so forth.

In the foregoing specification, embodiments of the disclosure have been described with reference to specific example embodiments thereof. It will, of course, be evident that various modifications may be made thereto without departing from the broader spirit and scope of embodiments of the disclosure as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.