阅读说明：本技术 存储器模块及具有存储器模块的存储系统 (Memory module and memory system having the same ) 是由 李奎东 尹永 朴星柱 尹珍成 于 2020-02-25 设计创作，主要内容包括：提供了存储器模块及具有存储器模块的存储系统。所述存储器模块包括：串行存在检测器(SPD),被配置为：通过至少一个模块位置标识端子检测模块标识(ID),并且生成模块ID和对应于模块ID的寄存器地址中的至少一个。电源管理单元(PMU)响应于由SPD生成的模块ID和寄存器地址中的至少一者。PMU被配置为基于模块ID和对应于模块ID的寄存器地址中的至少一者,设置内部时钟信号的开始时间点和/或结束时间点,并且还被配置为：响应于内部时钟信号生成至少一个内部电源电压。还提供了多个存储器件,多个存储器件被配置为：接收至少一个内部电源电压,并且响应于命令/地址信号执行操作。(A memory module and a memory system having the same are provided. The memory module includes: a Serial Presence Detector (SPD) configured to: a module Identification (ID) is detected through at least one module position identification terminal, and at least one of the module ID and a register address corresponding to the module ID is generated. A Power Management Unit (PMU) is responsive to at least one of the module ID and the register address generated by the SPD. The PMU is configured to set a start time point and/or an end time point of the internal clock signal based on at least one of the module ID and a register address corresponding to the module ID, and is further configured to: at least one internal supply voltage is generated in response to an internal clock signal. There is also provided a plurality of memory devices configured to: at least one internal power supply voltage is received and an operation is performed in response to the command/address signal.)

1. A memory module, comprising:

a serial presence detector configured to: detecting a module identification through at least one module location identification terminal and generating at least one of the module identification and a register address corresponding to the module identification;

A power management unit configured to: in response to at least one of the module identification and the register address generated by the serial presence detector, setting a start time point and/or an end time point of an internal clock signal based on at least one of the module identification and the register address corresponding to the module identification, the power management unit further configured to: generating at least one internal supply voltage in response to the internal clock signal; and

a plurality of semiconductor memory devices configured to: the at least one internal power supply voltage is received and an operation is performed in response to a command/address signal.

2. The memory module of claim 1, further comprising:

a temperature sensor communicatively coupled to the serial presence detector; and

a register clock driver communicatively coupled to the serial presence detector, the register clock driver configured to receive the command/address signals and send the command/address signals to the plurality of semiconductor memory devices.

3. The memory module of claim 2, wherein the serial presence detector is communicatively coupled to the power management unit, the register clock driver, and the temperature sensor through a local data communication channel; and the number of the first and second electrodes,

wherein the local data communication channel serially transmits at least one of the module identification and the register address corresponding to the module identification in response to a local serial clock signal.

4. The memory module of claim 1, wherein the power management unit comprises:

a register unit including a module identification register for storing the module identification and a plurality of control data registers for storing a plurality of different control data corresponding to a plurality of different module identifications; and

an internal clock signal generator configured to: generating the internal clock signal having the start time point and/or the end time point set in response to control data generated from a control data register: a control data register among the plurality of control data registers corresponding to the at least one of the module identification and the register address corresponding to the module identification.

5. The memory module of claim 1, wherein the serial presence detector is further configured to: supporting global data communication with an external device, receiving the register address corresponding to the module identification, performing local data communication with the power management unit, and transmitting the register address corresponding to the module identification.

6. The memory module of claim 5, wherein the power management unit comprises:

a register unit including a module identification register for storing the module identification and a plurality of control data registers for storing a plurality of different control data corresponding to a plurality of different module identifications; and

an internal clock signal generator configured to: generating the internal clock signal having the start time point and/or the end time point, the start time point and/or the end time point being set in response to control data generated from a control data register corresponding to the register address corresponding to the module identification among the plurality of control data registers.

7. The memory module of claim 6, wherein the global data communication is to serially transmit the register address corresponding to the module identification in response to a global serial clock signal.

8. A memory module, comprising:

a power management unit configured to: setting a start time point and/or an end time point of an internal clock signal based on a module identification, and generating at least one internal power supply voltage in response to the internal clock signal; and

a plurality of semiconductor memory devices configured to: the at least one internal power supply voltage is received and an operation is performed in response to a command/address signal.

9. The memory module of claim 8, further comprising:

a temperature sensor communicatively coupled to the power management unit; and

a register clock driver communicatively coupled to the power management unit, the register clock driver configured to receive the command/address signals and send the command/address signals to the plurality of semiconductor memory devices.

10. The memory module of claim 8, wherein the power management unit detects the module identification through at least one module location identification terminal and generates at least one of the module identification and a register address corresponding to the module identification.

11. The memory module of claim 10, wherein the power management unit comprises:

a register unit including a plurality of control data registers for storing a plurality of different control data corresponding to a plurality of different module identifications; and

an internal clock signal generator configured to: generating the internal clock signal having the start time point and/or the end time point set in response to control data generated from a control data register: a control data register among the plurality of control data registers corresponding to the at least one of the module identification and the register address corresponding to the module identification.

12. The memory module of claim 8, wherein the power management unit is further configured to: global data communication with an external device is supported and a register address corresponding to the module identification is received.

13. The memory module of claim 12, wherein the power management unit comprises:

a register unit including a plurality of control data registers for storing a plurality of different control data corresponding to a plurality of different module identifications; and

an internal clock signal generator configured to: generating the internal clock signal having the start time point and/or the end time point, the start time point and/or the end time point being set in response to control data generated from a control data register corresponding to the register address corresponding to the module identification among the plurality of control data registers.

14. A storage system, comprising:

a motherboard having a plurality of memory slots therein;

a plurality of memory modules mounted in the plurality of memory slots; and

a control unit configured to: performing global data communication with the plurality of memory modules, transmitting command/address signals, and transmitting and receiving data;

Wherein each of the plurality of memory modules comprises:

a power management unit configured to: setting a start time point and/or an end time point of an internal clock signal based on a corresponding module identification among a plurality of module identifications different from each other, and generating at least one internal power supply voltage in response to the internal clock signal; and

a plurality of semiconductor memory devices configured to: the at least one internal power supply voltage is received and an operation is performed in response to the command/address signal.

15. The memory system of claim 14, wherein each of the plurality of memory modules further comprises:

a serial presence detector configured to: at least one of the module identification and a register address corresponding to the module identification is transmitted by performing local data communication with the power management unit when the module identification is detected through at least one module location identification terminal, or the register address corresponding to the module identification is transmitted by performing the local data communication with the power management unit when the register address corresponding to the module identification is received by performing the global data communication.

16. The memory system of claim 15, wherein the local data communication serially transmits the at least one of the module identification and the register address corresponding to the module identification in response to a local serial clock signal, wherein the global data communication serially transmits the register address corresponding to the module identification in response to a global serial clock signal.

17. The memory system of claim 15, wherein each of the plurality of memory modules further comprises:

a temperature sensor configured to sense a temperature and perform local data communication with the serial presence detector; and

a register clock driver configured to receive the command/address signals, to transmit the command/address signals to the plurality of semiconductor memory devices, and to perform local data communication with the serial presence detector.

18. The storage system of claim 14, wherein the power management unit is further configured to: generating at least one of the module identification and a register address corresponding to the module identification when the module identification is detected through at least one module location identification terminal, or generating the register address corresponding to the module identification when the register address corresponding to the module identification is received by performing the global data communication.

19. The memory system of claim 18, wherein each of the plurality of memory modules further comprises:

a temperature sensor configured to sense a temperature and perform local data communication with the power management unit; and

a register clock driver configured to: receiving the command/address signal to transmit the command/address signal to the plurality of semiconductor memory devices, and performing local data communication with the power management unit.

20. The storage system of claim 14, wherein the power management unit further comprises:

a register unit including a module identification register for storing the module identification and a plurality of control data registers for storing a plurality of control data different from each other corresponding to the plurality of module identifications; and

an internal clock signal generator configured to: generating the internal clock signal having the start time point and/or the end time point set in response to control data generated from a control data register: a control data register among the plurality of control data registers corresponding to at least one of the module identification and a register address corresponding to the module identification.

Technical Field

Apparatuses and systems consistent with example embodiments relate to a memory module and a memory system including the memory module.

Background

A memory system may generally include a plurality of memory slots mounted on a motherboard, a controller, and a Power Management Unit (PMU). A memory module may be inserted into each of the plurality of memory slots. However, recently, memory modules including a power management unit have been developed. Therefore, a technique of controlling a power management unit included in each of a plurality of memory modules to stably generate an internal power supply voltage using an external power supply voltage is required.

Disclosure of Invention

Example embodiments of the inventive concept are directed to providing a memory module capable of stably generating an internal power voltage through a Power Management Unit (PMU) included in the memory module and a memory system having the memory module.

Aspects of the inventive concept should not be limited by the above description, and other aspects not mentioned will be apparent to those of ordinary skill in the art from the example embodiments described herein.

According to an example embodiment, there is provided a memory module comprising a serial presence detector configured to: a module Identification (ID) is detected through at least one module location identification terminal, and the module ID (or a register address corresponding to the module ID) is transmitted. There is also provided a power management unit configured to: the method includes communicating with the serial presence detector via a local data communication channel, receiving the module ID (or a register address corresponding to the module ID), setting a start time point and/or an end time point of an internal clock signal based on the module ID (or a register address corresponding to the module ID), and generating at least one internal power supply voltage in response to the internal clock signal. There is also provided a plurality of semiconductor memory devices configured to: the at least one internal power supply voltage is received, an operation is performed in response to a command/address signal, and data is stored or output.

According to a further example embodiment, there is provided a memory module comprising a power management unit configured to: a start time point and/or an end time point of an internal clock signal is set based on a module ID, and at least one internal power supply voltage is generated in response to the internal clock signal. There is also provided a plurality of semiconductor memory devices configured to: the at least one internal power supply voltage is received, an operation is performed in response to a command/address signal, and data is stored or output.

According to a further embodiment of the present invention, there is provided a memory system including a main board, a plurality of memory slots provided at a plurality of positions different from each other on the main board, a plurality of memory modules mounted in the plurality of memory slots, and a control unit. The control unit is configured to: performing global data communication with the plurality of memory modules, transmitting command/address signals, and transmitting and receiving data. Each of the plurality of memory modules may include: a respective power management unit configured to: a start time point and/or an end time point of an internal clock signal is set based on a corresponding module ID among a plurality of different module IDs, and at least one internal power supply voltage is generated in response to the internal clock signal. There is also provided a plurality of semiconductor memory devices configured to: receiving the at least one internal power supply voltage, performing an operation in response to the command/address signal, and storing or outputting the data.

Drawings

Fig. 1 is a block diagram of a configuration of a memory module according to an example embodiment of the inventive concepts.

Fig. 2 is a block diagram illustrating a configuration of a serial presence detector according to an exemplary embodiment of the inventive concept.

Fig. 3 is a block diagram illustrating a configuration of a power management unit according to an example embodiment of the inventive concepts.

Fig. 4 is a block diagram illustrating a configuration of an internal clock signal generator according to an example embodiment of the inventive concepts.

Fig. 5 is an operation timing diagram for describing the operation of the internal clock signal generator shown in fig. 4.

Fig. 6 is a diagram illustrating a configuration of a voltage generator according to an example embodiment of the inventive concepts.

Fig. 7 is a table illustrating control data according to module IDs of a plurality of control data registers of a register unit according to an example embodiment of the inventive concepts.

Fig. 8 is an operation timing diagram for describing local data communication between a serial presence detector and a power management unit according to an example embodiment of the inventive concepts.

Fig. 9 is an operation timing diagram for describing local data communication between a serial presence detector and a power management unit according to an example embodiment of the inventive concepts.

Fig. 10 is an operation timing diagram for describing global data communication between an external device and a serial presence detector according to an example embodiment of the inventive concepts.

Fig. 11 is an operation timing diagram for describing local data communication between a serial presence detector and a power management unit according to an example embodiment of the inventive concepts.

Fig. 12 is a block diagram illustrating a configuration of a memory module according to an example embodiment of the inventive concepts.

Fig. 13 is a block diagram illustrating a configuration of a power management unit according to an example embodiment of the inventive concepts.

Fig. 14 is an operation timing diagram for describing global data communication between an external device and a power management unit according to an example embodiment of the inventive concepts.

Fig. 15 is a block diagram illustrating a configuration of a storage system according to an example embodiment of the inventive concepts.

Detailed Description

Hereinafter, a memory module and a memory system having the same according to example embodiments will be described with reference to the accompanying drawings.

Fig. 1 is a block diagram illustrating a configuration of a memory module according to an example embodiment of the inventive concepts, and the memory module 100 may include: 4n semiconductor memory devices M11 to M1n, M21 to M2n, M31 to M3n, and M41 to M4n, a main board 10, a Serial Presence Detector (SPD)12, a Power Management Unit (PMU)14, a Temperature Sensor (TS)16, and a Register Clock Driver (RCD) 18. In fig. 1, 4n semiconductor memory devices M11 to M1n, M21 to M2n, M31 to M3n, and M41 to M4n, the serial presence detector 12, the power management unit 14, the temperature sensor 16, and the register clock driver 18 may be mounted on an upper surface (or a lower surface) of the main board 10. DQLP can represent a left data terminal, DQRP can represent a right data terminal, CA1P can represent a first command/address terminal, CA2P can represent a second command/address terminal, SAP can represent a serial address terminal, SCLP can represent a serial clock signal terminal, and SDAP can represent a serial data terminal.

The functionality of each of the blocks shown in fig. 1 is described more fully below.

The n semiconductor memory devices M11 through M1n may input and output data through some terminals of the left data terminals DQLP in response to the first command/address signals ca11, and the n semiconductor memory devices M21 through M2n may input and output data through the remaining terminals of the left data terminals DQLP in response to the second command/address signals ca 12. The n semiconductor memory devices M31 through M3n may input and output data through some of the right data terminals DQRP in response to the third command/address signal ca21, and the n semiconductor memory devices M41 through M4n may input and output data through the remaining terminals of the right data terminals DQRP in response to the fourth command/address signal ca 22. For example, when the memory module 100 includes 20 semiconductor memory devices M11 to M1n, M21 to M2n, M31 to M3n, and M41 to M4n (n ═ 5), each of the 20 semiconductor memory devices M11 to M1n, M21 to M2n, M31 to M3n, and M41 to M4n inputs and outputs 4-bit data through 4 data terminals, and the memory module 100 may input and output 80-bit data through 40 left data terminals lp and 40 right data terminals DQRP.

The Serial Presence Detector (SPD)12 may perform global data communications (e.g., data communications according to the I2C (between integrated circuits) or I3C (between modified integrated circuits) communication protocols) over a lane including a serial clock signal terminal SCLP and a serial data terminal SDAP. The serial presence detector 12 may detect a passive component (e.g., a resistor) connected to a module position identification terminal (MIDP) and generate a module Identification (ID). For example, the serial presence detector 12 may detect a current or voltage of the module position identification terminal MIDP and generate a module ID. Unlike the illustrated configuration, the serial presence detector 12 may detect voltages applied to at least two module location identification terminals (e.g., an external power supply voltage and/or a ground voltage applied to the memory module 100) and generate a module ID. The serial presence detector 12 may perform local data communications (e.g., data communications according to the I2C or I3C communication protocols) with the power management unit 14, the temperature sensor 16, and the register clock driver 18 over a channel that includes a local serial clock signal line LSCLL and a local serial data line LSDAL. The serial presence detector 12 may perform local data communication with the power management unit 14 to transmit the module ID or the register address corresponding to the module ID.

The power management unit 14 may generate a predetermined number of internal power supply voltages using the external power supply voltage and perform local data communication with the serial presence detector 12. The power management unit 14 may set a start time point and/or an end time point of the internal clock signal based on the module ID transmitted from the serial presence detector 12. The power management unit 14 may set a start time point and/or an end time point of the internal clock signal based on the register address corresponding to the module ID transmitted from the serial presence detector 12. Although not shown, the power management unit 14 may apply a predetermined number of internal power supply voltages to the 4n semiconductor memory devices M11 through M1n, M21 through M2n, M31 through M3n, and M41 through M4n, the serial presence detector 12, the temperature sensor 16, and the register clock driver 18.

The temperature sensor 16 may sense temperature and perform local data communication with the serial presence detector 12. The register clock driver 18 may input a first command/address applied through the first command/address terminal CA1P to generate a first command/address signal CA11 and a second command/address signal CA12, and may input a second command/address applied through the second command/address terminal CA2P to generate a third command/address signal CA21 and a fourth command/address signal CA 22. In addition, the register clock driver 18 may perform local data communications with the serial presence detector 12. As can be appreciated from the above description, when local data communication is performed, the serial presence detector 12 may function as a master, and the power management unit 14, the temperature sensor 16, and the register clock driver 18 may function as slaves.

FIG. 2 is a block diagram illustrating a configuration of a serial presence detector according to an example embodiment of the inventive concept, and the serial presence detector 12 may include a global interface unit 12-10, a module position detector 12-12, a control logic unit 12-14, a register unit 12-16, and a local interface unit 12-18.

The function of each block shown in fig. 2 is described below.

The global interface unit 12-10 may input and output the serial data SDA in response to the global serial clock signal SCL applied from the outside. For example, the global interface units 12-10 may perform global data communications based on the I2C or I3C communication protocols. Further, the global interface unit 12-10 may convert serial received serial data SDA into parallel generated data da, or convert parallel received data da into serial generated serial data SDA. The serial presence detector 12 may act as a slave when performing global data communications.

The module position detector 12-12 may sense a passive component (e.g., a resistor (not shown)) connected to the module position identification terminal MIDP (refer to fig. 1), and generate a module ID "mid". When a passive component is connected to the module position identification terminal MIDP, the module position detector 12-12 may sense a current flowing through the module position identification terminal MIDP or a voltage of the module position identification terminal MIDP and generate the module ID mid. Upon receiving the module ID mid, the control logic unit 12-14 may generate a register address add indicating the module ID register, generate the module ID mid as data d, and store the module ID in the module ID register. Upon receiving the module ID, the control logic unit 12-14 may generate the register address of the module ID register of the power management unit 14 and generate the module ID as data db. Alternatively, the control logic units 12-14 may generate a register address corresponding to the module ID of the power management unit 14 as data db. Upon receiving the data da, the control logic unit 12-14 may determine whether both the local device ID and the module ID included in the data da match both the corresponding local device ID stored in the local device ID register (i.e., the local device ID of the serial presence detector 12, e.g., 4-bit data "1010") and the corresponding module ID stored in the module ID register (i.e., the module ID of the memory module 100, e.g., 3-bit data "010"), and if the two IDs match, control logic unit 12-14 may receive data da and generate the register address included in data da as register address add, and stores the data d in the register of the register unit 12-16 corresponding to the register address add, or receives data d output from the register of the register unit 12-16 corresponding to the register address add to generate data da. If only the module IDs match and the local device IDs do not match, the control logic unit 12-14 may receive the data da to generate the data db. That is, when the control logic units 12-14 determine that the data da is related to other local devices of the respective memory module (e.g., the power management unit 14, the temperature sensor 16, or the register clock driver 18), the control logic units 12-14 may receive the data da to generate the data db.

The register units 12-16 may include a plurality of registers having a local device ID register and a module ID register, and the plurality of registers may be selected to store data d in response to a register address add, or output the stored data as data d. The local device ID register may pre-store the local device ID of the serial presence detector 12 (e.g., "1010"), the local device ID of the power management unit 14 (e.g., "1001"), the local device ID of the temperature sensor 16 (e.g., "0010"), and the local device ID of the register clock driver 18 (e.g., "1011").

The local interface units 12-18 may receive the data db and output local serial data LSDA in response to the local serial clock signal LSCL. In addition, the local interface units 12-18 may receive the local serial data LSDA in response to the local serial clock signal LSCL to generate the data db. The local interface units 12-18 may convert the parallel received data db to serial generated local serial data LSDA or convert the serial received local serial data LSDA to parallel generated data db.

Fig. 3 is a block diagram illustrating a configuration of a power management unit according to an example embodiment of the inventive concept, and the power management unit 14 may include a local interface unit 14-10, a control logic unit 14-12, a register unit 14-14, an internal clock signal generator 14-16, and a voltage regulator 14-18.

The function of each block shown in fig. 3 will be described below.

Local interface units 14-10 may input and output local serial data LSDA in response to local serial clock signal LSCL. For example, the local interface units 14-10 may perform local serial data communications based on the I2C or I3C communication protocols. Furthermore, local interface units 14-10 may convert serially received local serial data LSDA to parallel generated data dc, or convert parallel received data dc to serially generated local serial data LSDA.

When data dc is received, a local apparatus ID included in the data dc matches a corresponding local apparatus ID (e.g., "1001") stored in the local apparatus ID register, and a module ID included in the data dc indicates a corresponding module ID (e.g., "010"), the logic control unit 14-12 may receive the data dc to generate a register address included in the data dc as a register address addl and store the data dl in a register corresponding to the register address addl, or receive data d1 output from a register corresponding to the register address addl to generate the data dc. As one example, when the local device ID matches the corresponding local device ID, the module ID indicates the corresponding module ID, and the register address addl is a register address of the module ID register, the control logic unit 14-12 may store the module ID in the module ID register and output control data of the control data register corresponding to the module ID. As another example, control logic unit 14-12 may output the control data stored in the control data register when the local device ID matches the corresponding local device ID, the module ID indicates the corresponding module ID, and the register address addl is the register address of the control data register corresponding to the module ID.

The register units 14-14 may include a plurality of registers including a corresponding local device ID register, a module ID register, and a plurality of control data registers, and the plurality of registers may be selected to store data dl or output the stored data as data dl in response to a register address addl. The plurality of control data may be stored in a plurality of control data registers in advance. As one example, the plurality of control data registers may be configured to output one of the plurality of control data in response to a module ID stored in the module ID register. As another example, the plurality of control data registers may be configured to generate one of the plurality of control data in response to a register address.

The internal clock signal generators 14-16 may set a start time point and/or an end time point of the internal clock signal ICLK in response to the control data de. The voltage regulators 14-18 may include k internal supply voltage generators VR 1-VRk that generate k internal supply voltages V1-Vk that are the same as or different from each other. Each of the k internal supply voltage generators VR1 to VRk may generate k internal supply voltages V1 to Vk using an external supply voltage (e.g., 12V) applied from the outside (boosting down). Each of the k internal supply voltage generators VR1 to VRk may be a buck converter.

Fig. 4 is a block diagram illustrating a configuration of an internal clock signal generator according to an example embodiment of the inventive concepts, and the internal clock signal generators 14 to 16 may include a ramp signal generator 20, a comparison voltage generator 22, a first comparator 24, a second comparator 26, and a latch 28. Fig. 5 is an operation timing diagram for describing the operation of the internal clock signal generator shown in fig. 4.

The operation of each block will be described below with reference to fig. 4 and 5.

Ramp signal generator 20 may generate a ramp signal Vramp. The comparison voltage generator 22 may generate the first comparison voltage VC1 and the second comparison voltage VC2 using the external power supply voltage in response to the control data de. The first comparison voltage VC1 is greater than the second comparison voltage VC 2. The first comparator 24 may generate the first clock signal CLK1 increased to a logic "high" level when the voltage of the ramp signal Vramp is equal to or greater than the first comparison voltage VC1, and the first comparator 24 may generate the first clock signal CLK1 decreased to a logic "low" level when the voltage of the ramp signal Vramp is less than the first comparison voltage VC 1. The second comparator 26 may generate the second clock signal CLK2 increased to a logic "high" level when the voltage of the ramp signal Vramp is equal to or greater than the second comparison voltage VC2, and the second comparator 26 may generate the second clock signal CLK2 decreased to a logic "low" level when the voltage of the ramp signal Vramp is less than the second comparison voltage VC 2.

The latch 28 may generate the internal clock signal ICLK increased to a logic "high" level in response to the first clock signal CLK1 being at a logic "high" level and decreased to a logic "low" level in response to the second clock signal CLK2 being at a logic "high" level. The latch 28 may be an SR latch. In the internal clock signal generators 14 to 16 shown in fig. 4, in response to the control data de, the first comparison voltage VC1 may be variably set in the arrow direction shown in fig. 5, and the second comparison voltage VC2 may be variably set in the arrow direction shown in fig. 5. The start time point of the first clock signal CLK1 and the start time point of the second clock signal CLK2 may be variably set, and thus the start time point and the end time point of the internal clock signal ICLK may be variably set.

As another example, the first comparison voltage VC1 may be variably set, and the second comparison voltage VC2 may be fixed. Accordingly, the start time point of the first clock signal CLK1 may be variably set, and the start time point of the second clock signal CLK2 may be fixed, so that the start time point of the internal clock signal ICLK may be changed, and the end time point of the internal clock signal ICLK may be fixed. Further, as another example, the first comparison voltage VC1 may be fixed and the second comparison voltage VC2 may be variably set. Accordingly, the start time point of the first clock signal CLK1 may be fixed, and the start time point of the second clock signal CLK2 may be variably set, and thus the start time point of the internal clock signal ICLK may be fixed, and the end time point of the internal clock signal ICLK may be variably set. That is, the internal clock signal generators 14-16 shown in fig. 4 may variably set the start time point and/or the end time point of the internal clock signal ICLK in response to the control data de.

Fig. 6 is a diagram illustrating a configuration of a voltage generator according to an example embodiment of the inventive concept, and the voltage generator VR1 illustrated in fig. 6 may include a high-side switching transistor Q1, a low-side switching transistor Q2, an inductor L, and a capacitor C.

Referring to fig. 6, the internal clock signal ICLK may be applied to the high-side switching transistor Q1, and the internal clock signal iclklklkll may be applied to the low-side switching transistor Q2. The high-side switching transistor Q1 may be turned on in response to the internal clock signal ICLK being at a logic "high" level, and the low-side switching transistor Q2 may be turned on in response to the internal clock signal iclkll being at a logic "high" level. The voltage generator shown in fig. 6 illustrates a well-known buck converter, and the buck converter may perform a switching operation in response to the internal clock signals ICLK and iclklkll and generate the internal power supply voltage V1 using (pull-down) the external power supply voltage Vdd.

Fig. 7 is a table illustrating control data according to module IDs of a plurality of control data registers of a register unit according to an example embodiment of the inventive concepts.

Referring to fig. 7, 8 different control data C1 through C8 may be stored in 8 control data registers corresponding to 8 module IDs (e.g., "000," "001," "010," "011," "100," "101," "110," and "111"). The 8 control data registers may be configured to output corresponding control data according to the module ID stored in the module ID register. Alternatively, the 8 control data registers may be configured to output 8 different control data C1 through C8 in response to 8 different register addresses corresponding to 8 module IDs. Each of the plurality of register addresses may be a predetermined number of bits (e.g., 8 bits or more of data) of digital data, and each of the plurality of control data C1 through C8 may be a predetermined number of bits of digital data (e.g., 8 bits or more of data).

Referring to fig. 4 to 7, the internal clock signal generator 14-16, the first comparison voltage VC1, and/or the second comparison voltage VC2 may be changed in response to 8 different control data C1 to C8, so that a start time point and/or an end time of the internal clock signal ICLK may be variably set. For example, the internal clock signal generators 14-16 may generate the internal clock signal ICLK having a basic frequency in response to the control data C5, differently advance a start time point and/or an end time point of the internal clock signal ICLK in response to the control data C6 through C8, and differently delay the start time point and/or the end time point of the internal clock signal ICLK in response to the control data C1 through C4. In this case, the basic frequency of the internal clock signal ICLK may be maintained or changed in response to the control data C1 through C8.

Fig. 8 is an operation timing diagram for describing local data communication between the serial presence detector and the power management unit PMU according to an example embodiment of the inventive concept, and is a diagram for describing an operation in which the serial presence detector 12 writes a module ID into the power management unit 14 according to the I2C protocol.

Referring to FIG. 8, upon receiving the module ID mid, the serial presence detector 12 may perform local data communication for transmitting the module ID mid to the power management unit 14.

First, the serial presence detector 12 may send a START signal START to the power management unit 14. The serial presence detector 12 may transmit, as the local serial data LSDA, an 8-bit local device address (i.e., 4-bit local device IDs I6 through I3 (e.g., local device ID "1001" of the power management unit 14) + a 3-bit module ID I2 through I0 (e.g., "111") + 1-bit write command (e.g., "0" indicating a write command) indicating a corresponding module ID (e.g., "010") through 1 bit in response to the local serial clock signal LSCL. The power management unit 14 may receive the local device address and, when the local device address includes the corresponding local device ID and the module ID indicating the corresponding module ID, transmit a reception acknowledgement signal ACK as local serial data LSDA to the serial presence detector 12.

Next, the serial presence detector 12 may send 8-bit register addresses A7 through A0 (e.g., the register addresses of the module ID registers of the register units 14-14 shown in FIG. 3) to the power management unit 14 as local serial data LSDA over 1 bit in response to the local serial clock signal LSCL. Upon receiving the register address, the power management unit 14 may send a reception acknowledgement signal ACK to the serial presence detector 12.

Finally, the serial presence detector 12 may transmit data D7 to D0 including 3-bit module IDs D2 to D0 (e.g., "00000") + 3-bit module IDs (e.g., "010") to the power management unit PMU 14 as local serial data LSDA by 1 bit in response to the local serial clock signal LSCL. Upon receiving the module ID, the power management unit 14 may send a reception acknowledgement signal ACK to the serial presence detector 12. The power management unit 14 may store the data D7-D0 in the module ID registers of the register units 14-14. The power management unit PMU 14 may generate data D7 to D0 stored in the module ID register or control data de stored in the control data register according to the module IDs D2 to D0.

The serial presence detector 12 may end the communication by sending a reception non-acknowledgement signal NACK and a STOP signal STOP to the power management unit 14 after sending the data D7-D0 to the power management unit 14. According to the example embodiment shown in fig. 8, when serial presence detector 12 sends a module ID to power management unit PMU 14, power management unit 14 may generate control data de from a control data register corresponding to the module ID.

Fig. 9 is an operation timing diagram for describing local data communication between the serial presence detector and the power management unit according to an example embodiment of the inventive concepts, and is a diagram for describing an operation in which the serial presence detector 12 reads control data from the power management unit 14 according to the I2C protocol.

Referring to FIG. 9, upon receiving the module ID mid, the serial presence detector 12 may send a START signal START to the power management unit 14. The serial presence detector 12 may transmit an 8-bit local device address (i.e., 4-bit local device IDs I6 through I3 (e.g., "1001") + a 3-bit module ID (e.g., "111") + a 1-bit write command (e.g., "0")) indicating a corresponding module ID (e.g., "010") to the power management unit 14 as local serial data LSDA by 1 bit in response to the local serial clock signal LSCL. The power management unit 14 may receive the local device address and, when the local device address includes the corresponding local device ID and the module ID indicating the corresponding module ID, transmit a reception acknowledgement signal ACK as local serial data LSDA to the serial presence detector 12.

Next, the serial presence detector 12 may transmit 8-bit register addresses a7 through a0 (e.g., register addresses corresponding to corresponding module IDs among register addresses of a plurality of control data registers of the register units 14-14 shown in fig. 3) to the power management unit 14 as local serial data LSDA by 1 bit in response to the local serial clock signal LSCL. Upon receiving the register address, the power management unit 14 may send a reception acknowledgement signal ACK as local serial data LSDA to the serial presence detector 12.

Next, the serial presence detector 12 may send a restart signal R START to the power management unit 14. The serial presence detector 12 may transmit an 8-bit local device address (i.e., 4-bit local device addresses I6 through I3 (e.g., "1001") + a 3-bit module ID I2 through I0 (e.g., "111") + a 1-bit read command (e.g., "1" indicating a read command) indicating a corresponding module ID (e.g., "010") to the power management unit PMU 14 as local serial data LSDA by 1 bit in response to the local serial clock signal LSCL. Upon receiving the register address, the power management unit 14 may send a reception acknowledgement signal ACK as local serial data LSDA to the serial presence detector 12.

The power management unit 14 may send a reception acknowledgement signal ACK to the serial presence detector 12. The power management unit 14 may generate the control data de in response to the register address from a control data register selected from among a plurality of control data registers. Accordingly, a start time point and/or an end time point of the internal clock signal ICLK may be set. The power management unit 14 may send data D7 through D0 corresponding to the control data de to the serial presence detector 12.

The serial presence detector 12 may transmit the reception non-acknowledgement signal NACK and the STOP signal STOP after receiving the data D7 through D0 from the power management unit 14, and end the communication.

According to the example embodiment shown in fig. 9, when the serial presence detector 12 transmits a register address corresponding to the module ID to the power management unit 14, the power management unit 14 may generate the control data de from the control data register corresponding to the register address.

Fig. 10 is an operation timing diagram for describing global data communication between an external device and a serial presence detector, according to an example embodiment of the inventive concepts, and is a diagram for describing an operation in which the external device transmits data to the serial presence detector 12.

Referring to fig. 10, the external device may transmit a START signal START to the serial presence detector 12. The external device may transmit an 8-bit local device address (i.e., 4-bit local device IDs I6 through I3 (e.g., "1001") + 3-bit corresponding module IDs I2 through I0 (e.g., "010") + 1-bit write command (e.g., "0")) to the serial presence detector 12 through 1 bit as the global serial data SDA in response to the global serial clock signal SCL. The serial presence detector 12 may receive the local device address and transmit a reception acknowledgement signal ACK as global serial data to the external device when the local device address includes the corresponding local device ID and the corresponding module ID.

Next, the external device may transmit 8-bit register addresses a7 through a0 (e.g., register addresses corresponding to corresponding module IDs among register addresses of a plurality of control data registers of the register units 14-14 shown in fig. 3) to the serial presence detector 12 as the global serial data SDA by 1 bit in response to the global serial clock signal SCL. Upon receiving the register address, the serial presence detector 12 may send a reception acknowledgement signal ACK as global serial data SDA to the external device.

Next, the external device may send a restart signal R START to the serial presence detector 12. The external device may transmit an 8-bit local device address (i.e., 4-bit local device IDs I6 through I3 (e.g., "1001") + 3-bit corresponding module ID (e.g., "010") + 1-bit read command (e.g., "1" indicating a read command) to the serial presence detector 12 through 1 bit as the global serial data SDA in response to the global serial clock signal SCL. Upon receiving the register address, the serial presence detector 12 may send a reception acknowledgement signal ACK as global serial data SDA to the external device.

Fig. 11 is an operation timing diagram for describing local data communication between the serial presence detector and the power management unit according to an exemplary embodiment of the inventive concept, for example, a diagram for describing that the serial presence detector 12 transmits data related to the power management unit 14, which is transmitted from an external device, to the power management unit 14.

The operation timing diagram shown in fig. 11 may be the same as the operation timing diagram shown in fig. 9, and the operation timing diagram shown in fig. 11 will be easily understood with reference to the description of fig. 9 described above.

According to the example embodiments described in fig. 10 and 11, the external device may transmit a register address corresponding to the module ID to the serial presence detector 12, the serial presence detector 12 may transmit the register address to the power management unit 14, and the power management unit 14 may generate the control data de from the control data register corresponding to the register address.

Fig. 12 is a block diagram illustrating a configuration of a memory module according to an example embodiment of the inventive concept, and a memory module 100 'illustrated in fig. 12 may be configured to not include the power management unit 12 of the memory module 100 illustrated in fig. 1, and may include a power management unit 14' instead of the power management unit 14 illustrated in fig. 1.

Referring to fig. 12, the power management unit 14' may perform global data communication according to a serial data communication protocol through a lane including a serial clock signal terminal SCLP and a serial data terminal SDAP. The power management unit 14' can detect a passive component (e.g., a resistor) connected to the module position identification terminal MIDP, and generate a module ID mid. The power management unit 14' may detect the current or voltage of the module position identification terminal MIDP, and generate the module ID mid. Unlike the configuration shown in fig. 12, the power management unit 14 'may detect voltages applied to at least two module location identification terminals (e.g., an external power supply voltage and/or a ground voltage applied to the memory module 100') and generate the module ID mid. The power management unit 14' may perform local data communications with the temperature sensor 16 and the register clock driver 18 over a channel that includes a local serial clock signal line LSCLL and a local serial data line LSDAL.

The power management unit 14' may generate a predetermined number of internal power supply voltages using the external power supply voltage. Upon receiving the module ID mid, the power management unit 14' may store the module ID in the module ID register. The power management unit 14' may set a start time point and/or an end time point of the internal clock signal ICLK based on the module ID stored in the module ID register. Alternatively, the power management unit 14' may set the start time point and/or the end time point of the internal clock signal ICLK based on the register address corresponding to the module ID.

Although not shown, the power management unit 14' may apply a predetermined number of internal power supply voltages to the 4n semiconductor memory devices M11 through M1n, M21 through M2n, M31 through M3n, and M41 through M4n, the temperature sensor 16, and the register clock driver 18.

Fig. 13 is a block diagram illustrating a configuration of a power management unit, and the power management unit 14 'may include a global interface unit 14-10', a control logic unit 14-12', a register unit 14-14', an internal clock signal generator 14-16', a voltage regulator 14-18', a module position detector 14-20', and a local interface unit 14-22', according to an example embodiment of the inventive concepts.

The function of each block shown in fig. 13 will be described below.

The global interface units 14-10', control logic units 14-12', register units 14-14 'and module location detectors 14-20' may perform the same functions as the global interface units 12-10, control logic units 12-14, register units 12-16 and module location detectors 12-12, respectively, shown in FIG. 2.

The internal clock signal generator 14-16 'and the voltage regulator 14-18' may perform the same functions as the internal clock signal generator 14-16 and the voltage regulator 14-18, respectively, shown in fig. 3.

That is, the power management unit 14' shown in fig. 13 may have a configuration in which the serial presence detector 12 shown in fig. 2 and the power management unit 14 shown in fig. 3 are integrated. Therefore, the power supply management unit 14' can perform local data communication with the serial presence detector 12, and without adjusting the start time point and/or the end time point of the internal clock signal ICLK, when receiving the module ID mid, the start time point and/or the end time point of the internal clock signal ICLK is set in response to the control data de generated from the module ID mid or the register address corresponding to the module ID mid. The power management unit 14' may directly perform global data communication with the external device and receive a register address corresponding to the module ID mid and set a start time point and/or an end time point of the internal clock signal ICLK in response to the control data de generated according to the register address.

Upon receiving the module ID mid, the control logic unit 14-12' may generate the register address of the module ID register as the address addl and generate the module ID mid as the data d. As another example, when receiving a module ID mid, the control logic unit 14-12' may generate a register address corresponding to the module ID mid as the address addl. Further, as another example, when data da is received, control logic unit 14-12' may generate a register address of one of a plurality of control data registers included in data da as address addl.

The register unit 14-14' may store the module ID in the module ID register, and generate one control data of the plurality of control data as the control data de in response to the module ID. As another example, register unit 14-14' may generate control data de from a control data register corresponding to the register address.

The internal clock signal generator 14-16' may set a start time point and/or an end time point of the internal clock signal ICLK in response to the control data de.

Fig. 14 is an operation timing diagram for describing global data communication between an external device and a power management unit according to an example embodiment of the inventive concepts, for example, a diagram for describing an operation in which the external device reads data from the power management unit 14' according to the I2C protocol.

The operation timing chart shown in fig. 14 may be the same as the operation timing chart shown in fig. 11 except that the external device does not transmit the module ID (e.g., "111") indicating the corresponding module ID (e.g., "010") but transmits the corresponding module ID (e.g., "010") when transmitting the local device address to the power management unit 14'. Therefore, the power management unit 14 'can output the control data de from the control data register corresponding to the register address among the plurality of control data registers of the register units 14 to 14'. The power management unit 14' may set a start time point and/or an end time point of the internal clock signal ICLK according to the control data de. Further, the power management unit 14' may transmit data D7 through D0 corresponding to the control data de to the external device, and the external device may transmit a reception non-acknowledgement signal NACK and a STOP signal STOP after receiving the data D7 through D0 and end the communication.

Fig. 15 is a block diagram illustrating a configuration of a memory system according to an example embodiment of the inventive concept, and the memory system 200 may include a control unit 30 mounted on a motherboard 20, i module slots (module slots) MS1 through MSi, and i memory modules MD1 through MDi.

Referring to fig. 15, the memory system 200 may include i module ID resistors R1 to Ri connected to i module slots MS1 to MSi. The i module ID resistors R1 to Ri may be connected to an external power supply voltage Vdd line disposed on the main board 20, and have different resistances. The i module ID resistors R1 to Ri may be connected to the module position identification terminals MIDP of the i memory modules MD1 to MDi, respectively. The control unit 30 may include a global interface unit 32 and a memory controller 34. The left data line DQLL, the first command/address line CA1L, the second command/address line CA2L, the right data line DQRL, the global serial data line GSDAL, and the global serial clock signal line GSCLL may be disposed on the main board 20.

Although not shown, the left data line DQLL, the first command/address line CA1L, the second command/address line CA2L, and the right data line DQRL may be generally connected to the left data terminal DQLP, the first command/address terminal CA1P, the second command/address terminal CA2P, and the right data terminal DQRP, respectively, of each of the i memory modules MD 1-MDi. Further, the global serial data line GSDAL and the global serial clock signal line GSCLL may be commonly connected to the serial data terminal SDAP and the serial clock signal terminal SCKP of each of the i memory modules MD1 to MDi, respectively.

Referring to fig. 15, when each of the i memory modules MD1 through MDi is mounted in a corresponding module slot MS1, MS2 … …, or MSi, each of the i memory modules MD1 through MDi may detect a corresponding module ID resistor R1, R2 … …, or Ri connected to a corresponding module position identification terminal MIDP and identify a corresponding module ID. For example, when each of the 8 memory modules MD 1-MD 8 is mounted in a corresponding module slot MS1, MS2 … …, or MS8, each of the 8 memory modules MD 1-MD 8 may identify "000", "001", "010", "011", "100", "101", "110", or "111" as a corresponding module ID.

The i memory modules MD1 through MDi shown in fig. 15 may have the configuration described above with reference to fig. 1 through 11 and perform the operations described above with reference to fig. 1 through 11, and upon receiving the module ID mid, the serial presence detector 12 may perform local data communication with the power management unit 14 to transmit the module ID or the register address corresponding to the module ID, and the power management unit 14 may generate the control data de from the module ID or the register address corresponding to the module ID. Alternatively, global data communication and local data communication are performed among the control unit 30, the serial presence detector 12, and the power management unit 14, and the register address is transmitted to the power management unit 14, so the power management unit 14 can generate the control data de. Accordingly, the start time point and/or the end time point of the internal clock signal ICLK of the i memory modules MD1 through MDi may be set differently.

Further, the i memory modules MD1 to MDi shown in fig. 15 may have the configuration described above with reference to fig. 12 to 14 and perform the operations described above with reference to fig. 12 to 14, and when receiving the module ID mid, the power management unit 14' may generate the control data de according to the module ID or the register address corresponding to the module ID. Alternatively, global data communication is performed between the control unit 30 and the power management unit 14', and the register address is transmitted to the power management unit 14', so the power management unit 14' can generate the control data de. Accordingly, the start time point and/or the end time point of the internal clock signal ICLK of the i memory modules MD1 through MDi may be set differently.

Referring to fig. 15, since the i memory modules MD1 through MDi may share the global serial data line GSDAL and the global serial clock signal line GSCLL, a total of i global data communications may be sequentially performed to generate the control data de of the i memory modules MD1 through MDi.

However, unlike the configuration shown, the storage system may have a configuration in which: the global serial data line GSDAL is commonly connected to the i memory modules MD1 to MDi, and the i global serial clock signal lines GSCLL are respectively connected to the i memory modules MD1 to MDi, and one global data communication may be performed to generate the control data de of the i memory modules MD1 to MDi.

As a result, the start time point and/or the end time point of the internal clock signal ICLK of the i memory modules MD1 through MDi may be set differently, and thus the operation time points of the voltage regulators 14-18 or 14-18 'of the power management unit 14 or 14' may be different from each other. Therefore, the external power supply voltage drop due to the same operation time point of the voltage regulator 14-18 or 14-18 'of the power management unit 14 or 14' does not occur. Therefore, the internal power supply voltage can be stably generated.

According to the above-described exemplary embodiments, the example in which the module position detector generates the module ID is described, however, there may be an example in which the module position detector is not included. In this case, the control unit may transmit the corresponding module ID of each of the i memory modules to each of the i memory modules.

According to the above-described exemplary embodiments, the example in which the module position detector generates the module ID from the passive component connected to one module position identification terminal MIDP is described, however, the module position detector may generate the module ID by detecting the voltages applied to at least two module position identification terminals. For example, when there are 3 module location identification terminals, 8 different module IDs may be generated by detecting at least two voltages (e.g., a power supply voltage and a ground voltage) applied to the 3 module location identification terminals.

According to the above-described example embodiments, the memory module may stably generate the internal power supply voltage by changing the start time point and/or the end time point of the internal clock signal based on the module ID. In addition, the memory system having a plurality of memory modules may stably generate an internal power supply voltage by differently controlling start time points and/or end time points of internal clock signals of a plurality of power management units included in the plurality of memory modules. Accordingly, reliability of operation of the memory module and the memory system having the same can be ensured.

Although the embodiments of the present inventive concept have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various modifications may be made without departing from the scope of the present inventive concept and without changing essential features of the present inventive concept. Accordingly, the above-described embodiments should be considered in a descriptive sense only and not for purposes of limitation.