阅读说明：本技术 调整时序的方法、装置、计算机设备及介质 (Method, device, computer equipment and medium for adjusting time sequence ) 是由 蒋伟华 简卫 张欣 董火新 车诒桓 于 2020-06-23 设计创作，主要内容包括：本申请适用于时序信号修复技术领域,提供了一种调整时序的方法、装置、计算机设备及介质,其中,一种调整时序的方法,通过确定时序路径中待调整时序的第一目标时序元件,再测算第一目标时序元件与其上一级时序元件,即与第二目标时序元件之间的目标时钟偏斜值,由于第一目标时序元件为时序路径中待调整时序的时序元件,且测算所得的目标时钟偏斜值,可直接对该第一目标时序元件的时序违例进行修复,因此将该目标时钟偏斜值配置到预设的时钟树综合文件中,得到目标时钟树综合文件,通过执行目标时钟树综合文件,即可对第一目标时序元件进行时序调整操作,无需对时序电路进行多次迭代调整,提高了对时序电路进行时序调整的效率。(The application is applicable to the technical field of time sequence signal restoration, and provides a method, a device, a computer device and a medium for adjusting time sequence, wherein, the method for adjusting time sequence comprises the steps of determining a first target time sequence element of time sequence to be adjusted in a time sequence path, measuring and calculating a target clock skew value between the first target time sequence element and a previous time sequence element thereof, namely a second target time sequence element, directly restoring a time sequence violation of the first target time sequence element because the first target time sequence element is the time sequence element of time sequence to be adjusted in the time sequence path, measuring and calculating the obtained target clock skew value, configuring the target clock skew value into a preset clock tree comprehensive file to obtain a target clock tree comprehensive file, and performing time sequence adjustment operation on the first target time sequence element by executing the target clock tree comprehensive file, the time sequence circuit does not need to be adjusted in an iterative mode for many times, and the time sequence adjusting efficiency of the time sequence circuit is improved.)

1. A method for adjusting timing, comprising:

determining a first target sequential element of a sequential path to be adjusted in time sequence; the timing path comprises at least two hierarchical timing elements;

evaluating a target clock skew value between the first target sequential element and a second target sequential element; wherein the second target sequential element is a previous stage sequential element of the first target sequential element;

configuring the target clock skew value into a preset clock tree comprehensive file to obtain a target clock tree comprehensive file;

and executing the target clock tree comprehensive file, and performing timing adjustment operation on the first target timing element.

2. The method of claim 1, wherein determining a first target sequential element in a timing path whose timing is to be adjusted comprises:

inputting a clock signal and a data signal to the timing path;

acquiring a data signal establishing time and a data signal holding time which are determined by each intermediate time sequence element based on the clock signal and the data signal in the time sequence path; the intermediate sequential elements are the other sequential elements except the first-stage sequential element in the sequential path;

Determining the first target sequential element from the sequential path based on the data signal setup time and the data signal hold time corresponding to each of the intermediate sequential elements.

3. The method of claim 2, wherein determining the first target sequential element from the timing path based on the data signal setup time and the data signal hold time for each intermediate sequential element comprises:

judging whether the data signal establishing time and the data signal holding time corresponding to each intermediate sequential element meet the following constraint conditions:

T_Cn-1+T_Qn-1+T_L+T_Setup≤T_Cn+T_P；

T_Cn-1+T_Qn-1+T_L-T_Hold≥T_Cn；

wherein, T_Cn-1A delay time for a preceding sequential element of the intermediate sequential elements to receive the clock signal; t is_Qn-1An internal transition time of a preceding sequential element of the intermediate sequential element; t is_LDelaying a transmission path between the intermediate sequential element and a sequential element of a previous stage thereof by a time; t is_SetupEstablishing time for the data signal corresponding to the intermediate sequential element; t is_CnA delay time for the intermediate sequential element to receive the clock signal; t is_PA period of the clock signal; t is _HoldHolding time for the data signal corresponding to the intermediate sequential element;

identifying an intermediate sequential element that does not satisfy the constraint as the first target sequential element.

4. The method of claim 3, wherein the calculating a target clock skew value between the first target sequential element and a second target sequential element comprises:

if the first target sequential element is an intermediate sequential element of which the data signal establishing time does not meet the constraint condition, acquiring the time when a first data signal corresponding to the first target sequential element is keptInter T_{Hold_1}And maintaining a time T based on the first data signal_{Hold_1}Measuring and calculating the target clock skew value;

if the first target sequential element is an intermediate sequential element of which the data signal retention time does not meet the constraint condition, acquiring a first data signal establishment time T corresponding to the first target sequential element_{Setup_1}And establishing a time T based on said first data signal_{Setup_1}And measuring and calculating the target clock skew value.

5. The method of claim 4, wherein a holding time T is maintained based on the first data signal _{Hold_1}Evaluating the target clock skew value, comprising:

measuring and calculating a first value interval of the target clock skew value through the following formula:

T_FF1-T_FF2≤T_FFQ2+T_LD-T_{Hold_1}and (T)_FFQ2+T_LD-T_{Hold_1})>0；

Wherein, T_FF1A clock signal delay time for the first target sequential element; t is_FF2A clock signal delay time for the second target sequential element; t is_FF1-T_FF2The first value interval is obtained; t is_FFQ2An internal transition time for the second target sequential element; t is_LDDelaying a transmission path delay time between the first target sequential element and the second target sequential element; t is_{Hold_1}Holding time for a first data signal corresponding to the first target sequential element;

determining the target clock skew value from the first span based on a clock skew margin between the second target sequential element and a third target sequential element, and/or a clock skew margin between the second target sequential element and a fourth target sequential element; the third target sequential element is a previous-stage sequential element of the second target sequential element, and the fourth target sequential element is a next-stage sequential element of the first target sequential element.

6. The method of claim 4, wherein the time T is established based on the first data signal _{Setup_1}Evaluating the target clock skew value, comprising:

and measuring and calculating a second value interval of the target clock skew value by the following formula:

T_FF2-T_FF1≤T_P-T_FFQ2-T_LD-T_{Setup_1}and (T)_P-T_FFQ2-T_LD-T_{Setup_1})>0；

Wherein, T_FF1A clock signal delay time for the first target sequential element; t is_FF2A clock signal delay time for the second target sequential element; t is_FF2-T_FF1Is the second value interval; t is_PA period of the clock signal; t is_FFQ2An internal transition time for the second target sequential element; t is_LDDelaying a transmission path delay time between the first target sequential element and the second target sequential element; t is_{Setup_1}Establishing time for a first data signal corresponding to the first target sequential element;

determining the target clock skew value from the second span based on a clock skew margin between the second target sequential element and a third target sequential element, and/or a clock skew margin between the second target sequential element and a fourth target sequential element; the third target sequential element is a previous-stage sequential element of the second target sequential element, and the fourth target sequential element is a next-stage sequential element of the first target sequential element.

7. The method of any of claims 1 to 6, wherein the executing the target clock tree integration file to perform a timing adjustment operation on the first target timing element comprises:

Acquiring the number of the first target sequential elements;

configuring a respective set of buffer nodes based on the number of the first target sequential elements;

allocating a buffer node in the set of buffer nodes between the first target sequential element and the second target sequential element to complete a timing adjustment operation; the buffer node is to describe the target clock skew value.

8. An apparatus for adjusting timing, comprising:

the timing adjustment device comprises a determining unit, a timing adjusting unit and a control unit, wherein the determining unit is used for acquiring a first target timing element of a timing to be adjusted in a timing path; the timing path comprises at least two hierarchical timing elements;

a measurement unit to measure a target clock skew value between the first target sequential element and a second target sequential element; wherein the second target sequential element is a previous stage sequential element of the first target sequential element;

the configuration unit is used for configuring the target clock skew value into a preset clock tree comprehensive file to obtain a target clock tree comprehensive file;

and the execution unit is used for executing the target clock tree comprehensive file and performing time sequence adjustment operation on the first target time sequence element.

9. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the computer device, wherein the processor implements the steps of the method for adjusting timing according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, in which a computer program is stored, which, when being executed by a processor, carries out the steps of the method for adjusting a timing sequence according to any one of claims 1 to 7.

Technical Field

The present application relates to the field of timing signal restoration technology, and in particular, to a method and an apparatus for adjusting a timing, a computer device, and a computer-readable storage medium.

Background

The timing path refers to a circuit path including a timing element, and is widely applied to various computing devices, for example, a path composed of a plurality of levels of registers in a controller CPU is a timing path. Because the timing path includes timing elements, such as registers in the CPU, when the timing path is designed, timing adjustment needs to be performed on the timing path to ensure that the timing elements in the timing path can work normally.

Disclosure of Invention

In view of this, embodiments of the present application provide a method and an apparatus for adjusting a timing sequence, a computer device, and a computer readable storage medium, so as to solve the problem that the efficiency of adjusting the timing sequence is low in the existing scheme for adjusting the timing sequence.

A first aspect of an embodiment of the present application provides a method for adjusting a timing sequence, including:

determining a first target sequential element of a sequential path to be adjusted in time sequence; the timing path comprises at least two hierarchical timing elements;

evaluating a target clock skew value between the first target sequential element and a second target sequential element; wherein the second target sequential element is a previous stage sequential element of the first target sequential element;

configuring the target clock skew value into a preset clock tree comprehensive file to obtain a target clock tree comprehensive file;

and executing the target clock tree comprehensive file, and performing timing adjustment operation on the first target timing element.

In the foregoing solution, the determining a first target sequential element to be adjusted in a timing path includes:

inputting a clock signal and a data signal to the timing path;

acquiring a data signal establishing time and a data signal holding time which are determined by each intermediate time sequence element based on the clock signal and the data signal in the time sequence path; the intermediate sequential elements are the other sequential elements except the first-stage sequential element in the sequential path;

Determining the first target sequential element from the sequential path based on the data signal setup time and the data signal hold time corresponding to each of the intermediate sequential elements.

In the foregoing solution, the determining the first target sequential element from the sequential path based on the data signal setup time and the data signal hold time corresponding to each intermediate sequential element includes:

judging whether the data signal establishing time and the data signal holding time corresponding to each intermediate sequential element meet the following constraint conditions:

T_Cn-1+T_Qn-1+T_L+T_Setup≤T_Cn+T_P；

T_Cn-1+T_Qn-1+T_L-T_Hold≥T_Cn；

wherein, T_Cn-1A delay time for a preceding sequential element of the intermediate sequential elements to receive the clock signal; t is_Qn-1An internal transition time of a preceding sequential element of the intermediate sequential element; t is_LDelaying a transmission path between the intermediate sequential element and a sequential element of a previous stage thereof by a time; t is_SetupEstablishing time for the data signal corresponding to the intermediate sequential element; t is_CnA delay time for the intermediate sequential element to receive the clock signal; t is_PA period of the clock signal; t is_HoldHolding time for the data signal corresponding to the intermediate sequential element;

Identifying an intermediate sequential element that does not satisfy the constraint as the first target sequential element.

In the foregoing solution, the calculating a target clock skew value between the first target sequential element and the second target sequential element includes:

if the first target sequential element is an intermediate sequential element of which the data signal establishing time does not meet the constraint condition, acquiring a first data signal holding time T corresponding to the first target sequential element_{Hold_1}And maintaining a time T based on the first data signal_{Hold_1}Measuring and calculating the target clock skew value;

if the first target sequential element is an intermediate sequential element of which the data signal retention time does not meet the constraint condition, acquiring a first data signal establishment time T corresponding to the first target sequential element_{Setup_1}And establishing a time T based on said first data signal_{Setup_1}And measuring and calculating the target clock skew value.

In the above scheme, the holding time T based on the first data signal_{Hold_1}Evaluating the target clock skew value, comprising:

measuring and calculating a first value interval of the target clock skew value through the following formula:

T_FF1-T_FF2≤T_FFQ2+T_LD-T_{Hold_1}and (T)_FFQ2+T_LD-T_{Hold_1})>0；

Wherein, T_FF1A clock signal delay time for the first target sequential element; t is _FF2A clock signal delay time for the second target sequential element; t is_FF1-T_FF2The first value interval is obtained; t is_FFQ2An internal transition time for the second target sequential element; t is_LDDelaying a transmission path delay time between the first target sequential element and the second target sequential element; t is_{Hold_1}Holding time for a first data signal corresponding to the first target sequential element;

determining the target clock skew value from the first span based on a clock skew margin between the second target sequential element and a third target sequential element, and/or a clock skew margin between the second target sequential element and a fourth target sequential element; the third target sequential element is a previous-stage sequential element of the second target sequential element, and the fourth target sequential element is a next-stage sequential element of the first target sequential element.

In the above scheme, the time T is established based on the first data signal_{Setup_1}Evaluating the target clock skew value, comprising:

and measuring and calculating a second value interval of the target clock skew value by the following formula:

T_FF2-T_FF1≤T_P-T_FFQ2-T_LD-T_{Setup_1}and (T)_P-T_FFQ2-T_LD-T_{Setup_1})>0；

Wherein, T_FF1A clock signal delay time for the first target sequential element; t is _FF2A clock signal delay time for the second target sequential element; t is_FF2-T_FF1Is the second value interval; t is_PA period of the clock signal; t is_FFQ2An internal transition time for the second target sequential element; t is_LDDelaying a transmission path delay time between the first target sequential element and the second target sequential element; t is_{Setup_1}Establishing time for a first data signal corresponding to the first target sequential element;

determining the target clock skew value from the second span based on a clock skew margin between the second target sequential element and a third target sequential element, and/or a clock skew margin between the second target sequential element and a fourth target sequential element; the third target sequential element is a previous-stage sequential element of the second target sequential element, and the fourth target sequential element is a next-stage sequential element of the first target sequential element.

In the foregoing solution, the executing the target clock tree integration file to perform a timing adjustment operation on the first target timing element includes:

acquiring the number of the first target sequential elements;

configuring a respective set of buffer nodes based on the number of the first target sequential elements;

Allocating a buffer node in the set of buffer nodes between the first target sequential element and the second target sequential element to complete a timing adjustment operation; the buffer node is to describe the target clock skew value.

A second aspect of the embodiments of the present application provides an apparatus for adjusting a timing sequence, including:

the timing adjustment device comprises a determining unit, a timing adjusting unit and a control unit, wherein the determining unit is used for acquiring a first target timing element of a timing to be adjusted in a timing path; the timing path comprises at least two hierarchical timing elements;

a measurement unit to measure a target clock skew value between the first target sequential element and a second target sequential element; wherein the second target sequential element is a previous stage sequential element of the first target sequential element;

the configuration unit is used for configuring the target clock skew value into a preset clock tree comprehensive file to obtain a target clock tree comprehensive file;

and the execution unit is used for executing the target clock tree comprehensive file and performing time sequence adjustment operation on the first target time sequence element.

A third aspect of embodiments of the present application provides a computer device, which includes a memory, a processor, and a computer program stored in the memory and executable on the computer device, where the processor implements the steps of the method for adjusting timing provided in the first aspect when executing the computer program.

A fourth aspect of embodiments of the present application provides a computer-readable storage medium, which stores a computer program, and when the computer program is executed by a processor, the computer program implements the steps of the method for adjusting timing provided in the first aspect.

A fifth aspect of the embodiments of the present application provides a computer program product, which when run on a computer device, causes the computer device to execute the steps of the method for adjusting timing sequence of any one of the above first aspects.

The method, the device, the computer equipment and the computer readable storage medium for adjusting the time sequence provided by the embodiment of the application have the following beneficial effects:

the method for adjusting time sequence provided by the embodiment of the application comprises the steps of determining a first target time sequence element of the time sequence to be adjusted in a time sequence path, measuring and calculating a target clock skew value between the first target time sequence element and a previous time sequence element thereof, namely a second target time sequence element, directly repairing the time sequence violation of the first target time sequence element as the first target time sequence element is the time sequence element of the time sequence to be adjusted in the time sequence path and measuring and calculating the obtained target clock skew value, configuring the target clock skew value into a preset clock tree comprehensive file to obtain a target clock tree comprehensive file, executing the target clock tree comprehensive file to perform time sequence adjustment operation on the first target time sequence element, not needing to perform multiple iterative adjustments on a time sequence circuit, and reducing the time cost for performing time sequence adjustment on the time sequence path, the efficiency of carrying out the chronogenesis adjustment to the chronogenesis circuit has been improved.

In addition, when a first target sequential element of a time sequence to be adjusted in a sequential path is obtained, a first target sequential element of which the data signal establishing time and/or the data signal holding time do not meet the constraint condition is determined based on the data signal establishing time and the data signal holding time corresponding to each intermediate sequential element in the sequential path, when a target clock skew value between the first target sequential element and a second target sequential element is measured, the data signal establishing time and the data signal holding time of the first target sequential element are considered at the same time, a target clock skew value suitable for the data signal establishing time and the data signal holding time of the first target sequential element is determined and configured in a preset clock tree comprehensive file to obtain a target clock tree comprehensive file, the target clock tree comprehensive file is executed, and when the clock skew layout of the sequential path is presented, a timing adjustment operation for the first target sequential element is achieved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.

Fig. 1 is a flowchart illustrating an implementation of a method for adjusting a timing sequence according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a timing path;

FIG. 3 is a diagram of the normal timing relationship of clock signals to data signals;

FIG. 4 is a schematic diagram of a comparison between a clock signal and a plurality of data signals;

FIG. 5 is a flowchart illustrating an implementation of a method for adjusting timing according to another embodiment of the present application;

FIG. 6 is a block diagram of an apparatus for adjusting timing according to an embodiment of the present disclosure;

fig. 7 is a block diagram of a computer device according to another embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

The method for adjusting a timing sequence provided by the embodiment is applied to a computer device, that is, the main execution body of the method for adjusting a timing sequence is the computer device. Here, the computer device specifically includes a computer device for designing and/or debugging a timing path. In all embodiments of the present application, the computer device further completes the timing adjustment operation on the timing path by executing the method for adjusting the timing provided in this embodiment.

Referring to fig. 1, fig. 1 is a flowchart illustrating an implementation of a method for adjusting a timing sequence according to an embodiment of the present disclosure. The method for adjusting the timing sequence shown in fig. 1 comprises the following steps:

s11: a first target sequential element of a timing path whose timing is to be adjusted is determined.

In step S11, the timing path includes at least two hierarchical sequential elements. Here, the hierarchical structure refers to the hierarchical distribution between sequential elements, and sequential elements of different levels are determined according to the transmission sequence of data signals, for example, if a data signal is transmitted to a first sequential element first and then transmitted from the first sequential element to a second sequential element, the first sequential element is a previous sequential element of the second sequential element, and the second sequential element is a next sequential element of the first sequential element.

It should be noted that the first target sequential element is a sequential element in the timing path that has a timing violation, that is, a sequential element in which the clock signal does not match the data signal. Here, the sequential element may be any conventional electronic component that requires a clock signal and a data signal to act simultaneously, such as a register, a memory, and the like. In the time sequence path, certain data delay and clock delay exist between the time sequence elements of adjacent levels, and a first target time sequence element of the time sequence to be adjusted can be determined from the time sequence path by analyzing whether the data signal transmission time and the clock signal delay time between the time sequence elements of the adjacent levels are matched or not.

In practical applications, the information in the timing database of the timing path is used to describe the timing of each level of the sequential elements receiving the data signal and the clock signal, so that the data signal transmission time and the clock signal delay time between the sequential elements of adjacent levels can be obtained by querying the timing database of the timing path.

In other embodiments, the first target sequential element of which the timing sequence is to be adjusted in the timing sequence path is determined, and the first target sequential element of which the timing sequence violation exists may be determined from the timing sequence traversal of all the sequential elements in the timing sequence path.

As an embodiment of the present application, step S11 includes:

inputting a clock signal and a data signal to the timing path; acquiring a data signal establishing time and a data signal holding time which are determined by each intermediate time sequence element based on the clock signal and the data signal in the time sequence path; the intermediate sequential elements are the other sequential elements except the first-stage sequential element in the sequential path; determining the first target sequential element from the sequential path based on the data signal setup time and the data signal hold time corresponding to each of the intermediate sequential elements.

It should be noted that, since the timing path includes at least two hierarchical timing elements, after the clock signal and the data signal are input to the timing path, the data signal transmitted by the previous timing element received by the intermediate timing element must be matched with the clock signal received by the intermediate timing element, and when the clock signal received by the intermediate timing element is not matched with the data signal transmitted by the previous timing element, it is determined that the intermediate timing element fails to operate normally due to a timing violation, and thus the intermediate timing element is identified as the first target timing element.

In this embodiment, whether the clock signal received by the intermediate timing element matches the data signal transmitted by the previous timing element may be determined by obtaining a data signal setup time and a data signal hold time that are determined by the intermediate timing element based on the clock signal and the data signal, and determining whether the intermediate timing element is the first target timing element based on the data signal setup time and the data signal hold time that correspond to the intermediate timing element. The intermediate sequential element needs to work normally under the combined action of a clock signal and a data signal which are matched with each other, specifically, the intermediate sequential element starts to sample the data signal after detecting that a sampling clock edge of the clock signal arrives, and in order to ensure that the intermediate sequential element can smoothly sample the data signal, the intermediate sequential element needs to receive the data signal in a first time period before the sampling clock edge of the clock signal arrives and keep the data signal stable continuously in a second time period after the sampling clock edge of the clock signal arrives, wherein the first time period is a data signal establishment time, and the second time period is a data signal holding time. By analyzing the data signal setup time and the data signal hold time corresponding to each intermediate sequential element in the sequential path, it can be determined which intermediate sequential element receives a clock signal that is not matched with the data signal, i.e., the first target sequential element is determined from the sequential path.

As an embodiment of the present application, in the foregoing solution, the step of determining the first target sequential element from the sequential path based on the data signal setup time and the data signal hold time corresponding to each intermediate sequential element includes:

judging whether the data signal establishing time and the data signal holding time corresponding to each intermediate sequential element meet the following constraint conditions:

T_Cn-1+T_Qn-1+T_L+T_Setup≤T_Cn+T_P；

T_Cn-1+T_Qn-1+T_L-T_Hold≥T_Cn；

wherein, T_Cn-1A delay time for a preceding sequential element of the intermediate sequential elements to receive the clock signal; t is_Qn-1An internal transition time of a preceding sequential element of the intermediate sequential element; t is_LDelaying a transmission path between the intermediate sequential element and a sequential element of a previous stage thereof by a time; t is_SetupEstablishing time for the data signal corresponding to the intermediate sequential element; t is_CnA delay time for the intermediate sequential element to receive the clock signal; t is_PA period of the clock signal; t is_HoldFor the intermediate time sequenceThe data signal holding time corresponding to an element; identifying an intermediate sequential element that does not satisfy the constraint as the first target sequential element.

In this embodiment, the constraint condition is used to describe a condition that the clock signal and the data signal received by the intermediate sequential element are matched with each other, that is, a value range of a data signal setup time and a data signal hold time under a normal operating condition of the intermediate sequential element.

It should be noted that, after determining the connection path between sequential elements in a sequential path, the internal transition time in each sequential element and the transmission path delay time between adjacent sequential elements can be determined. After the clock signal and the data signal are input into the time sequence path, the time sequence element in the time sequence path works according to the clock signal and the data signal under the condition of not considering whether the time sequence is disordered or not, so that the delay time of the time sequence element at the upper stage of the middle time sequence element in the constraint condition for receiving the clock signal, the data signal establishment time corresponding to the middle time sequence element, the delay time of the middle time sequence element for receiving the clock signal, the period of the clock signal and the data signal holding time corresponding to the middle time sequence element can be determined, and whether the data signal establishment time and the data signal holding time of the middle time sequence element meet the limit or the value range of the constraint condition or not can be judged. Here, in determining the first target sequential element from the sequential paths, the timing relationship between two adjacent sequential elements, that is, the time relationship between the intermediate sequential element and the sequential element of the previous stage thereof is considered. The intermediate time sequence element and the previous time sequence element respectively receive clock signals with the same period, and the data signal received by the intermediate time sequence element is output by the previous time sequence element, so that whether the clock signal received by the intermediate time sequence element is matched with the data signal or not can be judged by analyzing the time sequence relation between the intermediate time sequence element and the previous time sequence element.

Fig. 2 shows a schematic diagram of a timing path. As shown in FIG. 2, in the timing path composed of the first register FF1 and the second register FF2, the data is stored in the first register FF1Signals are input from the data terminal D1 of the first register FF1, so that the first register FF1 is a sequential element at the previous stage of the second register FF2, and the second register FF2 is a sequential element at the next stage of the first register FF 1. In the timing path shown in FIG. 2, the period is T_periodRespectively, through a clock terminal C1 of the first register FF1 and a clock terminal C2 of the second register FF2, wherein the delay time of the clock signal transmitted to the clock terminal C1 of the first register FF1 is T₁The delay time of the clock signal transmitted to the clock terminal C2 of the second register FF2 is T₂。

In fig. 2, after being transferred to the first register FF1, the data signal and the clock signal are output from the transition terminal Q1 of the first register FF1, and then transferred to the data terminal D2 of the second register FF2 via the intermediate data path between the first register FF1 and the second register FF 2. For the second register FF2, determining whether the timing violation occurs in the timing of the second register FF2, i.e., determining whether the second register FF2 is the first target sequential element, can be determined based on the data signal setup time and the data signal hold time of the second register FF 2. Here, the data terminal D2 of the second register FF2 receives the data signal at the delay time T of the first register FF1 receiving the clock signal ₁A transition time T of a transition end Q1 of a first register FF1_Q1(i.e., internal transition time of first register FF 1) and transmission path delay time T_LSum, i.e. T₁+T_Q1+T_L。

FIG. 3 is a timing diagram illustrating the timing of a clock signal and a data signal received by a sequential element. With reference to fig. 2 and 3, since the sequential element first register FF1 is a sequential element at the first level in the sequential path, i.e. a sequential element that receives the clock signal and the data signal first, the first register FF1 does not have the timing violation problem caused by the path delay of the clock signal or the data signal during transmission. Therefore, the sequential elements of the first level in the timing path are not considered when the first target timing path is obtained from the timing path. FIG. 3 is a timing diagram of a sequential element receiving a clock signal and a data signalIn practical application, the sampling clock edge can be set as a falling edge according to practical requirements. Referring to fig. 2 and 3, when the sampling clock edge (rising edge) of the clock signal arrives, the first register FF1 collects the data signal having a whole clock signal period T and transfers the data signal to the second register FF2 _periodIs passed to the data terminal D2 of the second register FF 2. For the second register FF2, the data signal received by the data terminal D2 of the second register FF2 must remain unchanged for a first period of time, referred to as the data signal setup time T, before the clock signal sampling clock edge (rising edge) arrives_setupAfter the clock terminal C2 of the second register FF2 detects the arrival of the sampling clock edge (rising edge) of the clock signal, the data signal received by the data terminal D2 of the second register FF2 must be kept unchanged for a second period of time, which is called the data signal holding time T_hold. In determining whether the second register FF2 is the first target sequential element, this may be determined by determining whether the clock signal and the data signal received by the second register FF2 satisfy the duration of the data signal setup time and the duration of the data save time.

With reference to fig. 2 and 3, since the first register FF1 collects the data signal and transfers the data signal to the second register FF2, the collected data signal has a whole clock signal period T_periodIs transmitted to the data terminal D2 of the second register FF2, and the data signal received by the data terminal D2 of the second register FF2 must remain unchanged for the first period of time, i.e., the data signal setup time T needs to be satisfied _setupTherefore, for the second register FF2, the data signal must arrive earlier than the clock signal, i.e., the data signal setup time for the second register FF2 is constrained by the formula T₁+T_Q1+T_L+T_setup≤T₂+T_periodBy transforming this formula, T can be obtained_setup≤T₂+T_period-T₁-T_Q1-T_L. To prevent the number collected by the first register FF1When the data signal is transferred to the second register FF2 too fast, and the data signal collected by the second register FF2 is modified, the data signal collected by the first register FF1 must be allowed to be transferred to the second register FF2 after a certain period of time, that is, each time the data signal is transferred to the second register FF2, it needs to be considered whether the data signal has a certain hold time last time, that is, the data signal hold time of the second register FF2 is constrained by the formula T₁+T_Q1+T_L–T_hold≥T₂By transforming this formula, T can be obtained_hold≤T₁+T_Q1+T_L-T₂. Therefore, whether the data signal establishing time and the data signal holding time corresponding to each middle sequential element of the sequential path meet the constraint condition is judged: t is_Cn-1+T_Qn-1+T_L+T_Setup≤T_Cn+T_PAnd T_Cn-1+T_Qn-1+T_L-T_Hold≥T_CnThe first target sequential element may be determined from the timing path.

S12: a target clock skew value between the first target sequential element and a second target sequential element is evaluated.

In step S12, the second target sequential element is a previous sequential element to the first target sequential element. A target clock skew value between the first target sequential element and the second target sequential element to characterize a maximum modulatable clock skew between the first target sequential element and the second target sequential element. Here, since the clock offset value is used to describe the time difference between the clock signal transmitted to two or more sequential elements in the sequential path, the mismatch between the clock signal and the data signal of the sequential element can be adjusted by controlling the clock skew value between the adjacent sequential elements.

In this embodiment, since the second target sequential element is a previous sequential element of the first target sequential element, the timing of receiving the clock signal by the second target sequential element and the first target sequential element can be adjusted by constructing a clock skew value between the two sequential elements, thereby implementing the timing adjustment of the timing path.

Taking the timing path shown in FIG. 2 as an example, the period is T_periodRespectively, through a clock terminal C1 of the first register FF1 and a clock terminal C2 of the second register FF2, wherein the delay time of the clock signal transmitted to the clock terminal C1 of the first register FF1 is T ₁The delay time of the clock signal transmitted to the clock terminal C2 of the second register FF2 is T₂. Here, since the time difference between the arrival of the clock signal at two or more registers before and after the arrival is the clock skew, the delay time T of the clock signal transferred to the clock terminal C1 of the first register FF1₁And a delay time T of the clock signal to the clock terminal C2 of the second register FF2₂The difference between them is the clock skew value between the first register FF1 and the second register FF 2. When the clock signal is transmitted to the clock terminal C1 of the first register FF1 and the clock terminal C2 of the second register FF2 at the same time, there is no clock signal delay between the first register FF1 and the second register FF2, i.e. the delay time T₁And a delay time T₂The difference between them is 0; when the clock signal is not simultaneously transmitted to the clock terminal C1 of the first register FF1 and the clock terminal C2 of the second register FF2, a clock signal delay, i.e., a delay time T, exists between the first register FF1 and the second register FF2₁And a delay time T₂The difference between them is not 0. By measuring and calculating a target clock skew value between a first target sequential element and a second target sequential element, the size of an extreme value of a time difference between a clock signal transmitted to the second target sequential element and the first target sequential element in sequence can be determined, namely the configurable maximum clock skew value between the first target sequential element and the second target sequential element is determined.

As an embodiment of the present application, step S12 includes:

if the first target sequential element is an intermediate sequential element of which the data signal establishing time does not meet the constraint condition, acquiring a first data signal holding time T corresponding to the first target sequential element_{Hold_1}And maintaining a time T based on the first data signal_{Hold_1}Measurement and calculationThe target clock skew value;

if the first target sequential element is an intermediate sequential element of which the data signal retention time does not meet the constraint condition, acquiring a first data signal establishment time T corresponding to the first target sequential element_{Setup_1}And establishing a time T based on said first data signal_{Setup_1}And measuring and calculating the target clock skew value.

In this embodiment, if the first target sequential element is an intermediate sequential element in the sequential path whose data signal setup time does not satisfy the constraint condition, the data signal setup time may be adjusted by determining the data signal hold time margin corresponding to the first target sequential element and using the data signal hold time margin.

As shown in FIG. 3, in practical applications, when the sequential elements in the timing path receive the clock signal and the data signal, and the data signal setup time T is satisfied_setupAnd data signal hold time T_holdIn this case, there is usually a certain data signal setup time margin T at the same time_{setup_slack}With data signal holding time margin T_{hold_slack}。

Fig. 4 shows a schematic diagram of a comparison between a clock signal and a plurality of data signals, and with reference to fig. 3 and 4, when the clock signal and the data signal are paired, the timing of the timing path is relatively limited, that is, as can be seen in the waveform diagram of the data signal, the data signal setup time margin and the data signal hold time margin are compressed, and when the data signal setup time margin T is compressed to the margin limit, the data signal setup time margin T is compressed_{setup_slack}With data signal holding time margin T_{hold_slack}All are 0, as shown in fig. 4, the sampling clock edge displayed by the clock signal is a rising edge, and only the data signal establishing time T is left in the waveform diagram of the data signal_setupAnd data signal hold time T_hold. When the clock signal and the DATA signal DATA1 are paired, the DATA signal DATA1 cannot keep stable for a period of time before the sampling clock edge (rising edge) of the clock signal arrives, so that the DATA signal setup time is insufficient, but after the sampling clock edge (rising edge) of the clock signal arrives, the DATA signal DATA1 can keep stable for a period of time, that is, the DATA holding time requirement is met, and a remaining holding time margin remains. When the clock signal and the DATA signal DATA2 are paired, the DATA signal DATA2 cannot keep stable for a period of time after the clock signal sampling clock edge (rising edge) arrives, so that the DATA signal holding time is insufficient, but before the clock signal sampling clock edge (rising edge) arrives, the DATA signal DATA1 can keep stable for a period of time, that is, the DATA setup time requirement is met, and a setup time margin remains. It is possible to make a mutual compensation adjustment using the margin between the two times by determining whether the first target sequential element needs to be adjusted for the data signal setup time portion or the data signal hold time portion.

As an embodiment of the present application, in the above scheme, the holding time T is based on the first data signal_{Hold_1}Evaluating the target clock skew value, comprising:

measuring and calculating a first value interval of the target clock skew value through the following formula:

T_FF1-T_FF2≤T_FFQ2+T_LD-T_{Hold_1}and (T)_FFQ2+T_LD-T_{Hold_1})>0；

Wherein, T_FF1A clock signal delay time for the first target sequential element; t is_FF2A clock signal delay time for the second target sequential element; t is_FF1-T_FF2The first value interval is obtained; t is_FFQ2An internal transition time for the second target sequential element; t is_LDDelaying a transmission path delay time between the first target sequential element and the second target sequential element; t is_{Hold_1}Is the first target sequential elementA corresponding first data signal hold time;

determining the target clock skew value from the first span based on a clock skew margin between the second target sequential element and a third target sequential element, and/or a clock skew margin between the second target sequential element and a fourth target sequential element; the third target sequential element is a previous-stage sequential element of the second target sequential element, and the fourth target sequential element is a next-stage sequential element of the first target sequential element.

It should be noted that, in the constraint: t is_Cn-1+T_Qn-1+T_L-T_Hold≥T_CnThe value range used for describing the data signal holding time under the normal working condition of the intermediate sequential element is transformed, and the following relation can be obtained:

T_Cn-T_Cn-1≤T_Qn-1+T_L-T_Hold； (1)

it can be seen that, when the right side calculation formula value of the relation formula (1) is greater than 0, it indicates that the clock signal and the data signal can satisfy the data signal holding time T_holdCondition of (1), data signal retention time T_holdConvergence is achieved without using clock skew, so that the data signal establishes a time T_setupThe clock skew value corresponding to the left-side equation value of the relation (1) can be used for adjustment.

It is understood that, in the above relation (1), T_Cn-T_Cn-1For clock skew, i.e. with T_FF1-T_FF2Correspondingly, the first value interval is taken as a first value interval, and in practical application, the relation (1) and the formula T are taken into consideration_FF1-T_FF2≤T_FFQ2+T_LD-T_{Hold_1}And (4) mutually equal.

In this embodiment, the first value interval of the target clock skew value is calculated by the following formula:

T_FF1-T_FF2≤T_FFQ2+T_LD-T_{Hold_1}and (T)_FFQ2+T_LD-T_{Hold_1})>0, the number can be determinedAnd according to the holding time, determining a target clock skew value from the first value range based on the clock skew allowance between the second target sequential element and the third target sequential element and/or the clock skew allowance between the second target sequential element and the fourth target sequential element, and ensuring that the proper target clock skew value is selected to finish timing adjustment under the condition of not influencing the timing of the first target sequential element and the respective adjacent sequential elements of the second target sequential element.

As an embodiment of the present application, in the foregoing solutions, the time T is established based on the first data signal_{Setup_1}Evaluating the target clock skew value, comprising:

and measuring and calculating a second value interval of the target clock skew value by the following formula:

T_FF2-T_FF1≤T_P-T_FFQ2-T_LD-T_{Setup_1}and (T)_P-T_FFQ2-T_LD-T_{Setup_1})>0；

Wherein, T_FF1A clock signal delay time for the first target sequential element; t is_FF2A clock signal delay time for the second target sequential element; t is_FF2-T_FF1Is the second value interval; t is_PA period of the clock signal; t is_FFQ2An internal transition time for the second target sequential element; t is_LDDelaying a transmission path delay time between the first target sequential element and the second target sequential element; t is_{Setup_1}Establishing time for a first data signal corresponding to the first target sequential element;

determining the target clock skew value from the second span based on a clock skew margin between the second target sequential element and a third target sequential element, and/or a clock skew margin between the second target sequential element and a fourth target sequential element; the third target sequential element is a previous-stage sequential element of the second target sequential element, and the fourth target sequential element is a next-stage sequential element of the first target sequential element.

It should be noted that, in the constraint: t is_Cn-1+T_Qn-1+T_L+T_Setup≤T_Cn+T_PThe value range is used for describing the data signal establishing time under the normal working condition of the middle sequential element, and the following relational expression can be obtained by converting the value range:

T_Cn-1-T_Cn≤T_P-T_Qn-1-T_L-T_Setup； (2)

therefore, when the right side of the relation (2) is greater than 0, it means that the clock signal and the data signal can satisfy the data signal establishing time T_setupCondition of (1), data signal settling time T_setupConvergence is achieved without using clock skew, so that the data signal holds time T_holdThe clock skew value corresponding to the left-side equation value of the relation (2) can be used for adjustment.

It is understood that, in the above relation (2), T_Cn-1-T_CnFor clock skew, i.e. with T_FF2-T_FF1Correspondingly, the first value interval is taken as a first value interval, and in practical application, the relation (2) and the formula T are taken into consideration_FF2-T_FF1≤T_P-T_FFQ2-T_LD-T_{Setup_1}And (4) mutually equal.

In this embodiment, the first value section of the target clock skew value is calculated by the following formula:

T_FF2-T_FF1≤T_P-T_FFQ2-T_LD-T_{Setup_1}and (T)_P-T_FFQ2-T_LD-T_{Setup_1})>And 0, determining the size of data establishing time, and then determining a target clock skew value from a second value taking interval based on the clock skew allowance between the second target sequential element and the third target sequential element and/or the clock skew allowance between the second target sequential element and the fourth target sequential element, so as to ensure that the proper target clock skew value is selected to complete timing adjustment under the condition of not influencing the timing of the first target sequential element on the respective adjacent sequential elements of the second target sequential element.

S13: and configuring the target clock skew value into a preset clock tree comprehensive file to obtain the target clock tree comprehensive file.

In step S13, a Clock Tree constraint file is included in the Clock Tree Synthesis file (CTS), and the Clock Tree constraint file is used to define the Clock signal. The clock tree constraint file includes at least: the start of the clock, the clock period, the delay unit type or name, and the respective sequential element clock skew target value. In addition, the clock tree constraint file may also contain maximum/minimum clock network delays, maximum fan-out of clock units, maximum jump time of global devices, maximum value of global clock skew, and the like.

It should be noted that the clock tree synthesis requires the definition of the parameters to be implemented, which are provided by the clock tree constraint file, and the clock tree constraint file is the definition of the clock signal itself, which is directly derived from the standard design constraint SDC file. For a multi-clock complex SoC design, constraints such as a multi-cycle check path, a redundant pseudo path, a maximum delay time, a minimum delay time, and the like need to be set according to specific design conditions.

In this embodiment, the target clock skew value is configured into a preset clock tree integration file, which may be specifically configured into a clock constraint file of the clock tree integration file.

It is understood that, in practical applications, the file includes at least: the starting point, clock period, delay unit type or name of the clock, and clock skew target value of each sequential element, and configuring the target clock skew value into a preset clock tree integrated file, specifically, the target clock skew value may be used as the clock skew target value of the first target sequential element, and the clock skew corresponding to the first target sequential element is modified correspondingly.

S14: and executing the target clock tree comprehensive file, and performing timing adjustment operation on the first target timing element.

In step S14, since the target clock tree integration file is configured with the target clock skew value, when the target clock tree integration file is executed, the target clock skew value can constrain the clock skew between the first target sequential element and the second target sequential element, so as to repair the data signal setup time or the data signal hold time of the first target sequential element, that is, to adjust the timing of the timing path.

In this embodiment, the executing the target clock tree integration file may be executed by a timing adjustment tool installed in advance on the computer terminal, that is, the target clock tree integration file is executed by calling the timing adjustment tool, so as to perform a timing adjustment operation on the first target sequential element.

As an embodiment of the present application, step S14 specifically includes:

acquiring the number of the first target sequential elements;

configuring a respective set of buffer nodes based on the number of the first target sequential elements;

allocating a buffer node in the set of buffer nodes between the first target sequential element and the second target sequential element to complete a timing adjustment operation; the buffer node is to describe the target clock skew value.

In this embodiment, a target clock tree synthesis file is executed, a target clock skew value corresponding to each first target sequential element in a sequential path is recursively queried, the number of the first target sequential elements is obtained, a corresponding buffer node set is configured based on the number of the first target sequential elements, and a buffer optimal insertion node corresponding to the generated target clock skew value is determined, that is, between the first target sequential element and the second target sequential element, and the timing adjustment operation is completed by configuring a buffer node for describing the target clock skew value between the first target sequential element and the second target sequential element.

In practical applications, any intermediate sequential element in the sequential path may simultaneously correspond to one or more next-stage sequential elements, and when a same second target sequential element corresponds to a plurality of first target sequential elements in the same hierarchy, a common node may be configured between the plurality of first target sequential elements, and the common node is used as a buffer node, thereby implementing the target clock skew corresponding to the target clock skew value between the second target sequential element and the plurality of first target sequential elements, and completing the operation of adjusting the timing.

As can be seen from the above, in the method for adjusting a timing sequence provided in this embodiment, by obtaining a first target timing sequence element of a timing sequence path, and then measuring and calculating a target clock skew value between the first target timing sequence element and a previous stage timing sequence element thereof, that is, between the first target timing sequence element and a second target timing sequence element, since the first target timing sequence element is a timing sequence element of a timing sequence path to be adjusted, and the measured and calculated target clock skew value, a timing violation of the first target timing sequence element can be directly repaired, so that the target clock skew value is configured into a preset clock tree integrated file to obtain a target clock tree integrated file, and by executing the target clock tree integrated file, the timing sequence adjustment operation can be performed on the first target timing sequence element, without performing multiple iterative adjustments on a timing sequence circuit, thereby reducing the time cost for performing the timing sequence adjustment on the timing sequence path, the efficiency of carrying out the chronogenesis adjustment to the chronogenesis circuit has been improved.

In addition, by executing the target clock tree synthesis file, recursively inquiring a target clock skew value corresponding to each first target sequential element in the sequential path, acquiring the number of the first target sequential elements, configuring a corresponding buffer node set based on the number of the first target sequential elements, and determining and generating a buffer optimal insertion node corresponding to the target clock skew value, unnecessary buffer insertion is reduced.

Referring to fig. 5, fig. 5 is a flowchart illustrating an implementation of a method for adjusting a timing sequence according to another embodiment of the present application. With respect to the embodiment shown in fig. 1, the method for adjusting timing provided in this embodiment further includes step S21 after step S11 and before step S12. The details are as follows:

s21: identifying a previous stage sequential element of the first target sequential element as a second target sequential element.

In this embodiment, the second target sequential element is a previous sequential element of the first target sequential element.

In the timing path, since the first target timing element is determined as an intermediate timing element in the middle timing path and the intermediate timing element is a timing element other than the first-stage timing element in the timing path, the second target timing element may be a first-stage timing element in the timing path or any intermediate timing element in the timing path.

In practical applications, when the sequential elements in the sequential path are determined to be the previous sequential elements of the first target sequential element, the sequential element can be identified as the previous sequential element of the first target sequential element, that is, the second target sequential element, by determining the data signal input end of the first target sequential element, that is, to which sequential element in the sequential path the data signal input end of the first target sequential element is connected.

It should be understood that step S21 is performed after step S11 and before step S12, and steps S12 to S14 are performed after step S21 is performed.

Referring to fig. 6, fig. 6 is a block diagram illustrating a timing adjustment apparatus according to an embodiment of the present disclosure. The timing adjusting apparatus in this embodiment includes units for executing the steps in the embodiments corresponding to fig. 1 and 5. Please refer to fig. 1 and 5 and the related descriptions of the embodiments corresponding to fig. 1 and 5. For convenience of explanation, only the portions related to the present embodiment are shown. Referring to fig. 6, the apparatus 30 for adjusting timing includes: a determination unit 31, a calculation unit 32, a configuration unit 33 and an execution unit 34.

Wherein:

a determining unit 31, configured to acquire a first target sequential element to be adjusted in a timing path; the timing path comprises at least two hierarchical timing elements;

a measurement unit 32 for measuring a target clock skew value between the first target sequential element and a second target sequential element; wherein the second target sequential element is a previous stage sequential element of the first target sequential element;

the configuration unit 33 is configured to configure the target clock skew value into a preset clock tree comprehensive file to obtain a target clock tree comprehensive file;

An executing unit 34, configured to execute the target clock tree integration file to perform a timing adjustment operation on the first target sequential element.

As an embodiment of the present application, the apparatus 30 for adjusting timing further includes: an identification unit 35.

An identifying unit 35 configured to identify a sequential element previous to the first target sequential element as a second target sequential element.

It should be understood that, in the structural block diagram of the apparatus for adjusting timing shown in fig. 6, each unit is used to execute each step in the embodiment corresponding to fig. 1 and 5, and each step in the embodiment corresponding to fig. 1 and 5 has been explained in detail in the above embodiment, and specific reference is made to the description in the embodiment corresponding to fig. 1 and 5 and fig. 1 and 5, which is not repeated herein.

Fig. 7 is a block diagram of a computer device according to another embodiment of the present application. As shown in fig. 7, the computer device 4 of this embodiment includes: a processor 40, a memory 41 and a computer program 42 stored in said memory 41 and executable on said processor 40, such as a program of a method of adjusting a timing. The processor 40 executes the computer program 42 to implement the steps of the above-mentioned timing adjusting methods, such as S11-S14 shown in fig. 1. Alternatively, when the processor 40 executes the computer program 42, the functions of the units in the embodiment corresponding to fig. 6, for example, the functions of the units 31 to 35 shown in fig. 6, are implemented, for which reference is specifically made to the relevant description in the embodiment corresponding to fig. 6, and details are not repeated here.

Illustratively, the computer program 42 may be divided into one or more units, which are stored in the memory 41 and executed by the processor 40 to accomplish the present application. The one or more units may be a series of computer program instruction segments capable of performing certain functions, which are used to describe the execution of the computer program 42 in the computer device 4. For example, the computer program 42 may be divided into a first acquisition unit, a calculation unit, a configuration unit, an execution unit, and an identification unit, each unit functioning specifically as described above.

The computer device may include, but is not limited to, a processor 40, a memory 41. Those skilled in the art will appreciate that fig. 7 is merely an example of a computer device 4 and is not intended to limit computer device 4 and may include more or fewer components than those shown, or some of the components may be combined, or different components, e.g., the computer device may also include input output devices, network access devices, buses, etc.

The Processor 40 may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic, discrete hardware components, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

The memory 41 may be an internal storage unit of the computer device 4, such as a hard disk or a memory of the computer device 4. The memory 41 may also be an external storage device of the computer device 4, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like, which are provided on the computer device 4. Further, the memory 41 may also include both an internal storage unit and an external storage device of the computer device 4. The memory 41 is used for storing the computer program and other programs and data required by the computer device. The memory 41 may also be used to temporarily store data that has been output or is to be output.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.