阅读说明：本技术 灵敏放大器、存储器和灵敏放大器的控制方法 (Sense amplifier, memory and control method of sense amplifier ) 是由 彭春雨 王子健 卢文娟 吴秀龙 何军 李新 应战 曹堪宇 蔺智挺 陈军宁 于 2020-07-27 设计创作，主要内容包括：本公开提供了一种灵敏放大器、存储器和灵敏放大器的控制方法,涉及半导体存储器技术领域。该灵敏放大器包括：放大模块,被配置为当灵敏放大器处于放大阶段时,对位线或参考位线传输的电压进行放大；第一开关模块,被配置为当灵敏放大器针对位线进行读操作且灵敏放大器处于放大阶段时,控制放大模块与参考位线断开。本公开可以减小灵敏放大器的功耗。(The disclosure provides a sense amplifier, a memory and a control method of the sense amplifier, and relates to the technical field of semiconductor memories. The sense amplifier includes: the amplifying module is configured to amplify the voltage transmitted by the bit line or the reference bit line when the sense amplifier is in an amplifying stage; the first switch module is configured to control the amplifying module to be disconnected from the reference bit line when the sense amplifier performs a read operation on the bit line and the sense amplifier is in an amplifying stage. The present disclosure may reduce power consumption of a sense amplifier.)

1. A sense amplifier, comprising:

the amplifying module is configured to amplify the voltage transmitted by the bit line or the reference bit line when the sense amplifier is in an amplifying stage;

a first switch module configured to control the amplifying module to disconnect from the reference bit line when the sense amplifier performs a read operation with respect to the bit line and the sense amplifier is in an amplifying stage.

2. The sense amplifier of claim 1, wherein the first switch module is configured to control the amplifying module to disconnect from the reference bit line based on a data source control signal when the sense amplifier is in an amplifying phase.

3. The sense amplifier of claim 2, wherein the first switching module comprises:

a first switch unit, a first control end of which is used for receiving the data source control signal, a first end of which is connected with the amplifying module through a first node, and a second end of which is connected with the reference bit line.

4. The sense amplifier of claim 3, wherein the first switching module controls the amplifying module to be disconnected from the reference bit line based on the data source control signal, and comprises:

the first switching module is configured to control the amplifying module to be disconnected from the reference bit line in response to the data source control signal and a first control signal;

the first switch unit further comprises a second control end for receiving the first control signal.

5. The sense amplifier of claim 1, further comprising:

a second switch module configured to control the amplifying module to disconnect from the bit line when the sense amplifier performs a read operation with respect to the reference bit line and the sense amplifier is in an amplifying stage.

6. The sense amplifier of claim 5, wherein the second switching module comprises:

the input end of the inverter is used for receiving a data source control signal;

and a first control end of the second switch unit is connected with the output end of the phase inverter, a first end of the second switch unit is connected with the amplifying module through a second node, and a second end of the second switch unit is connected with the bit line.

7. The sense amplifier of claim 6, wherein the second switching unit further comprises:

and the second control end is used for receiving the first control signal.

8. The sense amplifier according to any of claims 1 to 7, further comprising:

a discharge control module configured to discharge the sense amplifier after the sense amplifier performs a read 1 operation with respect to the bit line.

9. The sense amplifier of claim 8, wherein the amplifying module comprises:

the drain electrode of the first PMOS tube is connected with a first node;

the drain electrode of the first NMOS tube is connected with the first node, and the grid electrode of the first NMOS tube is connected with the grid electrode of the first PMOS tube;

the drain electrode of the second PMOS tube is connected with a second node;

the drain electrode of the second NMOS tube is connected with the second node, and the grid electrode of the second NMOS tube is connected with the grid electrode of the second PMOS tube;

a drain electrode of the third PMOS transistor is connected with a source electrode of the first PMOS transistor and a source electrode of the second PMOS transistor, a gate electrode of the third PMOS transistor is used for receiving a second control signal, and a source electrode of the third PMOS transistor is used for receiving a power supply voltage;

a drain electrode of the third NMOS tube is connected with a source electrode of the first NMOS tube and a source electrode of the second NMOS tube, a grid electrode of the third NMOS tube is used for receiving a first control signal, and the source electrode of the third NMOS tube is grounded;

the grid electrode of the first PMOS tube is connected with the second node, and the grid electrode of the second PMOS tube is connected with the first node.

10. The sense amplifier of claim 9, wherein the discharge control module comprises:

a first discharge unit configured to connect a gate of the first NMOS transistor with the first node in response to a discharge control signal;

a second discharge unit configured to connect a gate of the second NMOS transistor with the second node in response to a discharge control signal.

11. The sense amplifier of claim 3, wherein the first switching unit comprises:

a gate of the fourth NMOS transistor is configured to receive the data source control signal, a source of the fourth NMOS transistor is connected to the reference bit line, and a drain of the fourth NMOS transistor is connected to the first node.

12. The sense amplifier of claim 4, wherein the first switching unit comprises:

a gate of the fourth NMOS transistor is configured to receive the data source control signal, a source of the fourth NMOS transistor is connected to the reference bit line, and a drain of the fourth NMOS transistor is connected to the first node;

a gate of the fourth PMOS transistor is configured to receive the first control signal, a drain of the fourth PMOS transistor is connected to the reference bit line, and a source of the fourth PMOS transistor is connected to the first node.

13. The sense amplifier of claim 6, wherein the second switching unit comprises:

a gate of the fifth NMOS transistor is connected with the output end of the phase inverter, a drain of the fifth NMOS transistor is connected with the bit line, and a source of the fifth NMOS transistor is connected with the second node.

14. The sense amplifier of claim 7, wherein the second switching unit comprises:

a gate of the fifth NMOS transistor is connected with the output end of the phase inverter, a drain of the fifth NMOS transistor is connected with the bit line, and a source of the fifth NMOS transistor is connected with the second node;

a gate of the fifth PMOS transistor is configured to receive the first control signal, a source of the fifth PMOS transistor is connected to the bit line, and a drain of the fifth PMOS transistor is connected to the second node.

15. The sense amplifier of claim 1, further comprising:

a precharge module configured to precharge the bit line and the reference bit line when the sense amplifier is in a precharge phase.

16. A memory comprising a sense amplifier as claimed in any one of claims 1 to 15.

17. A method of controlling a sense amplifier, comprising:

and when the sense amplifier carries out reading operation on a bit line and is in an amplifying stage, controlling the amplifying module to be disconnected from a reference bit line.

Technical Field

The disclosure relates to the technical field of semiconductor memories, in particular to a sense amplifier, a memory and a control method of the sense amplifier.

Background

With the popularization of electronic devices such as mobile phones, tablet computers, and personal computers, semiconductor memory technology has also been rapidly developed. Memories such as Dynamic Random Access Memories (DRAMs) and Static Random Access Memories (SRAMs) have been widely used in various electronic devices due to their advantages of high density, low power consumption, low price, and the like.

A Sense Amplifier (SA) is an important component of a semiconductor memory, and is mainly used for amplifying a small signal on a bit line to perform a read or write operation.

The power consumption is used as an important index for evaluating the performance of the sensitive amplifier, and directly influences the application scene of the memory. At present, how to reduce the power consumption of a sense amplifier becomes an urgent problem to be solved.

It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

An object of the present disclosure is to provide a sense amplifier, a memory, and a control method of the sense amplifier, thereby overcoming, at least to some extent, the problem of the high power consumption of the sense amplifier due to the limitations and disadvantages of the related art.

According to a first aspect of the present disclosure, there is provided a sense amplifier comprising: the amplifying module is configured to amplify the voltage transmitted by the bit line or the reference bit line when the sense amplifier is in an amplifying stage; the first switch module is configured to control the amplifying module to be disconnected from the reference bit line when the sense amplifier performs a read operation on the bit line and the sense amplifier is in an amplifying stage.

Optionally, the first switch module is configured to control the amplifying module to be disconnected from the reference bit line based on the data source control signal when the sense amplifier is in the amplifying stage.

Optionally, the first switch module comprises: the first control end of the first switch unit is used for receiving a data source control signal, the first end of the first switch unit is connected with the amplifying module through a first node, and the second end of the first switch unit is connected with the reference bit line.

Optionally, the first switch module controls the amplifying module to disconnect from the reference bit line based on the data source control signal, and includes: the first switch module is configured to control the amplifying module to be disconnected from the reference bit line in response to the data source control signal and the first control signal; the first switch unit further comprises a second control end for receiving the first control signal.

Optionally, the sense amplifier further comprises: and the second switch module is configured to control the amplifying module to be disconnected from the bit line when the sense amplifier performs a read operation on the reference bit line and the sense amplifier is in an amplifying stage.

Optionally, the second switch module comprises: the input end of the inverter is used for receiving a data source control signal; and a first control end of the second switch unit is connected with the output end of the phase inverter, a first end of the second switch unit is connected with the amplifying module through a second node, and a second end of the second switch unit is connected with the bit line.

Optionally, the second switching unit further comprises: and the second control end is used for receiving the first control signal.

Optionally, the sense amplifier further comprises: and the discharge control module is configured to discharge the sense amplifier after the sense amplifier performs a read 1 operation on the bit line.

Optionally, the amplifying module comprises: the drain electrode of the first PMOS tube is connected with the first node; the drain electrode of the first NMOS tube is connected with the first node, and the grid electrode of the first NMOS tube is connected with the grid electrode of the first PMOS tube; the drain electrode of the second PMOS tube is connected with the second node; the drain electrode of the second NMOS tube is connected with the second node, and the grid electrode of the second NMOS tube is connected with the grid electrode of the second PMOS tube; a drain electrode of the third PMOS tube is connected with a source electrode of the first PMOS tube and a source electrode of the second PMOS tube, a grid electrode of the third PMOS tube is used for receiving a second control signal, and a source electrode of the third PMOS tube is used for receiving power supply voltage; the drain electrode of the third NMOS tube is connected with the source electrode of the first NMOS tube and the source electrode of the second NMOS tube, the grid electrode of the third NMOS tube is used for receiving the first control signal, and the source electrode of the third NMOS tube is grounded; the grid electrode of the first PMOS tube is connected with the second node, and the grid electrode of the second PMOS tube is connected with the first node.

Optionally, the discharge control module comprises: a first discharge unit configured to connect a gate of the first NMOS transistor with a first node in response to a discharge control signal; and the second discharge unit is configured to respond to the discharge control signal and connect the grid electrode of the second NMOS tube with the second node.

Optionally, the first switching unit comprises: and the grid electrode of the fourth NMOS tube is used for receiving the data source control signal, the source electrode of the fourth NMOS tube is connected with the reference bit line, and the drain electrode of the fourth NMOS tube is connected with the first node.

Optionally, the first switching unit comprises: a gate of the fourth NMOS transistor is used for receiving a data source control signal, a source of the fourth NMOS transistor is connected with the reference bit line, and a drain of the fourth NMOS transistor is connected with the first node; and the grid electrode of the fourth PMOS tube is used for receiving the first control signal, the drain electrode of the fourth PMOS tube is connected with the reference bit line, and the source electrode of the fourth PMOS tube is connected with the first node.

Optionally, the second switching unit comprises: and the grid electrode of the fifth NMOS tube is connected with the output end of the phase inverter, the drain electrode of the fifth NMOS tube is connected with the bit line, and the source electrode of the fifth NMOS tube is connected with the second node.

Optionally, the second switching unit comprises: a grid electrode of the fifth NMOS tube is connected with the output end of the phase inverter, a drain electrode of the fifth NMOS tube is connected with the bit line, and a source electrode of the fifth NMOS tube is connected with the second node; and the grid electrode of the fifth PMOS tube is used for receiving the first control signal, the source electrode of the fifth PMOS tube is connected with the bit line, and the drain electrode of the fifth PMOS tube is connected with the second node.

Optionally, the sense amplifier further comprises: a precharge module configured to precharge the bit line and the reference bit line when the sense amplifier is in a precharge phase.

According to a second aspect of the present disclosure, there is provided a memory including a sense amplifier as in any one of the above.

According to a third aspect of the present disclosure, there is provided a control method of a sense amplifier, including: when the sense amplifier carries out reading operation aiming at the bit line and the sense amplifier is in an amplifying stage, the amplifying module is controlled to be disconnected with the reference bit line.

In an aspect provided by some embodiments of the present disclosure, the first switch module is configured to control the amplifying module to be disconnected from the reference bit line when the sense amplifier performs a read operation with respect to the bit line and the sense amplifier is in an amplifying stage. Therefore, when the read operation is performed on the bit line, the power consumption of the sensitive amplifier is greatly reduced. In addition, the signal processing speed of the circuit is improved because the voltage on the reference bit line is not amplified when the bit line is read.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty. In the drawings:

FIG. 1 schematically illustrates a schematic diagram of a sense amplifier according to one embodiment of the present disclosure;

FIG. 2 schematically illustrates a block diagram of a sense amplifier according to an exemplary embodiment of the present disclosure;

FIG. 3 schematically illustrates a block diagram of a sense amplifier according to another exemplary embodiment of the present disclosure;

FIG. 4 schematically illustrates a block diagram of a sense amplifier according to yet another exemplary embodiment of the present disclosure;

FIG. 5 schematically illustrates a circuit diagram of a sense amplifier according to an exemplary embodiment of the present disclosure;

fig. 6 schematically illustrates an operation timing diagram of a sense amplifier according to an exemplary embodiment of the present disclosure.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and the like. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.

Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repetitive description will be omitted. The descriptions of "first," "second," "third," "fourth," and "fifth" are for purposes of distinction only and are not intended to be limiting of the present disclosure.

It is noted that the term "coupled," as used herein, may include both direct and indirect connections. In the direct connection, there is no component between the terminals, for example, the first terminal of the switch a is connected to the first terminal of the switch B, and there may be only a connection line (e.g., a metal line) on the connection line between the first terminal of the switch a and the first terminal of the switch B, and there is no other component. In indirect connection, there may be other components between the terminals, for example, the first terminal of the switch C is connected to the first terminal of the switch D, and there may be at least one other component (e.g., the switch E, etc.) on the connection line between the first terminal of the switch C and the first terminal of the switch D in addition to the connection line.

FIG. 1 schematically shows a schematic diagram of a sense amplifier according to one embodiment of the present disclosure.

Referring to fig. 1, in reading data in a memory cell on a bit line, first, the bit line BL and the reference bit line BL _ B may be precharged such that they are precharged to VDD/2. Next, the address is decoded and the corresponding word line WL is turned on, for example, the lowest bit a0 of the row address is an even address and the high address is an odd address. It can be specified that even addresses after address decoding are turned on for memory cells connected to the bit line BL and odd addresses are turned on for memory cells connected to the reference bit line BL _ B. Subsequently, the storage voltage is charge-shared with the bit line, and the bit line BL and the reference bit line BL _ B generate a voltage difference. Then, in the amplifying stage, no matter reading 0 or 1, the power supply VDD will do work, and the voltage of one side bit line is pulled up to VDD, and the voltage of the other side bit line is pulled down to zero by GND. It should be noted that, determining the even address or the odd address is not limited to be identified by the lowest bit a0 of the row address, may be identified by other bits in the row address, or may be identified by a result obtained by processing at least one bit of the row address with a specific relationship.

When reading is performed on the bit line BL, since the reference bit line BL _ B does not perform a write-back operation on the memory cell, the voltage of the reference bit line BL _ B may not be amplified, that is, the amplified potential of the reference bit line BL _ B does not affect the reading of data. Therefore, the connection of the sense amplifier and the reference bit line BL _ B can be cut off in the amplification stage to reduce power consumption when the bit line BL performs a read operation.

In view of this, the present disclosure also provides a new sense amplifier.

FIG. 2 schematically illustrates a block diagram of a sense amplifier according to an exemplary embodiment of the present disclosure. Referring to fig. 2, the sense amplifier 2 may include an amplifying block 20 and a first switching block 21.

The amplification module 20 may be configured to: when the sense amplifier is in the amplifying stage, the voltage transmitted by the bit line or the reference bit line is amplified.

The first switching module 21 may be configured to: when the sense amplifier performs a read operation for the bit line and the sense amplifier is in the amplifying phase, the amplifying module 20 is controlled to be disconnected from the reference bit line.

The reading operation on the bit line includes a0 reading operation on the bit line and a 1 reading operation on the bit line.

By controlling the amplifying module to be disconnected from the reference bit line when the sense amplifier performs a reading operation on the bit line and the sense amplifier is in an amplifying stage, the power consumption of the sense amplifier can be effectively reduced, and the processing speed of the circuit is increased.

Specifically, when the sense amplifier 2 is in the amplifying stage, the first switch module 21 may control the amplifying module 20 to be disconnected from the reference bit line based on the data source control signal.

The data source control signal is used to indicate whether the data of the memory cell on the bit line or the reference bit line is read, and usually the least significant bit a0 of the column address is used as the data source control signal, for example, the least significant bit a0 of the column address is an even address, corresponding to the memory cell on the open bit line; the lowest bit A0 of the row address is high for an odd address, which corresponds to the memory cell on the open reference bit line. However, it should be noted that the data source control signal described in the present disclosure may also be any signal capable of identifying whether the bit line is read or the memory cell data on the reference bit line is read, and the present disclosure is not limited thereto.

The first switching module 21 may include a first switching unit.

The first control terminal of the first switch unit is configured to receive a data source control signal, the first terminal of the first switch unit is connected to the amplifying module 20 through a first node, and the second terminal of the first switch unit is connected to the reference bit line.

In another embodiment of the present disclosure, the first switch unit further includes a second control terminal for receiving the first control signal. In this case, the first switching module 21 is configured to control the amplifying module 20 to be disconnected from the reference bit line in response to the data source control signal and the first control signal.

Referring to fig. 3, the sense amplifier 3 may further include a second switching module 31 in addition to the amplification module 20 and the first switching module 21 described above. The second switching module 31 may be configured to: when the sense amplifier 3 performs a read operation with respect to the reference bit line and the sense amplifier 3 is in an amplifying stage, the amplifying module 20 is controlled to be disconnected from the bit line.

That is, the connection state of the amplifying block 20 to the bit line may be controlled by the second switching block 31, similar to the first switching block 21.

The first switch module is configured to control the amplifying module to be disconnected from the bit line when the sense amplifier performs a read operation with respect to the reference bit line and the sense amplifier is in an amplifying stage. Thus, the power consumption of the sense amplifier will be greatly reduced when a read operation is performed for the reference bit line. In addition, the signal processing speed of the circuit is improved because the voltage on the bit line is not amplified when the reference bit line is read.

In addition, the second switch module 31 may also be used to write back the read signal to the memory cell after the sense amplifier performs a read operation for the bit line.

The second switching module 31 may include an inverter and a second switching unit.

The input end of the inverter is used for receiving a data source control signal. A first control terminal of the second switch unit is connected to an output terminal of the inverter, a first terminal of the second switch unit is connected to the amplifying module 20 through a second node, and a second terminal of the second switch unit is connected to the bit line.

In another embodiment, the second switching unit further comprises a second control terminal for receiving the first control signal.

In the above exemplary sense amplifier scheme, for the case of bit line read 1, after the read 1 operation, the voltage of the reference bit line is VDD/2 and the voltage of the bit line is VDD. In this case, the sense amplifier may be affected when it is next precharged, and the sense amplifier may not be precharged to VDD/2.

To solve this problem, referring to fig. 4, the sense amplifier 4 may further include a discharge control module 41 in addition to the amplification module 20, the first switching module 21, and the second switching module 31 described above. The discharge control module 41 is configured to discharge the sense amplifier 4 after the sense amplifier 4 performs a read 1 operation with respect to the bit line. Thus, after the next precharge, the voltages of the reference bit line and the bit line can both be VDD/2.

In an exemplary embodiment of the present disclosure, the amplifying module 20 may include a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, a second NMOS transistor, a third PMOS transistor, and a third NMOS transistor.

Specifically, the drain electrode of the first PMOS transistor is connected with the first node, and the gate electrode of the first PMOS transistor is connected with the second node; the drain electrode of the first NMOS tube is connected with the first node, and the grid electrode of the first NMOS tube is connected with the grid electrode of the first PMOS tube; the drain electrode of the second PMOS tube is connected with the second node, and the grid electrode of the second PMOS tube is connected with the first node; the drain electrode of the second NMOS tube is connected with the second node, and the grid electrode of the second NMOS tube is connected with the grid electrode of the second PMOS tube; the drain electrode of the third PMOS tube is connected with the source electrode of the first PMOS tube and the source electrode of the second PMOS tube, the grid electrode of the third PMOS tube is used for receiving a second control signal, and the source electrode of the third PMOS tube is used for receiving power supply voltage; the drain electrode of the third NMOS tube is connected with the source electrode of the first NMOS tube and the source electrode of the second NMOS tube, the grid electrode of the third NMOS tube is used for receiving the first control signal, and the source electrode of the third NMOS tube is grounded.

According to an embodiment of the present disclosure, the first switching unit may include a fourth NMOS transistor. The grid electrode of the fourth NMOS tube is used for receiving the data source control signal, the source electrode of the fourth NMOS tube is connected with the reference bit line, and the drain electrode of the fourth NMOS tube is connected with the first node.

According to another embodiment of the present disclosure, the first switching unit may further include a fourth PMOS transistor in addition to the fourth NMOS transistor. The grid electrode of the fourth PMOS tube is used for receiving the first control signal, the drain electrode of the fourth PMOS tube is connected with the reference bit line, and the source electrode of the fourth PMOS tube is connected with the first node.

According to an embodiment of the present disclosure, the second switching unit may include a fifth NMOS transistor. The grid electrode of the fifth NMOS tube is connected with the output end of the phase inverter, the drain electrode of the fifth NMOS tube is connected with the bit line, and the source electrode of the fifth NMOS tube is connected with the second node.

According to another embodiment of the present disclosure, the second switching unit may further include a fifth PMOS transistor in addition to the fifth NMOS transistor. The grid electrode of the fifth PMOS tube is used for receiving the first control signal, the source electrode of the fifth PMOS tube is connected with the bit line, and the drain electrode of the fifth PMOS tube is connected with the second node.

In addition, the discharge control module 41 may include a first discharge unit and a second discharge unit.

Specifically, the first discharge unit may be configured to connect a gate of the first NMOS transistor to the first node in response to a discharge control signal, so that the first NMOS transistor forms a diode connection manner. The second discharge unit may be configured to connect a gate of the second NMOS transistor with the second node in response to the discharge control signal, so that the second NMOS transistor forms a diode connection manner.

It should be noted that the sense amplifier of the above-mentioned various configurations may further include a precharge module. The precharge module is configured to precharge the bit line and the reference bit line when the sense amplifier is in a precharge phase.

Fig. 5 schematically illustrates a circuit diagram of a sense amplifier according to an exemplary embodiment of the present disclosure.

In the embodiment shown in FIG. 5, the bit line is denoted as BL, the reference bit line is denoted as BL _ B, the first node is denoted as Q1, and the second node is denoted as Q2.

The first PMOS tube is marked as P1, the first NMOS tube is marked as N1, the second PMOS tube is marked as P2, the second NMOS tube is marked as N2, the third PMOS tube is marked as P3, the third NMOS tube is marked as N3, the fourth PMOS tube is marked as P4, the fourth NMOS tube is marked as N4, the fifth PMOS tube is marked as P5, and the fifth NMOS tube is marked as N5. The first control signal is denoted as a signal SAN, and the second control signal is denoted as a signal SAP.

The first discharge unit is configured as an NMOS transistor N6, and the second discharge unit is configured as an NMOS transistor N7. The discharge control signal is denoted as a signal DCG.

Although not depicted in fig. 5, it is easily understood by those skilled in the art that the bit line BL and the reference bit line BL _ B are each connected with a memory cell, which may be composed of, for example, an NMOS transistor and a capacitor, and controls the on state of the transistor based on the word line WL signal to read or write data stored in the capacitor.

In addition, although the precharge module is not depicted in fig. 5, based on the circuit shown in fig. 1, it can be seen by those skilled in the art that the precharge module of the exemplary embodiment of the present disclosure may include 3 NMOS transistors, and whether the precharge operation is performed on the bit line BL and the reference bit line BL _ B is performed by the precharge control signal PE.

In the example shown in FIG. 5, the least significant bit A0 of the row address is used as the data source control signal.

It should be understood that the configuration of the components in the circuit shown in fig. 5 is merely an exemplary depiction, and all the components involved with the switching function may be configured as NMOS transistors, PMOS transistors or transmission gates, which is not limited by the present disclosure.

The operation of the sense amplifier of the exemplary embodiments of the present disclosure to read the bit line may include a precharge phase, a sensing phase, an amplification phase, and a discharge phase.

Fig. 6 schematically illustrates an operation timing diagram of a sense amplifier according to an exemplary embodiment of the present disclosure. The operation of the sense amplifier shown in fig. 5 will be described with reference to the timing diagram of fig. 6, taking the example of turning on the memory cell on the bit line BL when the least significant bit a0 of the row address is low.

In the precharge stage, the precharge control signal PE is at a high level, the precharge module starts to operate to precharge the bit line BL and the reference bit line BL _ B, so that the voltages on the bit line BL and the reference bit line BL _ B are precharged to VDD/2.

In addition, the first control signal SAN is low, the transistor P4 and the transistor P5 are turned on, and in this case, the first node Q1 and the second node Q2 are precharged to VDD/2.

In the sensing phase, the word line WL is high, the memory cell is turned on, and the voltage in the memory cell is transferred to the amplifying block for charge sharing with the first node Q1 and/or the second node Q2.

During the amplification phase, the transistor N4 is turned off, and since the first control signal SAN is high, the transistor P4 is also in an off state. Therefore, during the amplification stage, the sense amplifier is disconnected from the reference bit line BL _ B.

In addition, the first control signal SAN is at a high level, the second control signal SAP is at a low level, the transistor N3 and the transistor P3 are turned on, and the voltages of the first node Q1 and the second node Q2 are amplified. With the transistor N5 in the on state, the amplified voltage on the second node Q2 is written back to the memory cell on the bit line BL through the transistor N5.

In the discharging phase, the discharging control signal DCG is at a high level, the transistor N6 and the transistor N7 are turned on, the first control signal SAN and the second control signal SAP are at a high level, the transistor P3 is turned off, and the transistor N3 is turned on. Thus, the transistor N1 and the transistor N2 are diode-connected and discharge through the transistor N1 and the transistor N2 to ensure that the bit line BL and the reference bit line BL _ B are precharged to VDD/2 at the next precharge.

Although the above description has been given by taking the example of turning on the memory cell on the bit line BL when the lowest bit a0 of the row address is low, other ways included in the present disclosure may be suggested to those skilled in the art based on the exemplary scheme of the present disclosure.

It should be understood that, in the above description, the sense amplifier of the exemplary embodiment of the present disclosure is described by taking the example of controlling the amplifying module to be disconnected from the reference bit line when in the amplifying phase for the bit line read operation. However, as mentioned above, based on the sense amplifier of the exemplary embodiment of the present disclosure, the amplifying module may also be controlled to be disconnected from the bit line while in the amplifying phase for the reference bit line read operation. Therefore, the power consumption of the sensitive amplifier is greatly reduced, and the signal processing speed of the circuit is improved.

Further, the present disclosure also provides a control method of the sense amplifier. The method specifically comprises the following steps: when the sense amplifier carries out reading operation aiming at the bit line and the sense amplifier is in an amplifying stage, the amplifying module is controlled to be disconnected with the reference bit line.

In addition, the control method of the sense amplifier may further include: when the sense amplifier carries out reading operation aiming at the reference bit line and the sense amplifier is in an amplifying stage, the amplifying module is controlled to be disconnected with the bit line.

The method for controlling the sense amplifier according to the exemplary embodiment of the present disclosure is suitable for the above-described sense amplifier, and the implementation process of the method is described in the above description of the sense amplifier, and is not described herein again.

By the control method of the sensitive amplifier, the power consumption of the sensitive amplifier can be effectively reduced, and the circuit speed is improved.

Further, the present disclosure also provides a memory, which includes the above sense amplifier.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is to be limited only by the terms of the appended claims.