阅读说明：本技术 灵敏放大器、存储器和灵敏放大器的控制方法 (Sense amplifier, memory and control method of sense amplifier ) 是由 吴秀龙 赵丽 赵阳扩 何军 李新 应战 曹堪宇 卢文娟 彭春雨 蔺智挺 陈军宁 于 2020-07-27 设计创作，主要内容包括：本公开提供了一种灵敏放大器、存储器和灵敏放大器的控制方法,涉及半导体存储器技术领域。该灵敏放大器包括：放大模块；偏移电压存储单元,与放大模块电连接,用于在灵敏放大器的偏移消除阶段,存储放大模块的偏移电压；负载补偿单元,与放大模块电连接,用于在灵敏放大器的放大阶段,补偿所述放大模块的负载的差异。本公开可以提高灵敏放大器读取数据的准确性。(The disclosure provides a sense amplifier, a memory and a control method of the sense amplifier, and relates to the technical field of semiconductor memories. The sense amplifier includes: an amplifying module; the offset voltage storage unit is electrically connected with the amplifying module and used for storing the offset voltage of the amplifying module in the offset eliminating stage of the sensitive amplifier; and the load compensation unit is electrically connected with the amplification module and used for compensating the difference of the load of the amplification module in the amplification stage of the sensitive amplifier. The data reading accuracy of the sensitive amplifier can be improved.)

1. A sense amplifier, comprising:

an amplifying module;

the offset voltage storage unit is electrically connected with the amplifying module and used for storing the offset voltage of the amplifying module in the offset eliminating stage of the sensitive amplifier;

and the load compensation unit is electrically connected with the amplification module and used for compensating the difference of the load of the amplification module in the amplification stage of the sensitive amplifier.

2. The sense amplifier of claim 1, wherein the amplification module comprises:

a first PMOS tube;

a source electrode of the second PMOS tube is connected with a source electrode of the first PMOS tube;

the drain electrode of the first NMOS tube is connected with the drain electrode of the first PMOS tube and the first end of the offset voltage storage unit, and the grid electrode of the first NMOS tube is connected with the grid electrode of the first PMOS tube;

a drain electrode of the second NMOS tube is connected with a drain electrode of the second PMOS tube, a source electrode of the second NMOS tube is connected with a source electrode of the first NMOS tube, and a grid electrode of the second NMOS tube is connected with the second end of the offset voltage storage unit;

in an offset cancellation phase of the sense amplifier, the first PMOS tube and the second PMOS tube are configured as a current mirror, and the first NMOS tube and the second NMOS tube are both configured in a diode connection manner to store an offset voltage of the amplification module in the offset voltage storage unit.

3. The sense amplifier of claim 2, wherein the drain of the first PMOS transistor and the drain of the first NMOS transistor are connected to a first node, and the drain of the second PMOS transistor and the drain of the second NMOS transistor are connected to a second node; the sense amplifier further includes:

a first end of the first switch is connected with the first node, and a second end of the first switch is connected with a grid electrode of the first NMOS tube;

a first end of the second switch is connected with the second node, and a second end of the second switch is connected with a grid electrode of the second NMOS tube;

a first end of the third switch is connected with the grid electrode of the first PMOS tube, and a second end of the third switch is connected with the grid electrode of the second PMOS tube;

wherein, in an offset cancellation phase of the sense amplifier, the first switch, the second switch and the third switch are all in a closed state.

4. The sense amplifier of claim 3, further comprising:

the pull-up unit is used for responding to a pull-up control signal and controlling the connection state of the source electrode of the first PMOS tube and power supply voltage;

the pull-down unit is used for responding to a pull-down control signal and controlling whether the source electrode of the first NMOS tube is grounded;

in the offset elimination stage of the sense amplifier, the source electrode of the first PMOS tube is connected with the power supply voltage, and the source electrode of the first NMOS tube is grounded.

5. The sense amplifier of claim 4, further comprising:

a first end of the fourth switch is connected with the grid electrode of the first NMOS tube, and a second end of the fourth switch is connected with the second node;

a first end of the fifth switch is connected with the grid electrode of the second PMOS tube, and a second end of the fifth switch is connected with the grid electrode of the second NMOS tube;

wherein, during an offset cancellation phase of the sense amplifier, the fifth switch is turned off.

6. The sense amplifier of claim 5, further comprising:

a sixth switch, a first end of which is connected to a first bit line, and a second end of which is connected to the first node;

a seventh switch, a first end of which is connected to a second bit line, and a second end of which is connected to the second node;

wherein, during an offset cancellation phase of the sense amplifier, the sixth switch and the seventh switch are both turned off.

7. The sense amplifier of claim 6, wherein a first terminal of the load compensation unit is connected to the gate of the first NMOS transistor, and a second terminal of the load compensation unit is connected to a second node;

in an offset elimination phase of the sense amplifier, the fourth switch is turned off, and the load compensation unit stores an offset voltage of the amplification module.

8. The sense amplifier of claim 7, wherein the fourth switch is turned on after an offset cancellation phase of the sense amplifier to clear the offset voltage of the amplifying block stored by the load compensation unit.

9. The sense amplifier of claim 8, wherein during a sensing phase of the sense amplifier, a memory cell corresponding to the first bit line or a memory cell corresponding to the second bit line is turned on, the first switch, the second switch and the third switch are turned off, a source of the first PMOS transistor is disconnected from a power voltage, a source of the first NMOS transistor is disconnected from ground, the fourth switch is turned off, and the fifth switch, the sixth switch and the seventh switch are turned on, so as to input voltages of the first bit line and the second bit line to the sense amplifier.

10. The sense amplifier of claim 9, wherein during an amplification phase of the sense amplifier, the source of the first PMOS transistor is connected to the power supply voltage, and the source of the first NMOS transistor is grounded to amplify the voltages on the first bit line and the second bit line.

11. The sense amplifier of claim 10, further comprising:

a first end of the eighth switch is connected with the first node, and a second end of the eighth switch is connected with the grid electrode of the second NMOS tube;

wherein, in a first amplification process of an offset cancellation stage, a sensing stage and an amplification stage of the sense amplifier, the eighth switch is turned off; in a second amplification process of the amplification stage of the sense amplifier, the fourth switch and the eighth switch are closed.

12. The sense amplifier of claim 6, further comprising:

a precharge unit configured to precharge the first bit line and the second bit line when the sense amplifier is in a precharge phase.

13. The sense amplifier of claim 12, wherein the precharge phase and the offset cancellation phase are configured to be performed simultaneously.

14. A memory comprising a sense amplifier as claimed in any one of claims 1 to 13.

15. A control method of a sense amplifier is characterized in that the sense amplifier comprises an amplifying module, an offset voltage storage unit and a load compensation unit, and the control amplification of the sense amplifier comprises the following steps:

controlling the offset voltage of the amplifying module to be stored in the offset voltage storage unit during an offset cancellation phase of the sense amplifier;

and compensating the difference of the load of the amplifying module by the load compensation unit in the amplifying stage of the sensitive amplifier.

16. The method of claim 15, wherein the load compensation unit stores an offset voltage of the amplification block during an offset cancellation phase of the sense amplifier; wherein the control method of the sense amplifier further comprises:

after the offset elimination phase of the sensitive amplifier, eliminating the offset voltage of the amplifying module stored by the load compensation unit;

amplifying the voltages on the first bit line and the second bit line in a first amplification process of an amplification stage of the sense amplifier;

and controlling the short circuit of the offset voltage storage unit and the load compensation unit in a second amplification process of the amplification stage of the sensitive amplifier.

17. The method of controlling a sense amplifier according to claim 15, further comprising:

and in the amplifying stage of the sensitive amplifier, based on the offset voltage stored in the offset voltage storage unit, the voltages of the first bit line and the second bit line caused by the inconsistency of at least two transistors in the amplifying module are inhibited from being amplified wrongly.

18. The method of claim 17, wherein the operation phase of the sense amplifier further comprises a precharge phase; wherein the control method of the sense amplifier further comprises:

and in the precharge phase of the sensitive amplifier, precharging the first bit line and the second bit line.

19. The method of claim 18, further comprising:

controlling to perform a precharge operation of the precharge phase while the sense amplifier is in the offset cancel phase.

Technical Field

The disclosure relates to the technical field of semiconductor memories, in particular to a sense amplifier, a memory and a control method of the sense amplifier.

Background

With the popularization of electronic devices such as mobile phones, tablet computers, and personal computers, semiconductor memory technology has also been rapidly developed. Memories such as Dynamic Random Access Memories (DRAMs) and Static Random Access Memories (SRAMs) have been widely used in various electronic devices due to their advantages of high density, low power consumption, low price, and the like.

A Sense Amplifier (SA) is an important component of a semiconductor memory, and is mainly used for amplifying a small signal on a bit line to perform a read or write operation. As technology advances, the size of semiconductor memories is decreasing, and in this case, the performance of semiconductor memories is seriously affected by the larger and larger offset voltage caused by the mismatch of transistors in sense amplifiers.

In some offset compensation schemes, although the offset voltage is suppressed, a read data error problem may occur due to a defect of the circuit structure.

It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

An object of the present disclosure is to provide a sense amplifier, a memory, and a control method of the sense amplifier, thereby overcoming, at least to some extent, the problem of data read errors of the sense amplifier due to the limitations and disadvantages of the related art.

According to a first aspect of the present disclosure, there is provided a sense amplifier comprising: the amplifying module is used for reading data of the storage units on the first bit line or the second bit line; the offset voltage storage unit is electrically connected with the amplifying module and used for storing the offset voltage of the amplifying module in the offset eliminating stage of the sensitive amplifier; and the load compensation unit is electrically connected with the amplification module and used for compensating the difference of the load of the amplification module in the amplification stage of the sensitive amplifier.

Optionally, the difference in the load of the amplifying module is generated by the offset voltage storage unit causing a load inconsistency between the first bit line and the second bit line.

Optionally, the amplifying module comprises: a first PMOS tube; the source electrode of the second PMOS tube is connected with the source electrode of the first PMOS tube; the drain electrode of the first NMOS tube is connected with the drain electrode of the first PMOS tube and the first end of the offset voltage storage unit, and the grid electrode of the first NMOS tube is connected with the grid electrode of the first PMOS tube; the drain electrode of the second NMOS tube is connected with the drain electrode of the second PMOS tube, the source electrode of the second NMOS tube is connected with the source electrode of the first NMOS tube, and the grid electrode of the second NMOS tube is connected with the second end of the offset voltage storage unit; in an offset elimination stage of the sense amplifier, the first PMOS tube and the second PMOS tube are configured as current mirrors, and the first NMOS tube and the second NMOS tube are both configured in a diode connection mode so as to store an offset voltage of the amplifying module in the offset voltage storage unit.

Optionally, the drain of the first PMOS transistor and the drain of the first NMOS transistor are connected to a first node, and the drain of the second PMOS transistor and the drain of the second NMOS transistor are connected to a second node; the sense amplifier further includes: the first end of the first switch is connected with the first node, and the second end of the first switch is connected with the grid electrode of the first NMOS tube; a first end of the second switch is connected with the second node, and a second end of the second switch is connected with the grid electrode of the second NMOS tube; a first end of the third switch is connected with the grid electrode of the first PMOS tube, and a second end of the third switch is connected with the grid electrode of the second PMOS tube; in the offset elimination stage of the sense amplifier, the first switch, the second switch and the third switch are all in a closed state.

Optionally, the sense amplifier further comprises: the pull-up unit is used for responding to a pull-up control signal and controlling the connection state of the source electrode of the first PMOS tube and the power supply voltage; the pull-down unit is used for responding to a pull-down control signal and controlling whether the source electrode of the first NMOS tube is grounded; in the offset elimination stage of the sense amplifier, the source electrode of the first PMOS tube is connected with the power supply voltage, and the source electrode of the first NMOS tube is grounded.

Optionally, the sense amplifier further comprises: a first end of the fourth switch is connected with the grid electrode of the first NMOS tube, and a second end of the fourth switch is connected with the second node; a first end of the fifth switch is connected with the grid electrode of the second PMOS tube, and a second end of the fifth switch is connected with the grid electrode of the second NMOS tube; wherein, in the offset canceling phase of the sense amplifier, the fifth switch is turned off.

Optionally, the sense amplifier further comprises: a first end of the sixth switch is connected with the first bit line, and a second end of the sixth switch is connected with the first node; a first end of the seventh switch is connected with the second bit line, and a second end of the seventh switch is connected with the second node; wherein, in the offset elimination phase of the sensitive amplifier, the sixth switch and the seventh switch are both turned off.

Optionally, a first end of the load compensation unit is connected to the gate of the first NMOS transistor, and a second end of the load compensation unit is connected to the second node; in the offset elimination stage of the sense amplifier, the fourth switch is turned off, and the load compensation unit stores the offset voltage of the amplification module.

Optionally, after the offset cancellation phase of the sense amplifier, the fourth switch is closed to clear the offset voltage of the amplifying block stored by the load compensation unit.

Optionally, in a sensing stage of the sense amplifier, the memory cell corresponding to the first bit line or the memory cell corresponding to the second bit line is turned on, the first switch is turned off, the second switch and the third switch are turned off, the source of the first PMOS transistor is turned off from the power voltage, the source of the first NMOS transistor is turned off from the ground, the fourth switch is turned off, and the fifth switch, the sixth switch and the seventh switch are turned on, so that voltages of the first bit line and the second bit line are input to the sense amplifier.

Optionally, in an amplifying stage of the sense amplifier, a source of the first PMOS transistor is connected to a power voltage, and a source of the first NMOS transistor is grounded, so as to amplify voltages on the first bit line and the second bit line.

Optionally, the sense amplifier further comprises: a first end of the eighth switch is connected with the first node, and a second end of the eighth switch is connected with the grid electrode of the second NMOS tube; wherein, in the first amplification process of the offset elimination stage, the induction stage and the amplification stage of the sensitive amplifier, the eighth switch is switched off; during a second amplification process of the amplification stage of the sense amplifier, the fourth switch and the eighth switch are closed.

Optionally, the sense amplifier further comprises: and a precharge unit configured to precharge the first bit line and the second bit line when the sense amplifier is in a precharge stage.

Optionally, the pre-charge phase and the offset cancellation phase are configured to be performed simultaneously.

According to a second aspect of the present disclosure, there is provided a memory including a sense amplifier as in any one of the above.

According to a third aspect of the present disclosure, there is provided a control method of a sense amplifier, the sense amplifier including an amplification block, an offset voltage storage unit, and a load compensation unit, the controlling amplification of the sense amplifier including: in the offset elimination stage of the sensitive amplifier, the offset voltage of the control amplification module is stored in an offset voltage storage unit; in the amplifying stage of the sense amplifier, the difference of the load of the amplifying module is compensated by the load compensation unit.

Optionally, in an offset cancellation phase of the sense amplifier, the load compensation unit stores an offset voltage of the amplification module; the control method of the sensitive amplifier further comprises the following steps: after the offset elimination phase of the sensitive amplifier, eliminating the offset voltage of the amplifying module stored by the load compensation unit; amplifying the voltages on the first bit line and the second bit line in a first amplification process of an amplification stage of the sense amplifier; and in the second amplification process of the amplification stage of the sensitive amplifier, the offset voltage storage unit and the load compensation unit are controlled to be short-circuited.

Optionally, the control method of the sense amplifier further includes: in an amplification stage of the sense amplifier, based on an offset voltage stored in an offset voltage storage unit, voltages of the first bit line and the second bit line are suppressed from being erroneously amplified due to a mismatch of at least two transistors in the amplification block. The transistor in the amplifying module at least comprises a first NMOS transistor, a second NMOS transistor, a first PMOS transistor and a second PMOS transistor.

Optionally, the operation phase of the sense amplifier further comprises a precharge phase; the control method of the sensitive amplifier further comprises the following steps: the first bit line and the second bit line are precharged during a precharge phase of the sense amplifier.

Optionally, the control method of the sense amplifier further includes: when the sense amplifier is in the offset canceling phase, the precharge operation of the precharge phase is controlled to be performed.

In the technical solutions provided by some embodiments of the present disclosure, on one hand, by configuring an offset voltage storage unit, an offset voltage of an amplification module in a sense amplifier may be stored in the offset voltage storage unit during an offset cancellation stage of the sense amplifier. Therefore, when the bit line data needs to be read, the offset compensation of the sensitive amplifier can be realized by means of the offset voltage stored in the offset voltage storage unit, the influence of offset voltage on the read bit line data caused by the mismatch of the transistor is greatly reduced, and the performance of the semiconductor memory is further improved; on the other hand, by configuring the load compensation unit, it can be ensured that in the amplification stage of the sense amplifier, adverse effects on the load of the sense amplifier due to the introduction of the offset voltage storage unit are avoided, and the problem that read data errors may be caused due to inconsistent loads on the first bit line and the second bit line is avoided, so that the reading accuracy is improved, and the performance of the semiconductor memory is further improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty. In the drawings:

FIG. 1 schematically illustrates a circuit diagram of a sense amplifier according to one embodiment of the present disclosure;

FIG. 2 schematically illustrates a block diagram of a sense amplifier according to an exemplary embodiment of the present disclosure;

FIG. 3 schematically illustrates a circuit diagram of a sense amplifier according to an exemplary embodiment of the present disclosure;

FIG. 4 is a circuit diagram schematically illustrating a specific configuration of a sense amplifier according to an embodiment of the present disclosure;

FIG. 5 schematically illustrates a timing diagram of various control signals involved in a sense amplifier according to an embodiment of the disclosure;

FIG. 6 schematically illustrates a circuit diagram of a sense amplifier during an offset cancellation phase according to an embodiment of the disclosure;

FIG. 7 schematically illustrates a circuit diagram of a sense amplifier during a sensing phase according to an embodiment of the disclosure;

FIG. 8 schematically illustrates a circuit diagram of a sense amplifier during an amplification phase according to an embodiment of the disclosure;

FIG. 9 schematically illustrates a timing diagram of various control signals involved in a sense amplifier according to another embodiment of the present disclosure;

FIG. 10 schematically illustrates a circuit diagram of a sense amplifier in a balanced phase according to an embodiment of the disclosure;

fig. 11 schematically illustrates a flowchart of a control method of a sense amplifier according to an exemplary embodiment of the present disclosure.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and the like. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.

Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repetitive description will be omitted. The descriptions of "first," "second," "third," "fourth," "fifth," "sixth," "seventh," and "eighth" are for purposes of distinction only and should not be construed as limiting the present disclosure.

It is noted that the term "coupled," as used herein, may include both direct and indirect connections. In the direct connection, there is no component between the terminals, for example, the first terminal of the switch a is connected to the first terminal of the switch B, and there may be only a connection line (e.g., a metal line) on the connection line between the first terminal of the switch a and the first terminal of the switch B, and there is no other component. In indirect connection, there may be other components between the terminals, for example, the first terminal of the switch C is connected to the first terminal of the switch D, and there may be at least one other component (e.g., the switch E, etc.) on the connection line between the first terminal of the switch C and the first terminal of the switch D in addition to the connection line.

In addition, in the following description, it is easily understood by those skilled in the art that the terms "offset" and "offset" are the same meaning, and each mean a deviation due to a difference of transistors.

In the sense amplifier, due to the difference in the manufacturing process and the influence of the operating environment, there may be differences in the sizes, mobilities, threshold voltages, etc. of the transistors, and the performances of the transistors may not be completely the same, which may cause the sense amplifier to be out of order, which is equivalent to the occurrence of out-of-order noise, and seriously affects the correctness of the read data of the memory.

For example, a sense amplifier includes two symmetrically configured NMOS transistors, and ideally, the two NMOS transistors are expected to perform exactly the same. However, in practice, the threshold voltages of the two NMOS transistors may be different, which may cause a circuit mismatch. At this time, if no measure is taken, when data is read from the memory cell, it is possible to read "1" originally stored as "0" error output or read "0" originally stored as "1" error output.

In view of this, the present disclosure provides a sense amplifier.

FIG. 1 schematically shows a circuit diagram of a sense amplifier according to one embodiment of the present disclosure. Referring to fig. 1, by configuring an offset voltage storage unit in a sense amplifier, an offset voltage generated due to a mismatch between at least two components in the sense amplifier is stored in the offset voltage storage unit in an offset canceling stage of the sense amplifier. Therefore, when the bit line data is read, the offset compensation of the sensitive amplifier can be realized by means of the offset voltage stored in the offset voltage storage unit, the influence on the reading operation caused by the mismatch of the transistor is greatly reduced, the accuracy of reading the data is improved, and the performance of the semiconductor memory is optimized.

In some embodiments of the circuit of fig. 1, the offset voltage storage unit may be configured to include a capacitor. In this case, during the amplification stage of the sense amplifier, the capacitance on the bit line BLL includes its own parasitic capacitance and the capacitance of the offset voltage storage unit, and the capacitance on the bit line BLR includes only its own parasitic capacitance. The asymmetric amount of the bit line capacitance may cause the load on the bit lines BLL and BLR to be inconsistent, and thus the read data may be erroneous.

In view of this, the present disclosure also provides a new sense amplifier.

FIG. 2 schematically illustrates a block diagram of a sense amplifier according to an exemplary embodiment of the present disclosure. As shown in fig. 2, the sense amplifier 2 may include an amplification block 20, an offset voltage storage unit 21, and a load compensation unit 22.

The amplifying module 20 is used for reading data of the memory cells on the first bit line or the second bit line;

the offset voltage storage unit 21 is electrically connected to the amplifying block 20, and is used for storing the offset voltage of the amplifying block 20 during the offset cancellation phase of the sense amplifier 2.

The load compensation unit 22 is electrically connected to the amplification module 20, and is used for compensating for a difference in load of the amplification module 20 during an amplification stage of the sense amplifier.

It should be noted that the offset voltage of the amplification module 20 may refer to an offset voltage between components included in the amplification module 20. That is, the offset voltage of the amplification module 20 may represent a voltage difference generated by a mismatch between at least two components in the amplification module 20. The offset voltage refers to an offset voltage of the entire amplification module 20 in the case of integrating the voltage differences between all the components.

The amplifying module 20 may include a first PMOS transistor (hereinafter, referred to as a transistor P1), a second PMOS transistor (hereinafter, referred to as a transistor P2), a first NMOS transistor (hereinafter, referred to as a transistor N1), and a second NMOS transistor (hereinafter, referred to as a transistor N2).

In some embodiments of the present disclosure, the offset voltage storage unit 21 may be configured as one capacitor. However, both devices and cells with voltage storage function can be used as the offset voltage storage unit in the present disclosure, and the present disclosure does not limit the configuration form of the offset voltage storage unit.

In addition, the load compensation unit 22 may also be configured as a capacitor, and the capacitor may be the same as the capacitor in the offset voltage storage unit 21. In this case, by configuring the load compensation unit, the bit line capacitance load of the first bit line and the second bit line can be made symmetrical.

However, when the offset voltage storage unit 21 is configured in other forms except for the capacitance, the load compensation unit 22 may be configured in the same circuit form as the offset voltage storage unit 21.

It should be noted that in some embodiments of the present disclosure, the amplifying module 20 connects a first bit line and a second bit line, the first bit line corresponds to a load, and the second bit line corresponds to another load, where the difference between the loads of the amplifying module 20 refers to the difference between the loads of the first bit line and the second bit line. It will be appreciated that this difference is caused by the offset voltage storage unit 21, that is, because the offset voltage storage unit 21 is introduced into the sense amplifier 2, the load on both sides of the first bit line and the second bit line is not uniform.

However, in other embodiments of the present disclosure, the difference in the load of the amplifying module 20 may also be caused by other asymmetry factors in the circuit, for example, the two inverters included in the amplifying module 20 are not consistent due to the difference of the transistors, and the reason for the difference in the load of the amplifying module 20 is not limited by the present disclosure.

That is, even if the amplification block 20 is disconnected from the first and second bit lines in the amplification stage, the load compensation can be achieved using the circuit scheme of the present disclosure.

Fig. 3 schematically illustrates a circuit diagram of a sense amplifier according to an exemplary embodiment of the present disclosure.

Referring to fig. 3, the source of transistor P1 is connected to the source of transistor P2, the drain of transistor P1 is connected to the drain of transistor N1, and the gate of transistor P1 is connected to the gate of transistor N1. Here, for convenience of description later, a first node nL may be defined in the sense amplifier, and a drain of the transistor P1 and a drain of the transistor N1 are connected to the first node nL.

The drain of the transistor N2 is connected to the drain of the transistor P2, and the source of the transistor N2 is connected to the source of the transistor N1. Here, for convenience of description later, a second node nR may be defined in the sense amplifier, and a drain of the transistor N2 and a drain of the transistor P2 are connected to the second node nR.

A first terminal of the offset voltage storage unit is connected to the drain of the transistor N1, i.e., to the first node nL. The second terminal of the offset voltage storage unit is connected to the gate of transistor N2.

The operation phase of the sense amplifier of the exemplary embodiments of the present disclosure may be divided into: an offset cancellation phase, a sensing phase and an amplification phase.

In the offset canceling phase, the sense amplifier may store offset voltages of at least two transistors of the transistors N1, N2, P1, and P2, which are generated due to differences in sizes, mobilities, threshold voltages, and the like of the transistors, in an offset voltage storage unit. In the amplifying stage, the sense amplifier can suppress the influence of the performance disorder of the transistor on the data amplification according to the offset voltage stored in the offset voltage storage unit, so that the data on the bit line can be accurately read.

For the offset canceling phase of the sense amplifier, the transistor P1 and the transistor P2 may be configured as a current mirror, and the transistor N1 and the transistor N2 may be both configured in a diode connection manner to store the offset voltage of the amplifying block in the offset voltage storage unit.

It should be noted that the offset voltage of the amplification block refers to the offset voltage of at least two transistors (or components) in the amplification block. Specifically, the offset voltage may be the offset voltage of the transistor P1 and the transistor P2, the offset voltage of the transistor N1 and the transistor N2, or the offset voltage obtained by combining the two, which is not limited in the present disclosure.

Referring to fig. 2, the sense amplifier further includes a first switch (hereinafter, referred to as switch K1), a second switch (hereinafter, referred to as switch K2), and a third switch (hereinafter, referred to as switch K3) to implement the configuration of the transistors N1, N2, P1, and P2 during the offset cancellation phase of the sense amplifier.

A first terminal of the switch K1 is connected to the first node nL, and a second terminal of the switch K1 is connected to the gate of the transistor N1; a first terminal of the switch K2 is connected to the second node nR, and a second terminal of the switch K2 is connected to the gate of the transistor N2; a first terminal of the switch K3 is connected to the gate of the transistor P1, and a second terminal of the switch K3 is connected to the gate of the transistor P2.

In the offset cancellation phase of the sense amplifier, the switch K1, the switch K2, and the switch K3 are all in a closed state.

Among them, the present disclosure does not limit the types of the switch K1, the switch K2, and the switch K3. For example, the switch K1 may be a PMOS transistor, an NMOS transistor, or a CMOS transmission gate; the switch K2 can be a PMOS tube, an NMOS tube or a CMOS transmission gate; the switch K3 may be a PMOS transistor, an NMOS transistor, or a CMOS transmission gate.

In some embodiments of the present disclosure, the switch K1 may include a control terminal for controlling a switching state of the switch K1 in response to a first control signal; the switch K2 may also include a control terminal for controlling the switch state of the switch K2 in response to a second control signal; the switch K3 may also include a control terminal for controlling the switch state of the switch K3 in response to a second control signal. That is, the control terminals of the switches K2 and K3 can both receive the second control signal.

The sense amplifier of the exemplary embodiments of the present disclosure further includes a pull-up unit and a pull-down unit. The pull-up unit is used for connecting the source of the transistor P1 with the power supply voltage VDD in response to a pull-up control signal. The pull-down unit is used for grounding the source of the transistor N1 in response to a pull-down control signal.

In one embodiment of the present disclosure, the pull-up unit may include a pull-up PMOS transistor, and the pull-down unit may include a pull-down NMOS transistor. However, the pull-up unit may also be implemented by using an NMOS transistor, the pull-down unit may also be implemented by using a PMOS transistor, and the pull-up unit or the pull-down unit may include more than one device, and may also include a plurality of devices that are controlled to be turned on or off by different control signals, which is not limited in this disclosure.

With continued reference to fig. 3, the sense amplifier of the present disclosure may further include a fourth switch (hereinafter referred to as switch K4) and a fifth switch (hereinafter referred to as switch K5).

A first terminal of the switch K4 is connected to the gate of the transistor N1, and a second terminal of the switch K4 is connected to the second node nR; a first terminal of the switch K5 is connected to the gate of the transistor P2, and a second terminal of the switch K5 is connected to the gate of the transistor N2.

Similarly, the present disclosure does not limit the type of switch K4 and switch K5. For example, the switch K4 may be a PMOS transistor, an NMOS transistor, or a CMOS transmission gate; the switch K5 may be a PMOS transistor, an NMOS transistor, or a CMOS transmission gate.

In some embodiments of the present disclosure, the switch K4 may include a control terminal for controlling a switching state of the switch K4 in response to a third control signal; the switch K5 may also include a control terminal for controlling the switch state of the switch K5 in response to a fourth control signal.

During the offset cancellation phase of the sense amplifier, both switch K4 and switch K5 may be in an open state.

In addition, the sense amplifier of the present disclosure may further include a sixth switch (hereinafter, simply referred to as switch K6) and a seventh switch (hereinafter, simply referred to as switch K7).

A first terminal of the switch K6 is connected to a first bit line (denoted as BLL), and a second terminal of the switch K6 is connected to a first node nL; a first terminal of the switch K7 is connected to a second Bit Line (BLR), and a second terminal of the switch K7 is connected to the second node nR. It is easily understood by those skilled in the art that the first bit line BLL and the second bit line BLR each have a memory cell thereon.

Similarly, the present disclosure does not limit the type of switch K6 and switch K7. For example, the switch K6 may be a PMOS transistor, an NMOS transistor, or a CMOS transmission gate; the switch K7 may be a PMOS transistor, an NMOS transistor, or a CMOS transmission gate.

In some embodiments of the present disclosure, the switch K6 may include a control terminal for controlling a switching state of the switch K6 in response to a fifth control signal; the switch K7 may also include a control terminal for controlling the switch state of the switch K7 in response to a fifth control signal. That is, the control terminals of the switches K6 and K7 can both receive the fifth control signal.

During the offset cancellation phase of the sense amplifier, switch K6 and switch K7 are both in an open state.

In conjunction with the above-described exemplary circuit configuration, the offset voltage of the amplification block may be stored in the offset voltage storage unit during the offset cancellation phase of the sense amplifier.

With continued reference to fig. 3, a first terminal of the load compensation unit is connected to the gate of transistor N1 and a second terminal of the load compensation unit is connected to the second node nR.

In the offset compensation phase of the sense amplifier, and in the instance where the switch K4 is in the open state, the load compensation unit may also store the offset voltage of the amplification block. In this case, after the offset cancellation phase, the switch K4 may be closed to clear the offset voltage stored by the load compensation unit.

In a sensing stage after the offset canceling stage of the sense amplifier, a memory cell corresponding to the first bit line BLL or a memory cell corresponding to the second bit line BLR is turned on, the switch K1 is turned off, the switch K2 and the switch K3 are turned off, the source of the transistor P1 and the source of the transistor P2 are turned off from the power supply voltage, the source of the transistor N1 and the source of the transistor N2 are turned off from the ground, the switch K4 is turned off, the switch K5 is turned on, and the switch K6 and the switch K7 are turned on, so that the voltages of the first bit line BLL and the second bit line BLR are input to the sense amplifier, and since the offset voltages of the transistor N1 and the transistor N2 are stored in the offset voltage storage unit, a data readout error due to the inconsistency of the transistor N1 and the transistor N2 can be suppressed.

As will be understood by those skilled in the art, the memory cell being turned on means that the word line of the memory cell is activated, so that the data (0 or 1) stored in the memory cell is transferred to the bit line.

In a case where a voltage difference between the first and second bit lines BLL and BLR is input to the sense amplifier, a source of the transistor P1 is connected to a power voltage, and a source of the transistor N1 is grounded, so as to amplify voltages on the first and second bit lines BLL and BLR.

In the amplifying stage, due to the symmetrical structure of the offset voltage storage unit and the load compensation unit, the total amount of capacitance on the first bit line BLL is the same as the capacitance load on the second bit line BLR.

In addition, referring to fig. 3, in other embodiments of the present disclosure, the sense amplifier may further include an eighth switch (hereinafter, referred to as switch K8).

A first terminal of the switch K8 is connected to the first node nL, and a second terminal of the switch K8 is connected to the gate of the transistor N2.

In this case, the amplification stage of the sense amplifier may include a first amplification process and a second amplification process. Specifically, the switch K8 may be combined to switch the first amplification process and the second amplification process.

In the first amplification process of the offset elimination stage, the sensing stage and the amplification stage of the sensitive amplifier, the switch K8 is switched off; switch K4 and switch K8 may be closed after the second amplification process of the amplification stage of the sense amplifier, i.e., the difference in the voltages on first bit line BLL and second bit line BLR, is pulled apart.

With the switch K4 and the switch K8 closed, the offset voltage storage unit and the load compensation unit are both in a short circuit state to eliminate the influence of the offset voltage storage unit and the load compensation unit on the speed of the sense amplifier circuit.

In addition, still referring to fig. 3, the sense amplifier of the exemplary embodiment of the present disclosure further includes a precharge unit configured to precharge the first and second bit lines BLL and BLR when the sense amplifier is in a precharge stage.

It can be seen that, with the sense amplifier structure of the exemplary embodiment of the present disclosure, since both the switch K6 and the switch K7 are in the off state during the offset canceling phase, the operation of storing the offset voltages of the transistor N1 and the transistor N2 into the offset voltage storage unit is not affected while the first bit line BLL and the second bit line BLR are precharged. Thus, in an exemplary embodiment of the present disclosure, the pre-charge phase and the offset cancellation phase described above may be configured to be performed simultaneously.

FIG. 4 schematically illustrates a circuit diagram of a sense amplifier according to an embodiment of the present disclosure.

In the embodiment shown in fig. 4, the offset voltage storage unit is configured as a capacitor C0 and the load compensation unit is configured as a capacitor C4.

The switch K1 is configured as a transistor N3, controlling the switch state in response to a first control signal S1; the switch K2 is configured as a transistor N4, controlling the switch state in response to a second control signal S2; the switch K3 is configured as a transistor N5, controlling the switch state in response to a second control signal S2.

The pull-up unit is configured as a transistor P3, controlling the switch state in response to a pull-up control signal Sense _ P; the pull-down unit is configured as a transistor N6, controlling the switch state in response to a pull-down control signal Sense _ N.

The switch K4 is configured as a transistor N7, controlling the switch state in response to a third control signal S3; the switch K5 is configured as a transistor N8, controlling the switch state in response to a fourth control signal S4.

The switch K6 is configured as a transistor N9, controlling the switch state in response to a fifth control signal S5; the switch K7 is configured as a transistor N10, controlling the switch state in response to a fifth control signal S5.

The precharge unit may include a transistor N11, a transistor N12, and a transistor N13. The gates of transistor N11, transistor N12, and transistor N13 may each receive the precharge control signal BLP. The source of the transistor N11 is connected to the first bit line BLL, and the drain of the transistor N11 is connected to the second bit line BLR; a source of the transistor N12 is connected to the first bit line BLL, and a drain of the transistor N12 is connected to a precharge voltage VBLP, wherein the precharge voltage VBLP may be configured to VDD/2; the source of the transistor N13 is connected to the second bit line BLR, and the drain of the transistor N13 is connected to the precharge voltage VBLP.

A memory cell corresponding to the first bit line BLL is configured to include a transistor N14 and a capacitor C1, the transistor N14 controlling a switching state in response to a first word line control signal WL 1; the memory cell corresponding to the second bit line BLR is configured to include a transistor N15 and a capacitor C2, and the transistor N15 controls a switching state in response to a second word line control signal WL 2.

The switch K8 is configured as a transistor N16, controlling the switch state in response to a sixth control signal S6.

FIG. 5 schematically shows a timing diagram of various control signals according to an embodiment of the disclosure.

The operation phases of the sense amplifier of some embodiments of the present disclosure are described with reference to fig. 6, 7 and 8, respectively, in conjunction with the timing diagram of fig. 5.

FIG. 6 shows the offset cancellation phase of the sense amplifier with the first control signal S1 being high and the transistor N3 being turned on (corresponding to the closed state of the switch); the second control signal S2 is high, and the transistor N4 and the transistor N5 are turned on; the third control signal S3 is low, and the transistor N7 is turned off (corresponding to the off state of the switch); the fourth control signal S4 is low, and the transistor N8 is turned off; the fifth control signal S5 is low, and the transistor N9 and the transistor N10 are turned off; the sixth control signal S6 is low, and the transistor N16 is turned off.

The pull-up control signal Sense _ P is low level, and the transistor P3 is turned on; the pull-down control signal Sense _ N is high and the transistor N6 is turned on.

Thus, the transistor P1 and the transistor P2 are configured as a current mirror, and the transistor N1 and the transistor N2 are both configured in a diode connection manner. In this case, the offset voltage of the transistors N1 and N2 is stored in the capacitor C0, and the voltage on the side of the capacitor C0 close to the first bit line BLL is denoted as V_LAnd the voltage near the second bit line BLR is denoted as V_R。

It can be seen that the offset voltages of the transistors N1 and N2 are also stored on the capacitor C4.

In addition, in the offset canceling phase, the word lines WL1/WL2 are at low level, and the corresponding transistors are in an off state. That is, there is no data on the bit line to be read.

While the precharge control signal BLP is at a high level, that is, the precharge is performed, and both the first bit line BLL and the second bit line BLR are precharged to the precharge voltage VBLP.

FIG. 7 shows the sensing phase of the sense amplifier with the first control signal S1 being low and the transistor N3 being off; the second control signal S2 is low, and the transistor N4 and the transistor N5 are turned off; the third control signal S3 goes high first to turn on the transistor N7 and discharge the capacitor C4 to clear the stored offset voltage. Then, the third control signal S3 is low, and the transistor N7 is turned off; the fourth control signal S4 is high, and the transistor N8 is turned on; the fifth control signal S5 goes low and then goes high, and the transistor N9 and the transistor N10 are turned off and then turned on.

The pull-up control signal Sense _ P is high, and the transistor P3 is turned off; the pull-down control signal Sense _ N is low and the transistor N6 is turned off.

The precharge control signal BLP is at a low level, and the precharge is completed.

First, the word line WL is at a high level, the corresponding transistor is turned on, and data stored in the capacitor is transferred to the bit line. For example, the first word line control signal WL1 is at a high level, the transistor N14 is turned on, and the data stored in the capacitor C1 is transmitted to the first bit line BLL. A small voltage difference is formed between the first bit line BLL and the second bit line BLR due to the influence of data on the bit lines.

Next, the fifth control signal S5 goes high, and the transistors N9 and N10 are turned on, so that the smaller voltage difference is transmitted to the inside of the sense amplifier, and the voltage actually transmitted to the gate of the transistor N2 is VBLL + VR-VL due to the capacitor C0, where VBLL is the voltage on the first bit line. Thus, the voltage difference due to the inconsistency of the transistor N1 and the transistor N2 is suppressed from being erroneously amplified, and the error rate is reduced.

FIG. 8 is a timing diagram of FIG. 5 for the amplifying phase of the Sense amplifier, wherein the pull-up control signal Sense _ P is low and the transistor P3 is turned on compared to the sensing phase; the pull-down control signal Sense _ N is high and the transistor N6 is turned on.

In this case, the transistor P1, the transistor P2, the transistor N1, and the transistor N2 form two cross-coupled inverter positive feedback circuits, so that the voltage difference on the bit line can be quickly amplified and written back to the corresponding memory cell.

It should be noted that by configuring C4 to form a symmetrical structure with C0, the load difference on the first bit line BLL and the second bit line BLR is compensated, and the accuracy of reading data is further improved.

Considering the presence of C0 and C4 in the circuit, the circuit speed may be reduced. In other embodiments of the present disclosure, the amplification stage is divided to include a first amplification process and a second amplification process, and transistor N16 is configured to address this problem. Specifically, in the first amplification process of the offset cancellation stage, the sensing stage and the amplification stage of the sense amplifier, the transistor N16 is in an off state, and in the second amplification process of the amplification stage, the transistor N16 and the transistor N7 are controlled to be on, so that the capacitor C0 and the capacitor C4 are in a short-circuit state, and the circuit speed is further improved.

In addition, in other embodiments of the present disclosure, between the offset canceling phase and the sensing phase of the sense amplifier, there may be a balancing phase to make the voltage of the first node nL coincide with the voltage of the second node nR.

Fig. 9 shows a timing diagram of the control signals comprising the balancing phase.

Referring to fig. 10 in conjunction with the timing diagram of fig. 9, the balancing phase in further embodiments of the present disclosure is illustrated.

In contrast to the offset canceling phase, in the balancing phase of the sense amplifier, the second control signal S2 is at a low level, the transistor N4 is turned off and the transistor N5 is turned off; the third control signal S3 is high, and the transistor N7 is turned on; the fourth control signal S4 is high, and the transistor N8 is turned on.

The pull-up control signal Sense _ P is high, and the transistor P3 is turned off; the pull-down control signal Sense _ N is low and the transistor N6 is turned off.

Therefore, the voltage of the first node nL in the sensitive amplifier is consistent with the voltage of the second node nR, the purpose of charge balance is achieved, and the influence of the voltage difference formed in the offset elimination stage on data reading is eliminated.

In embodiments including a balancing phase, the pre-charge phase may be performed when the offset cancellation phase is performed, or the pre-charge phase may be performed when the balancing phase is performed.

Further, the present disclosure also provides a control method of the sense amplifier.

Fig. 11 schematically illustrates a flowchart of a control method of a sense amplifier according to an exemplary embodiment of the present disclosure. As described above, the sense amplifier may include an amplification block, an offset voltage storage unit, and a load compensation unit.

Referring to fig. 11, the control method of the sense amplifier may include the steps of:

s112, in the offset elimination stage of the sensitive amplifier, controlling the offset voltage of the amplification module to be stored in an offset voltage storage unit;

and S114, compensating the difference of the load of the amplifying module through a load compensation unit in the amplifying stage of the sensitive amplifier.

Through the control method of the sense amplifier of the exemplary embodiment of the present disclosure, on one hand, offset compensation of the sense amplifier can be realized by means of the offset voltage stored in the offset voltage storage unit, so that the influence of offset voltage on reading bit line data due to mismatch of transistors is greatly reduced, and further, the performance of the semiconductor memory is improved; on the other hand, by configuring the load compensation unit, it can be ensured that in the amplification stage of the sense amplifier, adverse effects on the load of the sense amplifier due to the introduction of the offset voltage storage unit are avoided, and the problem that read data errors may be caused due to inconsistent loads on the first bit line and the second bit line is avoided, so that the reading accuracy is improved, and the performance of the semiconductor memory is further improved.

According to an exemplary embodiment of the present disclosure, in an offset canceling stage of a sense amplifier, a load compensation unit stores an offset voltage of an amplification module; the control method of the sensitive amplifier further comprises the following steps: after the offset elimination phase of the sensitive amplifier, eliminating the offset voltage of the amplifying module stored by the load compensation unit; amplifying the voltages on the first bit line and the second bit line in a first amplification process of an amplification stage of the sense amplifier; and in the second amplification process of the amplification stage of the sensitive amplifier, the offset voltage storage unit and the load compensation unit are controlled to be short-circuited.

According to an exemplary embodiment of the present disclosure, an amplifying module includes a first NMOS transistor and a second NMOS transistor; the control method of the sensitive amplifier further comprises the following steps: in an amplification stage of the sense amplifier, based on an offset voltage stored in an offset voltage storage unit, voltages of the first bit line and the second bit line are suppressed from being erroneously amplified due to a mismatch of at least two transistors in the amplification block.

According to an exemplary embodiment of the present disclosure, the operation phase of the sense amplifier further includes a precharge phase; the control method of the sensitive amplifier further comprises the following steps: the first bit line and the second bit line are precharged during a precharge phase of the sense amplifier.

According to an exemplary embodiment of the present disclosure, the control method of the sense amplifier further includes: when the sense amplifier is in the offset canceling phase, the precharge operation of the precharge phase is controlled to be performed.

The detailed processes of the control method of the sense amplifier according to the exemplary embodiment of the present disclosure are described above in the process of describing the sense amplifier, and are not described herein again.

Further, the present disclosure also provides a memory, which includes the above sense amplifier.

By means of the sensitive amplifier of the disclosed exemplary embodiment, the reading error rate of the memory is reduced, the reading speed is improved, and the reading power consumption is reduced. Therefore, the performance of the memory is greatly improved.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is to be limited only by the terms of the appended claims.