Integrated circuit electromagnetic response calculation method and device based on multilevel parallel strategy

文档序号：988109 发布日期：2020-11-06 浏览：12次中文

阅读说明：本技术 基于多层次并行策略的集成电路电磁响应计算方法及装置 (Integrated circuit electromagnetic response calculation method and device based on multilevel parallel strategy ) 是由唐章宏邹军黄承清汲亚飞王芬于 2020-06-08 设计创作，主要内容包括：本申请实施例公开了基于多层次并行策略的集成电路电磁响应计算方法及装置。该方法通过将多层超大规模集成电路频域仿真中需要计算的每个频点的电磁响应特征的计算划分为多个计算子任务,采用多个并行子颗粒分别对各个计算子任务进行并行计算,并且,利用多个并行粗颗粒独立执行多个频点对应的多个计算任务,完成所述多个频点的多进程并行计算。本申请可以提高多层超大规模集成电路频域仿真对频点的电磁响应特征计算中各部分的计算效率,还可以提高对数量较大的不同频点的集成电路的电磁响应特征的并行计算效率,满足高效的计算需求。(The embodiment of the application discloses an integrated circuit electromagnetic response calculation method and device based on a multilevel parallel strategy. The method divides the calculation of the electromagnetic response characteristic of each frequency point required to be calculated in the frequency domain simulation of the multilayer very large scale integrated circuit into a plurality of calculation sub-tasks, adopts a plurality of parallel sub-particles to respectively perform parallel calculation on each calculation sub-task, and utilizes a plurality of parallel coarse particles to independently execute a plurality of calculation tasks corresponding to a plurality of frequency points to complete the multi-process parallel calculation of the plurality of frequency points. The method and the device can improve the calculation efficiency of each part in the calculation of the electromagnetic response characteristics of frequency points by the frequency domain simulation of the multilayer super-large-scale integrated circuit, can also improve the parallel calculation efficiency of the electromagnetic response characteristics of the integrated circuits with different frequency points with large number, and meet the requirement of efficient calculation.)

1. The integrated circuit electromagnetic response calculation method based on the multilevel parallel strategy is characterized by comprising the following steps:

setting a plurality of frequency points which need to be calculated in a preset frequency band range by using multilayer very large scale integrated circuit frequency domain simulation;

taking a multilayer VLSI electromagnetic response characteristic overall calculation process for executing each frequency point as a calculation task, and dividing a calculation program of the overall calculation process into a plurality of non-overlapping calculation particles, wherein the calculation particles are calculation programs for executing all independent calculations of the same type, and one independent calculation executed by the calculation particles is taken as a calculation subtask;

acquiring weighted CPU time required by each calculation particle to execute the corresponding calculation sub-task and total CPU time required by the electromagnetic response characteristic calculation process of each frequency point of the whole integrated circuit, and determining parallel sub-particles according to the proportion of the sum of the weighted CPU time in the total CPU time;

performing alignment and simplification processing of the polygons of the multilayer very large scale integrated circuit layout by using the first parallel sub-particles;

after the polygons of the multilayer VLSI layout are aligned and simplified, identifying and collecting the triangle and polygon sides contained in each parallel flat field of the multilayer VLSI layout by using a parallel flat field identification method through second parallel sub-particles, and performing adaptive mesh subdivision processing on the triangles in each parallel flat field according to the calculation precision requirement and the common areas of different parallel flat fields;

after the self-adaptive mesh subdivision processing is carried out on the triangles in each parallel flat plate field, the third parallel sub-particles are utilized to carry out field-path coupling on the parallel flat plate fields of the multilayer ultra-large scale integrated circuit layout and the external circuit of the integrated circuit;

and independently executing a plurality of computing tasks corresponding to a plurality of frequency points by using a plurality of parallel coarse particles to finish the multi-process parallel computing of the plurality of frequency points.

2. The method of claim 1, wherein performing the alignment and simplification process of the multi-level VLSI layout polygon using the first parallel sub-grain comprises:

vertically projecting a plurality of polygons which comprise a plurality of vertexes at each layer in a multilayer ultra-large scale integrated circuit layout to the same layer by utilizing first parallel sub-particles, and forming a Delaunay triangular mesh which takes the polygon vertexes as mesh nodes according to a Delaunay triangulation algorithm, wherein each side of the polygons comprises preset polygon number information;

aligning the Delaunay triangular mesh to each side of the plurality of polygons according to a side exchange method, simultaneously calculating intersection points of the sides of the polygons, and adding the intersection points as vertexes of the polygons and nodes of the Delaunay triangular mesh to form a first triangular mesh;

forming inner auxiliary polygons P sandwiching each polygon P inside and outside the polygon P, respectively, based on the first triangular mesh₀And an outer auxiliary polygon P₉Controlling the distance between the inner auxiliary polygon and the polygon P through a set distance threshold;

and aligning and simplifying the sides of each layer of polygons between the inner auxiliary polygon and the outer auxiliary polygon, and restoring the multi-layer polygons projected to the same layer into each layer according to polygon number information contained in the sides of each polygon.

3. The method of claim 2, wherein said aligning the Delaunay triangular mesh to respective edges of the plurality of polygons according to an edge-swapping method, while computing intersection points of the edges of the plurality of polygons and adding the intersection points as vertices of the polygons and nodes of the Delaunay triangular mesh, forming a first triangular mesh, comprises:

collecting all the edges of the polygon which are not the common edge of the two triangles, and sequencing according to the edge lengths to form a set Lost;

taking out the side with the longest side length from the set LostAnd remove it from the set Lost;

from the edgeIs sent, searching for the vertex A included and vertex C, D located on the edgeTriangle ACD at both sides, if the side is searched

the repeated search includes the vertex A and two other vertices are located on the edge

if the edge is searched

and judging whether the set Lost is an empty set, if not, taking out the longest side from the set Lost again, removing the longest side from the set Lost and continuing the side exchange, and if so, finishing the side exchange to form a first triangular grid.

4. The method according to claim 3, wherein inner auxiliary polygons P sandwiching each polygon P are respectively formed inside and outside the polygon P based on the first triangular mesh₀And an outer auxiliary polygon P₉And controlling the distance between the inner and outer auxiliary polygons and the polygon P through a set distance threshold, comprising:

copying the polygon P into a polygon P ', and generating a fifth triangular mesh T of the vertex of the polygon P';

inserting an auxiliary node into the triangular mesh T, so that each triangle in the fifth triangular mesh T has at most one edge coinciding with one edge of the polygon P', wherein two edges coinciding means that two edges have two same vertexes and the directions of the two edges are the same or different;

calculating the inner auxiliary polygon P' one by one according to the information of each edge and vertex of the polygon P₀With the outer auxiliary polygon P₉For each inner auxiliary polygon P to be calculated₀Are sequentially connected to form the inner auxiliary polygon, and each outer auxiliary polygon P is calculated₉The vertexes of the auxiliary polygon are sequentially connected to form the outer auxiliary polygon;

deleting the polygon P' and the fifth triangular mesh T, and adding the vertexes and edges of the two auxiliary polygons into the first triangular mesh;

and judging whether the sides of the auxiliary polygon are intersected or not, if so, dividing the two intersected sides into two at the intersection point, and adding the intersection point into the vertex of the auxiliary polygon and the first triangular mesh.

5. The method of claim 4, wherein aligning and simplifying the edges of the polygons in each layer between the inner and outer auxiliary polygons, and restoring the multi-layer polygons projected to the same layer into each layer according to polygon number information included in the edges of each polygon, comprises:

aligning the first triangular mesh to each side of the inner auxiliary polygon and the outer auxiliary polygon according to the side exchange method to form a second triangular mesh;

identifying vertices of all polygons in a region sandwiched by the inner and outer auxiliary polygons, defining the identified vertices as polygon vertices whose distance from the polygon P is less than a predetermined threshold;

for each polygon, finding out continuous identified vertexes of the polygon where the identified vertexes are located according to the identified vertexes, regarding a partial polygon segment or a complete polygon formed by the continuous identified vertexes as being overlapped with the polygon P, and combining the overlapped partial polygon segment or the complete polygon into the polygon P to form an aligned multi-layer polygon;

deleting the continuous identified vertexes, the edges between the continuous identified vertexes, and the vertexes, the edges of the inner and outer auxiliary polygons and the mesh nodes and the meshes corresponding to all the deleted vertexes and edges in the overlapped partial polygon segments or complete polygons in the second triangular mesh to form a third triangular mesh, aligning the third triangular mesh to the aligned multilayer polygons according to the edge exchange method to form a fourth triangular mesh;

simplifying the polygons projected to the same layer and aligned by adopting a single-layer polygon simplifying method;

and restoring the multi-layer polygons projected to the same layer into each layer according to the polygon number information contained in the sides of each polygon.

6. The method of claim 1, wherein performing adaptive mesh subdivision on the triangles in each of the parallel plate fields and then using a third parallel subparticle to perform field coupling between the parallel plate fields of the multi-layer very large scale integrated circuit layout and external circuitry of the integrated circuit comprises:

simplifying a parallel flat plate field three-dimensional model of a multilayer ultra-large scale integrated circuit layout by using third parallel sub-particles to obtain a plurality of two-dimensional models, establishing a frequency domain field equation set of the two-dimensional model corresponding to each third parallel sub-particle by using a finite element analysis method, and finally combining all the third parallel sub-particles to obtain a total sparse matrix of the frequency domain field equation set;

analyzing the external circuit of the multilayer super large scale integrated circuit by a circuit super node analysis method to obtain a symmetrical and positive external circuit equation set;

and combining the frequency domain field equation set and the external circuit equation set in a mode of scanning a super node to establish a symmetrical positive definite equation set of parallel flat plate field-circuit coupling.

7. The method of claim 6, wherein said analyzing external circuits of said multi-layer VLSI by circuit supernode analysis to obtain a symmetric positive set of external circuit equations comprises:

generating an external circuit of the integrated circuit not comprising the voltage source branch;

establishing a symmetrical and positive external circuit equation set for the external circuit of the integrated circuit without the voltage source branch circuit by a circuit super-node analysis method;

filling an external circuit of an integrated circuit containing a voltage source branch circuit with a super-node voltage vector, a super-node current vector, a non-reference-node voltage vector, a mutual conductance matrix of a super-node and a non-reference node and a super-node admittance matrix to generate an external circuit equation set of the super-node voltage vector; wherein the content of the first and second substances,

the external circuit equation set comprises a super-node voltage vector, a super-node current vector, a non-reference-node voltage vector, a mutual conductance matrix of the super-node and the non-reference node and a super-node admittance matrix.

8. The method of claim 7, wherein said combining the set of frequency domain field equations with the set of external circuit equations by scanning for a supernode to establish a symmetric positive definite set of parallel plate field-circuit couplings comprises:

scanning all the super nodes and changing the related grid node numbers according to the grid node and external circuit super node numbers independently generated by the third parallel sub-particles, and regenerating unified continuous node numbers after scanning is finished;

and combining a frequency domain field equation set corresponding to the third parallel sub-particles and the external circuit equation set according to the unified continuous node numbers to form a field-path coupled and symmetrical and positive unified equation set.

9. The method of any of claims 1-8, wherein said determining parallel sub-grains based on a fraction of the sum of the weighted CPU times in the total CPU time comprises:

and sequencing the weighted CPU time of each calculation particle in a descending order and sequentially accumulating until the accumulated sum exceeds the preset proportion of the total CPU time, and taking each calculation particle in the accumulated sum as a parallel sub-particle.

10. An integrated circuit electromagnetic response computing device based on a multilevel parallel strategy is characterized by comprising:

the frequency point setting module is used for setting a plurality of frequency points which need to be calculated in a preset frequency band range by the frequency domain simulation of the multilayer very large scale integrated circuit;

the system comprises a first processing module, a second processing module and a third processing module, wherein the first processing module is used for taking the integral calculation process of the electromagnetic response characteristics of the multilayer VLSI executing each frequency point as a calculation task and dividing a calculation program of the integral calculation process into a plurality of non-overlapping calculation particles, the calculation particles are calculation programs executing all independent calculations of the same type, and one independent calculation executed by the calculation particles is taken as a calculation subtask;

the second processing module is used for acquiring weighted CPU time required by each calculation particle to execute the corresponding calculation sub-task and total CPU time required by the electromagnetic response characteristic calculation process of each frequency point of the whole integrated circuit, and determining parallel sub-particles according to the proportion of the sum of the weighted CPU time in the total CPU time;

the third processing module is used for executing the alignment and simplification processing of the polygon of the multilayer super large scale integrated circuit layout by utilizing the first parallel sub-particles;

the fourth processing module is used for identifying and collecting triangles and polygon edges contained in each parallel flat plate field of the multilayer very large scale integrated circuit layout by using second parallel sub-particles through a parallel flat plate field identification method after aligning and simplifying the polygons of the multilayer very large scale integrated circuit layout, and performing adaptive mesh subdivision processing on the triangles in each parallel flat plate field according to the calculation precision requirement and the common areas of different parallel flat plate fields;

the fifth processing module is used for performing adaptive grid subdivision processing on the triangles in each parallel flat field and then performing field-path coupling on the parallel flat fields of the multilayer ultra-large scale integrated circuit layout and an external circuit of the integrated circuit by using third parallel sub-particles;

and the sixth processing module is used for independently executing a plurality of computing tasks corresponding to a plurality of frequency points by using a plurality of parallel coarse particles to complete the multi-process parallel computing of the plurality of frequency points.

Technical Field

The invention relates to the field of integrated circuit high-performance calculation, in particular to an integrated circuit electromagnetic response calculation method and device based on a multilevel parallel strategy.

Background

Integrated circuits have played a very important role in various industries and are a cornerstone of modern information society. It is a miniature electronic device or component, and is made up by adopting a certain technological process to make the elements of transistor, resistor, capacitor and inductor, etc. required in a circuit and wiring interconnection together, and make them be made into a small piece or several small pieces of semiconductor wafer or medium substrate, then package them in a tube shell so as to obtain the miniature structure with required circuit function.

And calculating the acquired electromagnetic response characteristics of a plurality of frequency points in the frequency range in the frequency domain simulation of the multilayer very large scale integrated circuit to obtain an electromagnetic response curve of the integrated circuit in the frequency range.

However, in the process of implementing the present invention, the inventor finds that, in the prior art, the above-mentioned integrated circuit frequency domain simulation electromagnetic response characteristic calculation process for frequency points involves massive large-scale numerical calculation of the same type, whereas the conventional parallel calculation is basically parallel to a single calculation example, and parallel is implemented in a large number of cyclic calculation parts, and parallel particles are usually very fine, so that a large amount of data exchange exists among different processes, and the parallel calculation efficiency is reduced; in addition, the prior parallel strategy does not divide the parallel computation into different layers according to the computation complexity of different computation modules, but performs the parallel computation according to the same layer, so that in the process of the parallel computation, a main process generates a large amount of waiting time for collecting the computation results of all slave processes at different stages, and the parallel computation efficiency is further low; moreover, in order to obtain an electromagnetic response curve of an integrated circuit with smaller error, response characteristics of different frequency points with larger quantity are generally required to be calculated, and the parallel calculation efficiency in the prior art is lower, so that the practical requirement that the frequency domain simulation of a multilayer very large scale integrated circuit still has higher calculation efficiency on the calculation of the response characteristics of the frequency points is difficult to meet.

Disclosure of Invention

The embodiment of the application provides an integrated circuit electromagnetic response calculation method and device based on a multilevel parallel strategy, which can improve the calculation efficiency of frequency domain simulation of multilayer super-large-scale integrated circuits on each part in the calculation of electromagnetic response characteristics of frequency points, can also improve the parallel calculation efficiency of electromagnetic response characteristics of integrated circuits with larger number of different frequency points, and meet the requirement of efficient calculation.

In a first aspect, an embodiment of the present application provides an integrated circuit electromagnetic response calculation method based on a multilevel parallel strategy, where the method includes:

setting a plurality of frequency points which need to be calculated in a preset frequency band range by using multilayer very large scale integrated circuit frequency domain simulation;

performing alignment and simplification processing of the polygons of the multilayer very large scale integrated circuit layout by using the first parallel sub-particles;

As a possible implementation, the performing the alignment and simplification process of the polygons of the multi-layer vlsi layout using the first parallel sub-granule includes:

As a possible implementation, the aligning the Delaunay triangular mesh to the respective edges of the plurality of polygons according to an edge exchange method, while calculating intersection points of the edges of the plurality of polygons and adding the intersection points as vertices of the polygons and nodes of the Delaunay triangular mesh, to form a first triangular mesh, includes:

collecting all the edges of the polygon which are not the common edge of the two triangles, and sequencing according to the edge lengths to form a set Lost;

taking out the side with the longest side length from the set Lost

And remove it from the set Lost;

from the edgeIs sent, searching for the vertex A included and vertex C, D located on the edgeTriangle ACD at both sides, if the side is searchedIntersecting edges

Exchanging the common edge of the triangle delta ACD and the adjacent triangle delta DCE instead of the edge of the other polygon to obtain a triangle delta ACE and a triangle delta EDA, wherein the adjacent triangle is a triangle having a common edge with the triangle;

the repeated search includes the vertex A and two other vertices are located on the edgeTriangles on both sides exchange the common edge of the triangle with its neighbor triangles until the edgeIs a common edge of two neighboring triangles;

if the edge is searchedIf the crossed edge is the edge of another polygon, the exchange of the crossed edge is cancelled, and a vertex and a mesh node are directly added at the intersection point of the two edgesInserting the mesh node into the Delaunay triangular mesh, wherein the mesh node divides the two neighboring triangles into four triangles, and the vertex divides two intersected edges into four edges sharing the vertex;

As a possible implementation, the inner auxiliary polygons P sandwiching the polygon P are respectively formed inside and outside each polygon P based on the first triangular mesh₀And an outer auxiliary polygon P₉And controlling the distance between the inner and outer auxiliary polygons and the polygon P through a set distance threshold, comprising:

copying the polygon P into a polygon P ', and generating a fifth triangular mesh T of the vertex of the polygon P';

deleting the polygon P' and the fifth triangular mesh T, and adding the vertexes and edges of the two auxiliary polygons into the first triangular mesh;

As a possible embodiment, the aligning and simplifying the edges of the polygons in each layer between the inner and outer auxiliary polygons, and restoring the multi-layer polygons projected to the same layer into each layer according to the polygon number information included in the edges of each polygon includes:

aligning the first triangular mesh to each side of the inner auxiliary polygon and the outer auxiliary polygon according to the side exchange method to form a second triangular mesh;

simplifying the polygons projected to the same layer and aligned by adopting a single-layer polygon simplifying method;

and restoring the multi-layer polygons projected to the same layer into each layer according to the polygon number information contained in the sides of each polygon.

As a possible implementation manner, after performing adaptive mesh subdivision processing on the triangles in each parallel flat field, performing field-circuit coupling on the parallel flat fields of the multilayer very large scale integrated circuit layout and the external circuit of the integrated circuit by using the third parallel sub-particles, includes:

analyzing the external circuit of the multilayer super large scale integrated circuit by a circuit super node analysis method to obtain a symmetrical and positive external circuit equation set;

As a possible implementation, the analyzing the external circuit of the multi-layer vlsi circuit by the circuit super-node analysis method to obtain a symmetric positive external circuit equation set includes:

generating an external circuit of the integrated circuit not comprising the voltage source branch;

As a possible implementation, the merging the frequency domain field equation set and the external circuit equation set by scanning the super node to establish a symmetric positive definite equation set of parallel flat-panel field-circuit coupling includes:

As a possible implementation, the determining parallel sub-grains according to the ratio of the weighted CPU time sum to the total CPU time includes:

In a second aspect, an embodiment of the present application provides an integrated circuit electromagnetic response calculation apparatus based on a multi-level parallel strategy, the apparatus including:

The embodiment of the application has the following beneficial effects:

according to the method, a plurality of frequency points needing to be calculated in a preset frequency band range are simulated by setting a plurality of layers of frequency domains of the very large scale integrated circuit; taking the integrated circuit electromagnetic response characteristic overall calculation process of executing each frequency point as a calculation task, dividing a calculation program of the overall calculation process into a plurality of non-overlapping calculation particles, and taking an independent calculation executed by the calculation particles as a calculation subtask; acquiring weighted CPU time required by each calculation particle to execute the corresponding calculation sub-task and total CPU time required by the electromagnetic response characteristic calculation process of each frequency point of the whole integrated circuit, and determining parallel sub-particles according to the proportion of the sum of the weighted CPU time in the total CPU time; respectively executing a plurality of calculation sub-tasks in the integrated circuit electromagnetic response characteristic calculation process of each frequency point by using a plurality of parallel sub-particles; the method has the advantages that a plurality of parallel coarse particles are utilized to independently execute a plurality of calculation tasks corresponding to a plurality of frequency points, the multi-process parallel calculation of the frequency points is completed, the calculation efficiency of frequency domain simulation of multilayer super large scale integrated circuits on each part in the calculation of electromagnetic response characteristics of the frequency points can be improved, the parallel calculation efficiency of electromagnetic response characteristics of integrated circuits with large number of different frequency points can be improved, and the high-efficiency calculation requirement is met.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic flowchart of an embodiment of a method for calculating an electromagnetic response of an integrated circuit based on a multilevel parallel policy provided in the present application.

Fig. 2 is a schematic diagram of intersecting each layer of polygons after being projected to the same layer and forming a Delaunay triangular mesh in the embodiment of the integrated circuit electromagnetic response calculation method based on the multilevel parallel strategy provided in the present application.

Fig. 3 is a partially enlarged view of a Delaunay triangular mesh in an embodiment of the integrated circuit electromagnetic response calculation method based on a multilevel parallel strategy provided in the present application.

Fig. 4 is a schematic diagram of a switching process of the edge switching method in an embodiment of the integrated circuit electromagnetic response calculation method based on a multilevel parallel strategy provided in the present application.

Fig. 5 is a schematic diagram of mesh generation of a polygon selected when an auxiliary polygon is formed in the embodiment of the integrated circuit electromagnetic response calculation method based on the multilevel parallel strategy provided by the present application.

Fig. 6 is a mesh generation diagram after an auxiliary node is inserted into a selected polygon when an auxiliary polygon is formed in the embodiment of the integrated circuit electromagnetic response calculation method based on the multilevel parallel strategy provided by the present application.

FIG. 7 is a schematic diagram of an auxiliary polygon formed in an embodiment of a method for calculating an electromagnetic response of an integrated circuit based on a multilevel parallel strategy according to the present application.

Fig. 8 is a schematic diagram illustrating intersection of an internal auxiliary polygon and an external auxiliary polygon in an embodiment of a method for calculating an electromagnetic response of an integrated circuit based on a multilevel parallel strategy provided in the present application.

Fig. 9 is a schematic diagram of field-circuit coupling between parallel flat-plate fields of a multilayer vlsi layout and external circuits of an integrated circuit by using third parallel sub-particles in an embodiment of the integrated circuit electromagnetic response calculation method based on a multilevel parallel strategy provided in the present application.

Fig. 10 is a schematic diagram illustrating numbering of external circuits and initial nodes in an embodiment of a method for calculating an electromagnetic response of an integrated circuit based on a multilevel parallel strategy according to the present application.

Fig. 11 is a schematic numbering diagram of an external circuit and a supernode in an embodiment of the integrated circuit electromagnetic response calculation method based on a multilevel parallel policy provided in the present application.

Fig. 12 is a schematic diagram illustrating an external circuit-field and an initial node number thereof in an embodiment of an integrated circuit electromagnetic response calculation method based on a multilevel parallel strategy according to the present application.

Fig. 13 is a schematic diagram of an external circuit-field and its unified node numbering in an embodiment of the integrated circuit electromagnetic response calculation method based on a multilevel parallel policy provided in the present application.

Fig. 14 is a schematic diagram illustrating the numbers of external circuit-field and coupling nodes thereof in an embodiment of the integrated circuit electromagnetic response calculation method based on a multilevel parallel strategy provided in the present application.

FIG. 15 is a schematic structural diagram of an embodiment of an integrated circuit electromagnetic response calculation apparatus based on a multilevel parallelism strategy provided in the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be described in detail by embodiments with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. In the description of the present invention, "a plurality" means two or more unless otherwise specified. In the description of the present invention, "first", "second", "third", "fourth", "fifth", and the like are used only for distinguishing one from another, and do not indicate the degree of importance, the order, and the like thereof.

Referring to fig. 1-14, an embodiment of the present application provides a method for calculating an electromagnetic response of an integrated circuit based on a multilevel parallel strategy; as shown, the method mainly comprises:

step 100, setting a plurality of frequency points needing to be calculated in a preset frequency band range for frequency domain simulation of a multilayer very large scale integrated circuit;

step 200, taking the integral calculation process of the electromagnetic response characteristics of the multilayer VLSI executing each frequency point as a calculation task, and dividing a calculation program of the integral calculation process into a plurality of non-overlapping calculation particles, wherein the calculation particles are calculation programs executing all independent calculations of the same type, and an independent calculation executed by the calculation particles is taken as a calculation subtask;

step 300, acquiring weighted CPU time required by each calculation particle to execute the corresponding calculation sub-task and total CPU time required by the electromagnetic response characteristic calculation process of each frequency point of the whole integrated circuit, and determining parallel sub-particles according to the proportion of the sum of the weighted CPU time in the total CPU time;

step 400, utilizing the first parallel sub-particles to execute the alignment and simplification processing of the multi-layer very large scale integrated circuit layout polygon;

step 500, after the polygons of the multilayer VLSI layout are aligned and simplified, identifying and collecting triangles and polygon edges contained in each parallel flat field of the multilayer VLSI layout by using second parallel sub-particles through a parallel flat field identification method, and performing adaptive mesh subdivision processing on the triangles in each parallel flat field according to the calculation precision requirement and the common areas of different parallel flat fields;

step 600, after adaptive mesh subdivision processing is performed on the triangles in each parallel flat field, field-circuit coupling is performed on the parallel flat fields of the multilayer very large scale integrated circuit layout and an external circuit of the integrated circuit by using third parallel sub-particles;

step 700, independently executing the calculation of a plurality of calculation tasks corresponding to a plurality of frequency points by using a plurality of parallel coarse particles, and completing the multi-process parallel calculation of the plurality of frequency points.

By adopting the method, the calculation efficiency of each part in the calculation of the electromagnetic response characteristics of the frequency points by the frequency domain simulation of the multilayer very large scale integrated circuit can be improved, the parallel calculation efficiency of the electromagnetic response characteristics of the integrated circuits with different frequency points with larger number can also be improved, and the high-efficiency calculation requirement can be met.

Wherein the calculation particles are defined according to the problem calculation characteristics. The problem calculation characteristics are different from industry to industry. For example, the electromagnetic response characteristics of frequency points of frequency domain simulation of the large-scale integrated circuit are calculated, and the problem calculation characteristics are that when the multilayer integrated circuit board with a certain structure and an external circuit thereof are subjected to field-path coupling, the alignment and simplification of polygons in different layouts, the external circuit matrix symmetry processing, the formation of a large-scale integrated circuit electromagnetic field distribution numerical calculation sparse matrix, the large-scale sparse matrix solution, the current, potential and power density distribution of each layer plate are calculated based on the solved field, and the like.

Specifically, if the whole calculation process of the electromagnetic response characteristics of the extracted integrated circuit of one frequency point is divided into 2 calculation particles of c1 and c2 according to the definition of the calculation particles, 2 calculation particles can execute the calculation task of the whole calculation process; if c1 executes 100 computation subtasks, c2 executes 200 computation subtasks; then a total of 300 computation subtasks constitute the entire computation process, which only requires c1, c2, and a total of 2 computation particles to implement. Wherein the execution of the whole calculation process requires 2 calculation particles of c1 and c2 in sequence, and each of c1 and c2 comprises at least 1 independent calculation (calculation task).

As a possible implementation manner, the performing, by using the first parallel sub-granule, alignment and simplification processing of polygons in a multilayer very large scale integrated circuit layout in step 400 mainly includes:

using the first parallel sub-particles to perform the following steps:

step 410, vertically projecting a plurality of polygons including a plurality of vertexes in each layer of a multilayer very large scale integrated circuit layout to the same layer, and forming a Delaunay triangular mesh taking the polygon vertexes as mesh nodes according to a Delaunay triangulation algorithm, wherein each side of the polygons includes preset polygon number information;

step 420, aligning the Delaunay triangular mesh to each edge of the plurality of polygons according to an edge exchange method, calculating intersection points of the plurality of polygon edges, and adding the intersection points as vertices of the polygons and nodes of the Delaunay triangular mesh to form a first triangular mesh;

step 430, based on the first triangular mesh, forming an inner auxiliary polygon P inside and outside each polygon P to clamp the polygon P₀And an outer auxiliary polygon P₉Controlling the distance between the inner auxiliary polygon and the polygon P through a set distance threshold;

step 440, aligning and simplifying the sides of each layer of polygons between the inner and outer auxiliary polygons, and restoring the multi-layer polygons projected to the same layer to each layer according to the polygon number information contained in the sides of each polygon.

By adopting the method, the fragmentation problem generated after the multi-layer polygons form the parallel flat plate field areas can be greatly reduced, unnecessary dense grids generated near fragments when the field areas are subjected to grid subdivision are further obviously reduced, the grid quality is greatly improved, the solving time and the required memory of multi-layer integrated circuit analysis are shortened, and the shape of the integrated circuit layout is basically not changed even if the width of gaps among the polygons is in the nanometer level before the adaptive simplification processing is carried out on the premise that the polygon shape is almost maintained, and the gaps among the polygons are completely reserved after the adaptive simplification processing, so that the circuit connection of the original normal integrated circuit layout is maintained.

The polygon is defined as a closed graph formed by sequentially connecting N (N is more than or equal to 3) line segments end to end, and the line segment endpoints form the polygon vertexes. If the vertexes of the polygons are arranged anticlockwise, defining the polygons as positive, and corresponding to the conductive areas of the integrated circuit layout in the polygons; if the polygon vertexes are arranged clockwise, defining the polygon as negative, and corresponding to the integrated circuit layout insulation area in the polygon; the directions of all triangles in the Delaunay triangular mesh formed according to the Delaunay triangulation algorithm are positive. When the propagation of electromagnetic waves in a very large scale integrated circuit is calculated by a numerical calculation method, a conductive region and a dielectric layer of an integrated circuit layout and a parallel flat plate field formed by the conductive region and the dielectric layer need to be considered.

As a possible implementation, the aligning the Delaunay triangular mesh to each edge of the polygons according to the edge exchange method in the step 420, and simultaneously calculating intersection points of the polygon edges and adding the intersection points as the vertices of the polygons and the nodes of the Delaunay triangular mesh to form a first triangular mesh mainly includes:

step 421, collecting all the sides of the polygon which are not the common side of the two triangles, and sorting the sides according to the side length to form a set Lost;

step 422, the side with the longest side length is taken out from the set Lost

And remove it from the set Lost;

step 423, from the edgeStarting from one vertex A, search for a packetContaining the vertex A and the vertex C, D being located on the edge

Triangle ACD at both sides, if the side is searchedIntersecting edges

step 424, repeating said step 423 until said edgeIs a common edge of two neighboring triangles;

step 425, if the edge is foundIf the intersected edge is the edge of another polygon, the exchange of the intersected edge is cancelled, a vertex and a mesh node are directly added at the intersection point of the two edges, the mesh node is inserted into the Delaunay triangular mesh, the mesh node divides the two adjacent triangles into four triangles, and the vertex divides the two intersected edges into four edges sharing the vertex; referring to fig. 4, fig. 4 is a schematic diagram illustrating a switching process of the edge switching method in an embodiment of a method for calculating an electromagnetic response of an integrated circuit based on a multilevel parallel strategy according to the present application; it is noted that the edges are shown in FIG. 4

Intersecting edges

Is also an edge of another polygon, thus takingThe exchange of the edges is eliminated, a vertex and a mesh node G are directly added at the intersection point of the two edges, the mesh node G is inserted into the Delaunay triangular mesh, the mesh node G divides the two adjacent triangles into four triangles, and the vertex divides the two intersected edges into four edges sharing the vertex;

and 426, judging whether the set Lost is an empty set, if not, turning to 422, and if so, ending the edge exchange to form a first triangular mesh.

As a possible embodiment, the set distance threshold is a value calculated according to the information of the polygon and the mesh, and the calculation formula of the distance threshold is as follows:

wherein n is_bNumber of sides, l, of said polygon P_iRepresents the length of the ith side of the polygon P, m_irepresenting a weighting factor corresponding to the ith edge;

represents a round-down operation; e.g. of the type_maxRepresenting the largest triangle side length among all triangles of the mesh.

As a possible implementation manner, the step 430 forms inner auxiliary polygons P sandwiching each polygon P inside and outside the polygon P based on the first triangular mesh₀And an outer auxiliary polygon P₉And controlling the distance between the inner and outer auxiliary polygons and the polygon P through a set distance threshold, mainly comprising:

step 431, copying the polygon P into a polygon P ', and generating a fifth triangular mesh T of the vertex of the polygon P'; referring to fig. 5, fig. 5 is a schematic diagram illustrating mesh generation of a polygon selected when forming an auxiliary polygon in an embodiment of an integrated circuit electromagnetic response calculation method based on a multilevel parallel strategy according to the present application;

step 432, inserting an auxiliary node into the triangular mesh T, so that at most one edge of each triangle in the fifth triangular mesh T coincides with one edge of the polygon P', wherein two edges coincide with each other, that is, two edges have two same vertices, and the directions of the two edges are the same or different; referring to fig. 6, fig. 6 is a schematic diagram illustrating mesh generation after inserting auxiliary nodes into a selected polygon when forming an auxiliary polygon in an embodiment of a method for calculating an electromagnetic response of an integrated circuit based on a multilevel parallel strategy according to the present application; as shown in the figure, four auxiliary nodes are inserted into the polygon P 'to form a new triangle, and in fig. 6, at most one edge of each triangle in the fifth triangular mesh T coincides with one edge of the polygon P';

step 433, calculating the inner auxiliary polygon P one by one according to the information of each edge and vertex of the polygon P₀With the outer auxiliary polygon P₉The respective vertex information of (2): let two adjacent edges of a vertex B of the polygon P' beAndthe two adjacent sides form a triangle delta ABC with side lengths of a, b and c, and the calculation formulas of the radius and the center of a circle inscribed in the triangle are respectively as follows:

wherein (x)_i,y_i) (i-1, 2,3) represents the three vertex coordinates of said triangle Δ ABC,

obtaining vertex coordinate formulas of the inner auxiliary polygon and the outer auxiliary polygon corresponding to the vertex B according to the formula (1) of the distance threshold, wherein the vertex coordinate formulas are respectively as follows:

wherein (x)_b,y_b) The coordinates of the vertex B, i being 0 and 9, respectively correspond to the inner auxiliary polygon P₀Outer auxiliary polygon P₉Inner auxiliary polygon P corresponding to the vertex B₀The vertex of the triangle takes the center of the triangle delta ABC inscribed circle and the outer auxiliary polygon P corresponding to the vertex B₉The vertex of (a) is a mirror image of the circle center about the vertex B, and coordinates of inner and outer mirror image points corresponding to the vertex B are respectively as follows:

x_b0＝x,y_b0＝y

x_b9＝2x_b-x,y_b9＝2y_b-y，

sequentially connecting the vertexes of the inner auxiliary polygons correspondingly calculated by i-0 to form the inner auxiliary polygons, and sequentially connecting the vertexes of the outer auxiliary polygons correspondingly calculated by i-9 to form the outer auxiliary polygons; referring to FIG. 7, FIG. 7 is a schematic diagram illustrating an auxiliary polygon formed in an embodiment of a method for calculating an electromagnetic response of an integrated circuit based on a multilevel parallel strategy according to the present application;

step 434, deleting the polygon P' and the fifth triangular mesh T, and adding the vertices and edges of the two auxiliary polygons into the first triangular mesh;

step 435, determining whether the edges of the auxiliary polygon intersect, if yes, dividing the two intersecting edges into two at the intersection point, and adding the intersection point to the vertex of the auxiliary polygon and the first triangular mesh; referring to fig. 8, fig. 8 is a schematic diagram illustrating intersection of an inner auxiliary polygon and an outer auxiliary polygon in an embodiment of a method for calculating electromagnetic response of an integrated circuit based on a multilevel parallel strategy provided in the present application, where the polygons are drawn with thick solid lines, the auxiliary polygons are drawn with dotted lines, and edges of the auxiliary polygons intersect at A, B, C, which are then added to vertices of the auxiliary polygons and a first triangular mesh.

As a possible implementation manner, the aligning and simplifying the edges of the polygons in each layer between the inner and outer auxiliary polygons in step 440, and restoring the multi-layer polygons projected to the same layer into each layer according to the polygon number information contained in the edges of each polygon, mainly includes:

step 441, aligning the first triangular mesh to each side of the inner and outer auxiliary polygons according to the side exchange method to form a second triangular mesh;

step 442, identifying the vertices of all polygons in the region clamped by the inner and outer auxiliary polygons, and defining the identified vertices as the vertices of the polygons with the distance from the polygon P smaller than a predetermined threshold;

step 443, for each polygon, finding out continuous identified vertices located in the polygon where the identified vertices are located according to the identified vertices, regarding a partial polygon segment or a complete polygon formed by the continuous identified vertices as being overlapped with the polygon P, and merging the overlapped partial polygon segment or complete polygon into the polygon P to form an aligned multi-layer polygon;

step 444, deleting the continuous identified vertexes, the edges between the continuous identified vertexes, and the vertexes, the edges of the inner and outer auxiliary polygons, and the mesh nodes and the meshes corresponding to all the deleted vertexes and edges in the overlapped partial polygon segments or complete polygons in the second triangular mesh to form a third triangular mesh, aligning the third triangular mesh to the aligned multi-layer polygons according to the edge exchange method to form a fourth triangular mesh;

step 445, simplifying the polygons projected to the same layer and aligned by adopting a single-layer polygon simplifying method;

step 446, restoring the multi-layer polygons projected to the same layer to each layer according to the polygon number information contained in the sides of each polygon.

As a possible implementation manner, after the aligning and simplifying processing is performed on the polygons of the multilayer very large scale integrated circuit layout in step 500, the second parallel sub-particles are used to identify and collect the triangles and polygon edges included in each parallel flat plate field of the multilayer very large scale integrated circuit layout by a parallel flat plate field identification method, and according to the calculation precision requirement and the common area of different parallel flat plate fields, the adaptive mesh subdivision processing is performed on the triangles in each parallel flat plate field, which mainly includes:

using the second parallel sub-particles to perform the following steps:

setting a polygon set poly (i, j) and a triangle set tri (i, j) of all parallel flat field areas (i, j) to be empty, wherein the parallel flat field areas (i, j) are parallel flat field areas formed by the ith layer and the jth layer of a metal layer in the multilayer integrated circuit layout and internal media of the ith layer and the jth layer, and i and j are layers of the metal layer;

selecting an unprocessed triangle t or polygon edge e, identifying a jth metal layer, j > i, appearing for the first time upwards on the ith metal layer from the lowest layer according to the layer information of the triangle t or polygon edge e, adding the triangle t into the set tri (i, j) or adding the polygon edge e into the poly (i, j) so as to collect the triangle and polygon edges contained in each parallel flat plate field;

judging whether the metal layer i is the highest layer, if so, continuing the next operation, if not, assigning the j to the i, returning to and continuing to determine the j-th metal layer appearing for the first time on the i-th layer according to the layer information of the triangle t or the polygon edge e;

judging whether all the triangle and polygon edges are identified, if so, finishing the identification, otherwise, returning to continuously select an unprocessed triangle or polygon edge, and identifying and collecting;

then, the vertexes of a plurality of polygons of each parallel flat plate field are obtained, and a second triangular mesh is formed according to a Delaunay triangulation algorithm;

aligning the second triangular mesh to the sides of a plurality of polygons of each parallel flat plate field according to the identified parallel flat plate fields, and deleting triangles outside each parallel flat plate field to form a third triangular mesh;

sequentially carrying out mesh subdivision processing on the parallel flat plate field areas (i, j) in each third triangular mesh according to the priority sequence of first priority control on the quality of the meshes and second priority control on the size of the meshes;

performing mesh subdivision on a common area of two adjacent parallel flat plate fields, wherein if layer information of a polygonal side e of the parallel flat plate field (i, j) comprises the parallel flat plate field (i, j) and a parallel flat plate field (l, m), wherein two numbers in the i, j, l, m are equal, an area corresponding to the polygonal side e is the common area of the parallel flat plate field (i, j) and the parallel flat plate field (l, m), the common area is defined as an inter-plate coupling area, and the i, j, l, m are layers of the metal layer;

and judging whether the quality and the size of the grids of all the parallel flat plate fields meet preset values, if so, finishing the grid subdivision, and if not, returning to continue to carry out the grid subdivision on each parallel flat plate field (i, j).

As a possible implementation manner, after performing adaptive mesh subdivision processing on the triangles in each parallel flat field in step 600, performing field coupling on the parallel flat fields of the multilayer very large scale integrated circuit layout and the external circuit of the integrated circuit by using a third parallel sub-particle, mainly includes:

using the third parallel sub-particle to complete the following steps:

step 610, as shown in fig. 9, simplifying a parallel flat plate field three-dimensional model of a multilayer very large scale integrated circuit layout to obtain a plurality of two-dimensional models, establishing a frequency domain field equation set of the two-dimensional model corresponding to each third parallel sub-particle by a finite element analysis method, and finally merging all the third parallel sub-particles to obtain a total sparse matrix of the frequency domain field equation set; in fig. 10, the different domains and their external circuits are coupled to each other by vias, because each domain and its external circuit formed by the integrated circuits of the various layers is not an isolated electrical connection, and all the domains ultimately form an integrated system.

However, the computational resources required for solving the three-dimensional model of the electromagnetic response characteristic of a frequency point in the frequency domain simulation of the multilayer very large scale integrated circuit by the three-dimensional method are huge, and the method is difficult to be used for really analyzing the complex very large scale integrated circuit system under the existing computational resources. However, as it can be seen from the analysis of the dimension characteristics of the multi-layer very large scale integrated circuit, in the frequency domain simulation of the multi-layer very large scale integrated circuit, since the dimension of the actual PCB or chip package in the multi-layer very large scale integrated circuit is much larger than the thickness and the distance between the boards, it can be known that the frequency domain simulation of the multi-layer very large scale integrated circuit is not changed in the thickness direction of the boards, and therefore, an equation which is simplified into two dimensions can be used to solve the problem which needs to be solved by using a three-dimensional equation, and therefore, in step 610, the three-dimensional model can be.

In step 610, the distributions of dielectric constant, permeability μ, electric field strength E, and magnetic field strength H in the three-dimensional model of the electromagnetic response characteristic of a frequency point in the frequency domain simulation of the multi-layer very large scale integrated circuit are all functions of three-dimensional space coordinates (x, y, z), that is: and (x, y, z), μ ═ μ (x, y, z), E ═ E (x, y, z), H ═ H (x, y, z). The function of the three-dimensional model satisfies the following equation:

where J is the applied current density distribution and ω is the angular frequency of the integrated circuit simulation.

In step 610, when the actual PCB or chip package board size in the multi-layer VLSI is much larger than the board thickness and the board spacing H, the three-dimensional model of the electromagnetic response characteristic of a frequency point in the frequency domain simulation of the multi-layer VLSI can be simplified into a two-dimensional model, and the distribution of dielectric constant, magnetic permeability mu, electric field strength E and magnetic field strength H in the model is two-dimensional plane coordinates (x, y)I.e.: and (x, y), μ ═ μ (x, y), E ═ E (x, y), H ═ H (x, y), and the distribution is independent of z. And the potential u and the surface current density J in the field_sSatisfies the following conditions:

in the formulaRespectively representing unit vectors in the x, y, z directions, E_zIs the z-direction component of the electric field strength, H_xAnd H_yThe x and y directional components of the magnetic field strength, respectively.

Through the equivalence from the three-dimensional model to the two-dimensional model, the two-dimensional finite element functional extreme value formula corresponding to the two-dimensional model is obtained as follows:

in the formula (I), the compound is shown in the specification,

is a functional, means to take an extreme value to the functional,for the surface admittance of the grid cell i,

is a boundary_jIs determined by the constant of (a) and (b),is a normal vector of the cell surface, V is a boundary_jVolume of the corresponding grid cell, u_kIs a boundary_kThe distribution of the electric potential on the upper side,

indicating a position to the right of the boundary and infinitely close to the boundary,

denotes the position to the left of the boundary and infinitely close to the boundary, Ω_iIndicates the area of the cell i, J_ziIs the current density of grid cell i, Z_siIs the surface impedance of the grid cell i, u_iIs the potential of grid cell i.

With the extreme conditions of equation (6), a finite element stiffness matrix can be formed. Meanwhile, the chip and the circuit board are usually driven by a voltage source through an external circuit, so that the external circuit and the field can be coupled through an access point of the circuit to perform joint solution.

And step 620, analyzing the external circuit of the multilayer super large scale integrated circuit by a circuit super node analysis method to obtain a symmetrical and positive external circuit equation set. The circuit super-node analysis method is an external circuit equation set analysis method based on a super node. The super node is a node comprising a group of circuits, one super node comprises a group of circuit nodes, the voltage between any two points of the group of nodes can be intuitively obtained through an ideal voltage source contained in the super node, but the potential between any point outside the super node and any point inside the super node is unknown. Usually, the external circuit includes a large number of super nodes, and the external circuit can be divided into different circuit modules, as shown in fig. 11, the different external circuit modules are also coupled, and after each external circuit module is processed, the processing result is collected and coupled.

In the prior art, a common node analysis method is used for analyzing a branch external circuit to obtain the following node voltage equation:

wherein G ═ A_YG_eA_Y ^T，A_YAnd A_eAre all basic correlation matrices, A_YAssociated with branches without ideal voltage source, A_eAssociated with a branch containing an ideal voltage source, J ═ A_Y(G_eu_g-i_g) Is an equivalent node current source vector, G_eAdmittance of branchArray, i_eIs the current vector of the ideal voltage source branch u_gIs a voltage source branch vector, i_gIs a current source branch vector, u is a node voltage vector, and e is a voltage vector of an ideal voltage source branch.

In the field coupling process, the following defects are generated by directly coupling the node voltage equation of equation (7) with the finite element equation: first, the part of diagonal elements in the matrix of equation (7) is 0, which makes the coupled matrix not a positive definite matrix, resulting in an increase in solution time. Second, directly incorporating the matrix in equation (7) into the finite element stiffness matrix would make the current of the ideal voltage source the unknown to be solved, resulting in an increase in the unknown, and not consistent with the finite element method's use of the node voltage as the unknown. Thus, a symmetrical positive external circuit equation set is formed in step 520 using a circuit supernode analysis method.

And 630, combining the frequency domain field equation set and the external circuit equation set in a mode of scanning a super node, and establishing a symmetrical positive definite equation set of parallel flat plate field-circuit coupling.

As a possible implementation manner, the analyzing the external circuit of the multi-layer very large scale integrated circuit by the circuit super node analysis method in step 620 to obtain a symmetric positive external circuit equation set mainly includes:

step 621 generates an external circuit for the integrated circuit that does not include a voltage source branch.

And 622, establishing a symmetrical and positive external circuit equation set for the external circuit of the integrated circuit without the voltage source branch circuit by a circuit super-node analysis method.

Step 623, filling an external circuit of the integrated circuit containing the voltage source branch circuit with a super-node voltage vector, a super-node current vector, a non-reference-node voltage vector, a mutual conductance matrix of the super-node and the non-reference node and a super-node admittance matrix, and generating an external circuit equation set of the super-node voltage vector; wherein the content of the first and second substances,

As a possible way of implementing the method,

the super node voltage vector is a vector formed by the voltages of all super node reference nodes;

the super node current vector is a vector formed by the sum of all currents flowing into each super node;

the length of the voltage vector of the non-reference node is the number of all non-reference nodes, and the ith element P of the non-reference nodes_iThe potential of the non-reference node i to its reference node is the sum of the voltages of all ideal voltage source branches on the path from the non-reference node i to its reference node;

the rows of the mutual conductance matrixes of the super nodes and the non-reference nodes correspond to the super nodes, the columns of the mutual conductance matrixes of the super nodes and the non-reference nodes correspond to the non-reference points, and the elements P of the ith row and the jth column of the super nodes and the non-reference nodes_ijIs the mutual conductance of a super node i and a non-reference point j or the self-conductance of the non-reference node j, wherein if the non-reference point j belongs to the super node i, the P is_ijIs the self-conductance with the value of the non-reference point j being positive, if the non-reference point j does not belong to the super node i, then the P_ijMutual conductance is that the values of the supernode i and the non-reference point j are negative;

the rows and the columns of the super-node admittance matrix correspond to super-nodes, and the ith row diagonal element Pd of the super-node admittance matrix_iIs the self-conductance of the ith super node, Pd_iIs the admittance sum of all the branches connected to the ith branch, the ith row and the jth column element P_ijIs the mutual conductance of the ith and jth supernodes, and the value is the negative value of the admittance sum of all branches connecting the ith and jth supernodes, wherein j is not equal to i.

In a super node, one of the nodes will be selected as a reference point, such as nodes 1 and 2 in FIG. 10, and the other nodes will be selected as non-reference points, such as nodes 1 'and 2' in FIG. 11.

The external circuit of fig. 10 comprises a circuit with three ideal voltage source branches, and nodes (1,3) form a supernode, and nodes (2,7) also form a supernode. The supernodes are identified in the external circuit of fig. 11, where (1,1') corresponds to nodes (1,3) in fig. 10 and (2,2') corresponds to nodes (2,7) in fig. 10.

The super node voltage refers to the voltage of a reference point corresponding to the super node, and the self conductance, mutual conductance and current of the super node are the sum of the self conductance, mutual conductance and current of all nodes contained in the super node. After the formula (7) is rewritten by adopting a super-node method, the following external circuit equation is obtained:

G_supU_sup＝I_sup-G_mulU_nonrefequation (8);

in equation (8), U_supIs the voltage vector of the supernode; g_supAn admittance matrix for the supernode, the matrix being positively symmetric; i is_supA current vector of a supernode; u shape_nonrefIs a voltage vector of a non-reference node with a length of n_nonref，n_nonrefThe number of all non-reference nodes is counted; g_mulA transconductance matrix of a supernode and a non-reference node of size n × n_nonrefAnd n is the number of supernodes.

Suppose all supernodes are numbered 1,2, …, n, and the non-reference nodes are numbered 1,2, …, n_nonrefMatrix U_nonrefAnd G_mulCan be formed according to the following rules: matrix U_nonrefIs the potential of the non-reference node i to its reference node, which is the algebraic sum of the voltages of all the ideal voltage source branches on the path from the non-reference node to its reference node. Matrix G_mulThe rows of (1) correspond to supernodes, the columns correspond to non-reference points, G_i,jAnd if the non-reference point j belongs to the super node i, the mutual conductance is the self-conductance of the non-reference point j, and the value is positive, otherwise, the value is negative.

Before calculating the matrix, the supernodes and the non-reference points need to be numbered again. The renumbering means that one node is selected as a reference node of each super node, other nodes are non-reference nodes of the super node, the nodes are numbered continuously for all reference nodes, the number is the number of the super nodes, the nodes are numbered continuously for all non-reference nodes, and the number is the number of the non-reference nodes. Taking the model shown in fig. 10 as an example, the non-reference points in the graph are labeled 1',2', the supernodes are renumbered to 1,2, …,5, and the renumbering results of the supernodes and the non-reference points are shown in fig. 11. In the figure, there are 2 super nodes and 2 non-reference points in the model, and the matrix corresponding to equation (8) is as follows:

the matrix (9) is:

the matrix (10) is:

the matrix (11) is:

the matrix (12) is:

this results in a symmetrical positive external circuit equation set.

As a possible implementation manner, the combining the frequency domain field equation set and the external circuit equation set by means of scanning the super node in step 630 to establish a symmetric positive definite equation set of parallel flat-plate field-circuit coupling includes:

and 631, scanning all the super nodes and changing the related grid node numbers according to the grid node and external circuit super node numbers independently generated by the third parallel sub-particles, and regenerating the unified continuous node numbers after the scanning is finished.

And 632, combining a frequency domain field equation set corresponding to the third parallel sub-particles and the external circuit equation set according to the unified continuous node numbers to form a field-path coupled and symmetrical and positive unified equation set.

In step 630And merging the equation sets by scanning the super nodes, finishing scanning if all the super nodes are scanned completely, and finally collecting scanning results for merging. Assume that there is N in the external circuit_CA super node having N in the finite element mesh_DA node common to both has N_CDThat is to say with N_CDIf each grid node is connected with a circuit node, the total unknown quantity after combination is known to be N_C+N_D-N_CDNodes are renumbered prior to field-line coupling.

Continuing with the above assumption as an example, since there is N_CThe number of each super node and the number of each grid node are added with N on the original basis_C. For a supernode i, the grid nodes are searched for based on all nodes j (reference nodes and non-reference nodes) it includes. If a mesh node k is connected to circuit node j, the mesh node k is renumbered as j, while the number of the last mesh node is changed to k. After all circuit nodes are scanned, the last grid node is numbered to N_C+N_D-N_CD。

As shown in fig. 12, in which there are 16 mesh nodes, the external circuit employs the model shown in fig. 10, and mesh nodes 1,3,4 are connected to circuit nodes 6,7,5, respectively. Fig. 13 shows the result after the modification of the external circuit node to a supernode and the renumbering of the mesh nodes, in order to merge the circuit nodes and mesh nodes in fig. 13, the mesh nodes 8,9,6 in fig. 13 are renumbered as 2',4 and 5, respectively, in fig. 14, while the mesh nodes 21,20,19 in fig. 13 are renumbered as 8,9,6, respectively, in fig. 14. Finally, the total number of unknowns after combination is 5+ 16-3-18, and the unknowns are the potential of the supernode and the potential of the grid node in the circuit. Fig. 14 is a diagram illustrating the numbering of the external circuit-field and its coupled nodes in this embodiment, which shows the final numbering of the nodes.

Depending on the renumbered node number, the voltage vector may be constructed as follows:

the front portion of the voltage vector is the circuit supernode voltage and the back portion is the voltage of the grid node that is not connected to the external circuit node. Form a matrix G_supRear, superThe numbering of the nodes is not changed any more, so the matrix G_supCan be directly filled in the same position of the sparse matrix. However, the finite element stiffness matrix obtained by solving the equation processing according to the field needs to be written into the corresponding position of the sparse matrix according to the renumbering of the nodes. Because the new node number arranges the external circuit node in front, firstly, the right end item corresponding to the finite element stiffness matrix of the finite element equation set is filled in the corresponding position to form the modified right end item, and then, the right end item of the external circuit is directly merged in front of the modified right end item, and the position of the right end item corresponds to the node number of the external circuit. So that the whole field coupling process is completed.

As a possible implementation, the first parallel sub-particle in step 400 may include a plurality of first parallel small particles, and the plurality of first parallel small particles may perform alignment and simplification processes on a plurality of polygons simultaneously; memory is shared between the calculation of the first parallel small particles.

As a possible implementation manner, in step 700, each of the parallel coarse particles may independently perform a plurality of computation tasks corresponding to a plurality of frequency points, and a plurality of the parallel coarse particles may independently perform computation on a large number of frequency points.

As a possible implementation, the determining parallel sub-grains according to the ratio of the weighted CPU time sum to the total CPU time includes:

As a possible implementation, the parallel computation of each of the computation subtasks shares a memory.

By adopting the method, data can be shared among the parallel computations of the computing sub-tasks, the parallel computations of a vital larger process of a processing part can be accelerated, and the memory can be more fully utilized.

Referring to fig. 15, an embodiment of the present application provides an integrated circuit electromagnetic response calculating apparatus based on a multilevel parallel strategy, the apparatus mainly includes:

By adopting the device, the calculation efficiency of each part in the calculation of the electromagnetic response characteristics of frequency points by the frequency domain simulation of the multilayer super-large-scale integrated circuit can be improved, the parallel calculation efficiency of the electromagnetic response characteristics of the integrated circuits with larger number of different frequency points can be improved, and the high-efficiency calculation requirement can be met.

The foregoing is considered as illustrative of the preferred embodiments of the invention and the technical principles employed. It will be understood by those skilled in the art that the present application is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the application. Therefore, although the present application has been described in more detail with reference to the above embodiments, the present application is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present application, and the scope of the present application is determined by the scope of the appended claims.

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