阅读说明：本技术 减缓存储器子系统中存储器单元的电压状况 (Mitigating voltage conditions of memory cells in a memory subsystem ) 是由 K·K·姆奇尔拉 V·P·拉亚普鲁 P·费利 S·K·瑞特南 S·帕塔萨拉蒂 林其松 S 于 2019-02-01 设计创作，主要内容包括：可以识别已对紧邻存储器组件的特定存储器单元的一或多个存储器单元执行的操作的数量。可以基于操作的所识别数量来关于所述特定存储器单元是否已从与降低的错误率相关联的状态转变到与增加的错误率相关联的另一种状态作出确定。响应于确定所述特定存储器单元已从与所述降低的错误率相关联的所述状态转变到与所述增加的错误率相关联的所述另一种状态,可以对所述特定存储器单元执行操作以将所述特定存储器单元从与所述增加的错误率相关联的所述另一种状态转变到与所述降低的错误率相关联的所述状态。(The number of operations that have been performed on one or more memory cells that are immediately adjacent to a particular memory cell of the memory component may be identified. A determination may be made as to whether the particular memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate based on the identified number of operations. In response to determining that the particular memory cell has transitioned from the state associated with the reduced error rate to the another state associated with the increased error rate, an operation may be performed on the particular memory cell to transition the particular memory cell from the another state associated with the increased error rate to the state associated with the reduced error rate.)

1. A system, comprising:

a memory component; and

a processing device operatively coupled with the memory component, the processing device to:

determining, based on a number of operations that have been performed on one or more memory cells immediately adjacent to a particular memory cell of the memory component, whether the particular memory cell has transitioned from a state associated with a first error rate to another state associated with a second error rate, the second error rate corresponding to a higher number of errors than the first error rate; and is

In response to determining that the particular memory cell has transitioned from the state associated with the first error rate to the another state associated with the second error rate, performing an operation on the particular memory cell to transition the particular memory cell from the another state associated with the second error rate to the state associated with the first error rate.

2. The system of claim 1, wherein the state associated with the first error rate corresponds to a transient threshold voltage state of the particular memory cell and the other state associated with the second error rate corresponds to a stable threshold voltage state of the particular memory cell, and wherein data stored at the particular memory cell is retrieved with fewer errors when the particular memory cell is in the transient threshold voltage state than when the particular memory cell is in the stable threshold voltage state.

3. The system of claim 1, wherein to determine whether the particular memory cell has transitioned from the state associated with a first error rate to another state associated with the second error rate based on the number of operations, the processing device is further to:

determining whether the number of operations that have been performed on the one or more memory cells equals or exceeds a threshold number of operations, wherein it is determined that the particular memory cell has transitioned to the other state associated with the second error rate when the identified number of operations equals or exceeds the threshold number of operations.

4. The system of claim 1, wherein the operation is a read operation or application of a voltage.

5. The system of claim 1, wherein the processing device is further to:

identifying that a first programming operation has been performed on the particular memory cell and that a second programming operation has not been performed on the particular memory cell, wherein performing the operation on the particular memory cell is further in response to performing the first programming operation on the particular memory cell and that the second programming operation has not been performed on the particular memory cell.

6. The system of claim 1, wherein the one or more memory cells immediately adjacent to the particular memory cell are located on a same wordline as the particular memory cell, wherein the one or more memory cells immediately adjacent to the particular memory cell correspond to a block of data at a same plane that includes another block of data of the particular memory cell.

7. The system of claim 1, wherein the operation that has been performed on the one or more memory cells is a write operation or an erase operation.

8. A method, comprising:

determining that a program operation has been performed on a memory cell;

identifying an amount of time that has elapsed since the programming operation was performed on the memory cell;

determining whether the elapsed amount of time satisfies a threshold time condition; and

in response to determining that the elapsed amount of time satisfies the threshold time condition, performing, by a processing device, an operation on the memory cell to change or maintain a voltage condition of the memory cell.

9. The method of claim 8, wherein the operation for the memory cell to change or maintain the voltage condition of the memory cell corresponds to changing the memory cell from a state associated with an increased error rate to another state associated with a decreased error rate or maintaining the memory cell in the another state associated with the decreased error rate.

10. The method of claim 9, wherein the state associated with the increased error rate is a stable threshold voltage state of the memory cell, and wherein the other state associated with the decreased error rate is a transient threshold voltage state of the memory cell.

11. The method of claim 8, further comprising:

determining that a second programming operation has not been performed on the memory cell, wherein performing the operation on the memory cell to change or maintain the voltage condition of the memory cell is further in response to determining that the second programming operation has not been performed on the memory cell.

12. The method of claim 8, wherein the threshold time condition is satisfied by the elapsed amount of time when the amount of time equals or exceeds a threshold amount of time.

13. The method of claim 8, further comprising:

determining not to perform the operation on the memory cell to change or maintain the voltage condition of the memory cell in response to determining that the elapsed amount of time does not satisfy the threshold time condition.

14. The method of claim 8, wherein the programming operation stores data at the memory cell, and wherein the identified amount of elapsed time corresponds to an elapsed time since the data was stored at the memory cell without performing subsequent programming and read operations at the memory cell.

15. A non-transitory computer-readable medium comprising instructions that, when executed by a processing device, cause the processing device to:

determining whether the memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate;

receiving a read offset corresponding to the another state associated with the increased error rate; and is

In response to determining that the memory cell has transitioned from the state associated with the reduced error rate to the another state associated with the increased error rate, performing a read operation on the memory cell based on the read offset corresponding to the another state associated with the increased error rate.

16. The non-transitory computer-readable medium of claim 15, wherein the state associated with the reduced error rate corresponds to a transient threshold voltage state of the memory cell and the other state associated with the increased error rate corresponds to a stable threshold voltage state of the memory cell, and wherein data stored at the memory cell is retrieved with fewer errors when the memory cell is in the transient threshold voltage state than when the memory cell is in the stable threshold voltage state.

17. The non-transitory computer-readable medium of claim 15, wherein the read offset specifies a threshold voltage for application to the memory cell when performing the read operation to retrieve data stored at the memory cell.

18. The non-transitory computer-readable medium of claim 15, wherein the operations further comprise:

in response to determining that the memory cell has not transitioned from the state associated with the reduced error rate to the another state associated with the increased error rate, performing the read operation on the memory cell without the read offset.

19. The non-transitory computer-readable medium of claim 18, wherein the read operation without the read offset and the read operation based on the read offset specify different threshold voltages for application to the memory cell when performing the read operation.

20. The non-transitory computer-readable medium of claim 15, wherein determining whether the memory cell has transitioned is based on a number of operations performed on other memory cells or an amount of time elapsed since a programming operation was performed on the memory cell.

21. A method, comprising:

determining, based on a number of operations that have been performed on one or more memory cells immediately adjacent to a particular memory cell of a memory component, whether the particular memory cell has transitioned from a state associated with a first error rate to another state associated with a second error rate, the second error rate corresponding to a higher number of errors than the first error rate; and

in response to determining that the particular memory cell has transitioned from the state associated with the first error rate to the another state associated with the second error rate, performing, by a processing device, an operation on the particular memory cell to transition the particular memory cell from the another state associated with the second error rate to the state associated with the first error rate.

22. The method of claim 21, wherein the state associated with the first error rate corresponds to a transient threshold voltage state of the particular memory cell and the other state associated with the second error rate corresponds to a stable threshold voltage state of the particular memory cell, and wherein data stored at the particular memory cell is retrieved with fewer errors when the particular memory cell is in the transient threshold voltage state than when the particular memory cell is in the stable threshold voltage state.

23. The method of claim 21, wherein determining whether the particular memory cell has transitioned from the state associated with a first error rate to another state associated with the second error rate based on the number of operations comprises:

determining whether the number of operations that have been performed on the one or more memory cells equals or exceeds a threshold number of operations, wherein it is determined that the particular memory cell has transitioned to the other state associated with the second error rate when the identified number of operations equals or exceeds the threshold number of operations.

Technical Field

The present disclosure relates generally to a memory subsystem and, more particularly, to mitigating voltage conditions of memory cells in a memory subsystem.

Background

The memory subsystem may be a storage system, such as a Solid State Drive (SSD), and may include one or more memory components that store data. The memory components may be, for example, non-volatile memory components and volatile memory components. In general, a host system may utilize a memory subsystem to store data at and retrieve data from memory components.

Drawings

The present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure.

FIG. 1 illustrates an example computing environment including a memory subsystem in accordance with some embodiments of the present disclosure.

FIG. 2 is a flow diagram of an example method for performing an operation on a memory cell to change a voltage condition of the memory cell in accordance with some embodiments of the present disclosure.

FIG. 3 shows voltage conditions or states of memory cells in accordance with some embodiments of the present disclosure.

FIG. 4 is a flow diagram of an example method for determining whether to perform an operation on a memory cell to change a voltage condition based on other memory cells, in accordance with some embodiments of the present disclosure.

FIG. 5A shows operations for immediately adjacent memory cells that change the voltage condition of a particular memory cell, in accordance with some embodiments of the present disclosure.

FIG. 5B shows an operation for an immediately adjacent memory cell that changes the voltage condition of a particular memory cell such that the voltage condition is to be mitigated, in accordance with some embodiments of the present disclosure.

FIG. 6 is a flow diagram of an example method for determining whether to perform an operation on a memory cell to change a voltage condition based on an elapsed time in accordance with some embodiments of the present disclosure.

FIG. 7 is a flow diagram of an example method for mitigating voltage conditions of a memory cell based on a read offset in accordance with some embodiments of the present disclosure.

Fig. 8 is a block diagram of an example computer system in which embodiments of the present disclosure may operate.

Detailed Description

Aspects of the present disclosure relate to mitigating voltage conditions of memory cells in a memory subsystem. The memory subsystem is also referred to hereinafter as a "memory device". An example of a memory subsystem is a storage system such as a Solid State Drive (SSD). In some embodiments, the memory subsystem is a hybrid memory/storage subsystem. In general, a host system may utilize a memory subsystem that includes one or more memory components. The host system may provide data to be stored in the memory subsystem and may request that the data be retrieved from the memory subsystem.

Each memory component may include a plurality of memory cells, where each memory cell may store one or more bits of binary data corresponding to data received from a host system. Conventional memory subsystems may store data at a particular memory cell by performing two programming passes (or any number of programming passes) that each program or store data at the memory cell. For example, a first programming pass may program data at a memory cell at a particular time. At a later time, a second programming pass may be performed on the memory cells to store additional data at the memory cells, and the second programming pass requires and uses the information stored in the first programming pass. A certain time may pass between the memory subsystem performing the first programming pass and performing the second programming pass on the same memory cells.

The state or condition of the memory cells may change during an amount of time that has elapsed between the memory subsystem performing the first programming pass and the second programming pass on the memory cells. For example, after performing a programming operation on the memory cells using a first programming pass, the memory cells may be in an initial voltage condition. The initial voltage condition corresponds to an instantaneous threshold voltage (V)_t) Status. In some embodiments, the transient V_tThe state may be a physical state of the memory cell, where electrons of the memory cell are distributed throughout the memory cell. After the first programming pass has been performed and a certain amount of time has passed without other operations being performed on the memory cell, the memory cell may transition from an initial voltage condition or state to another voltage condition or state. For example, the memory cell may transition to a stable threshold voltage (V)_t) State of said stable V_tThe state corresponds to another physical state of the memory cell in which electrons of the memory cell are not distributed throughout the memory cell. Instead, the electrons may be distributed towards the edges or outside of the memory cell.

Memory sheetThe voltage condition of the cell being from the instant V_tState to steady V_tThe change in state may result in the data stored in the memory cells by the first programming pass being erroneously read or retrieved when the second programming pass is performed. For example, data programmed to the memory cells by the first programming pass will subsequently be read from the memory cells and used to store additional data at the memory cells during the second programming pass. However, if after performing the first programming pass on the memory cell and before performing the second programming pass on the memory cell, the memory cell has been programmed from the transient V_tState transition to stable V_tStatus, then errors in the data read from the memory cells may be more frequent. Thus, the instant V_tThe state may correspond to a state of the memory cell in which a stable V when compared to a stable V that is possible to read or retrieve data stored at the memory cell at an increased error rate_tThe data stored at the memory cells can be read or retrieved at a reduced error rate compared to the state. Thus, in conventional memory subsystems, the increased use of error detection and correction operations (i.e., error control operations) should be performed to correct errors in the data before additional data is programmed to the memory cells as part of the second programming pass. The increased use of error control operations may result in a performance degradation of the conventional memory subsystem because fewer read and write operations may be performed from the host system while the memory subsystem is performing additional error control operations.

Furthermore, in other conventional memory systems, if an error control operation is not performed on data stored due to the first programming pass before performing the second programming pass, the data may contain a large number of bit errors if the corresponding memory cells are in a stable Vt state, resulting in a write error of the data. Such write errors may reduce the correction capability of error correction operations that use soft (i.e., reliability) information associated with the data.

Aspects of the present disclosure address the above sum by mitigating voltage conditions of memory cells at a memory subsystemOther disadvantages. For example, an operation (i.e., a read operation) may be performed on the memory cell between performing a first programming pass on the memory cell and performing a second programming pass on the memory cell to begin the memory cell from a stable V_tState to instantaneous V_tA transition of state. Thus, when the memory cell is at the instant V_tA second programming pass may then be performed when the state is and associated with a reduced error rate.

In some embodiments, the performance of the operation to transition the state of the particular memory cell may be based on other programming passes or operations that have been performed on other memory cells immediately adjacent to the particular memory cell. For example, a first programming pass may be performed to store data at a particular memory cell, and then other programming passes or operations (e.g., write operations or erase operations) may be performed on other memory cells that are located immediately adjacent to the particular memory cell. Such operations performed on other memory cells may affect the memory cells from the transient V_tState transition to stable V_tStatus. For example, a write operation performed on adjacent or immediately adjacent memory cells (e.g., other memory cells on the same plane or die of a particular memory cell) may facilitate the particular memory cell from a transient V_tState transition to stable V_tStatus. As more operations are performed on immediately adjacent memory cells, then a particular memory cell may transition to a stable V more quickly_tStatus. In some embodiments, after a threshold number of program and erase operations are performed on immediately adjacent memory cells, a read operation may be performed on a particular memory cell. Thus, a read operation may initiate a particular memory cell from a stable V_tState to instantaneous V_tA transition of state. In the same or alternative embodiments, a read operation may be performed on a particular memory cell if a threshold amount of time has elapsed since a first programming pass was performed on the particular memory cell and before any second programming pass was performed on the particular memory cell.

Advantages of the present disclosure include, but are not limited to, increased performance of the memory subsystem because when writing data to storageFewer error control operations are performed while the machine subsystem is in operation. For example, when the memory cell is at the instant V at which data stored at the memory cell due to the first programming pass can be read with fewer errors_tIn state, a second programming pass may be performed on the memory cells. In addition, then since the memory cell is at the instant V_tPerforming a second programming pass on the memory cell while in state may improve the reliability of the data stored at the memory cell.

FIG. 1 illustrates an example computing environment 100 including a memory subsystem 110 in accordance with some embodiments of the present disclosure. Memory subsystem 110 may contain media, such as memory components 112A through 112N. The memory components 112A-112N may be volatile memory components, non-volatile memory components, or a combination thereof. In some embodiments, the memory subsystem is a storage system. An example of a storage system is an SSD. In some embodiments, memory subsystem 110 is a hybrid memory/storage subsystem. In general, the computing environment 100 may contain a host system 120 that uses a memory subsystem 110. For example, the host system 120 may write data to the memory subsystem 110 and read data from the memory subsystem 110.

The host system 120 may be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, or such computing devices that include memory and processing devices. The host system 120 may contain or be coupled to the memory subsystem 110 such that the host system 120 may read data from or write data to the memory subsystem 110. The host system 120 may be coupled to the memory subsystem 110 through a physical host interface. As used herein, "coupled to" generally refers to a connection between components that may be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, and the like. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, peripheral component interconnect express (PCIe) interfaces, Universal Serial Bus (USB) interfaces, fibre channel, serial attached scsi (sas), and the like. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled with the host system 120 over a PCIe interface, the host system 120 may further utilize an NVM Express (NVMe) interface to access the memory components 112A-112N. The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120.

The memory components 112A-112N may include any combination of different types of non-volatile memory components and/or volatile memory components. Examples of non-volatile memory components include NAND (NAND) type flash memory. Each of memory components 112A-112N may include one or more arrays of memory cells, such as Single Level Cells (SLC) or multi-level cells (MLC) (e.g., Triple Level Cells (TLC) or Quad Level Cells (QLC)). In some embodiments, a particular memory component may include both SLC and MLC portions of a memory cell. Each of the memory cells may store one or more bits of data (e.g., a block of data) used by the host system 120. Although non-volatile memory components such as NAND type flash memory are described, the memory components 112A through 112N may be based on any other type of memory such as volatile memory. In some embodiments, memory components 112A-112N may be, but are not limited to, Random Access Memory (RAM), Read Only Memory (ROM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Phase Change Memory (PCM), Magnetic Random Access Memory (MRAM), NOR (NOR) flash memory, Electrically Erasable Programmable Read Only Memory (EEPROM), and cross-point arrays of non-volatile memory cells. A cross-point array of non-volatile memory in combination with a stackable cross-grid data access array may perform bit storage based on changes in body resistance. In addition, in contrast to many flash-based memories, cross-point non-volatile memories may perform write-in-place (in-place) operations in which non-volatile memory cells may be programmed without prior erasing of the non-volatile memory cells. Further, the memory cells of memory components 112A through 112N may be grouped into memory pages or data blocks, which may refer to the cells of the memory components used to store data.

A memory system controller 115 (hereinafter referred to as a "controller") may communicate with the memory components 112A-112N to perform operations such as reading data, writing data, or erasing data at the memory components 112A-112N, as well as other such operations. The controller 115 may include hardware, such as one or more integrated circuits and/or discrete components, a buffer memory, or a combination thereof. The controller 115 may be a microcontroller, special purpose logic circuitry (e.g., a Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), etc.), or other suitable processor. The controller 115 may include a processor (processing device) 117 configured to execute instructions stored in a local memory 119. In the example shown, the local memory 119 of the controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120. In some embodiments, local memory 119 may include memory registers that store memory pointers, acquired data, and the like. The local memory 119 may also include a Read Only Memory (ROM) for storing microcode. Although the example memory subsystem 110 in fig. 1 is shown to contain the controller 115, in another embodiment of the present disclosure, the memory subsystem 110 may not contain the controller 115, but may rely on external control (e.g., provided by an external host or a processor or controller separate from the memory subsystem).

In general, the controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory components 112A-112N. The controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and Error Correction Code (ECC) operations, encryption operations, cache operations, and address translation between logical and physical block addresses associated with the memory components 112A-112N. The controller 115 may further include host interface circuitry to communicate with the host system 120 through a physical host interface. Host interface circuitry may convert commands received from the host system into command instructions to access memory components 112A-112N and convert responses associated with memory components 112A-112N into information for host system 120.

Memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that may receive addresses from controller 115 and decode the addresses to access memory components 112A-112N.

Memory subsystem 110 can include voltage condition component 113 (e.g., circuitry, dedicated logic, programmable logic, firmware, etc.) to perform operations on memory cells to change the voltage conditions of the memory cells. In some embodiments, the controller 115 includes at least a portion of the voltage condition component 113. For example, the controller 115 may include a processor 117 (processing device) configured to execute instructions stored in the local memory 119 for performing the operations described herein. In some embodiments, the voltage condition component 113 is part of the host system 110, an application, or an operating system.

In some embodiments, voltage condition component 113 can perform operations on memory cells at memory components 112A-112N to bring the memory cells from a state of increased error rate (e.g., stable V)_tState) to another state of reduced error rate (e.g., instantaneous V)_tStatus). Further details regarding the operation of the voltage condition component 113 are described below.

FIG. 2 is a flow diagram of an example method for performing an operation on a memory cell to change a voltage condition of the memory cell in accordance with some embodiments of the present disclosure. Method 200 may be performed by processing logic that may comprise hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 200 is performed by the voltage condition component 113 of FIG. 1. Although shown in a particular sequence or order, the order of the processes may be modified unless otherwise specified. Thus, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

As shown in FIG. 2, at block 210, processing logic identifies that a programming operation has been performed on the memory cells. In some embodiments, a program operation is performed on a block of data that includes a set of memory cells. As such, the operations described herein may be performed on a block of data (e.g., a group of memory cells) and/or individual memory cells. For example, the operations described in this disclosure with respect to memory cells may also be used with blocks of data as a group of memory cells. The programming operation may be performed as part of a first programming pass that programs data at memory cells of memory components in the memory subsystem. The first programming pass may be part of a two-pass programming operation that includes a second programming pass that programs additional data at the memory cells after the first programming pass is performed on the memory cells. At block 220, processing logic identifies that a subsequent programming operation has not been performed on the memory cells. For example, the memory subsystem may identify that a second programming pass has not been performed on the memory cells (e.g., a certain time has elapsed since the first programming pass). At block 230, processing logic determines that the voltage condition of the memory cell has changed. For example, the voltage condition may correspond to whether the memory cell has gone from a transient V_tChange of state to a stable V_tStatus. For example, the memory subsystem may identify whether a threshold number of program/erase operations have been performed at other memory cells immediately adjacent to the memory cell.With respect to FIGS. 4, 5A, and 5B, discussion is made with respect to determining whether a voltage condition of a memory cell has changed (e.g., from an instantaneous V) based on performing a threshold number of operations at an immediately adjacent memory cell_tState to steady V_tStatus). In the same or alternative embodiments, the memory subsystem may identify that the voltage condition of the memory cell has changed based on a threshold amount of time elapsing since the first programming pass was performed on the memory cell. Further details regarding determining whether the voltage condition of the memory cell has changed based on the passage of a threshold amount of time are described with respect to FIG. 6. In some embodiments, the memory subsystem may infer or assume that the voltage condition of a memory cell has changed based on performing a threshold number of operations at an immediately adjacent memory cell and/or a threshold amount of time elapsing from performing a first programming pass on the memory cell.

At block 240, when the voltage condition of the memory cell has changed, processing logic performs an operation on the memory cell to restore the voltage condition of the memory cell. For example, when the memory cell has changed to a stable V_tWhile in state, performing an operation on the memory cell may restore the memory cell to a transient V_tStatus. The operation may be, but is not limited to, a read operation performed on the memory cell. In some embodiments, the operation may be the application of a voltage to the memory cell, or any other operation or action that causes a voltage to be applied to the memory cell. At block 250, after performing the operation to restore the voltage condition of the memory cell, processing logic performs a subsequent programming operation on the memory cell. The subsequent programming operation may be for after the memory cell has transitioned back to the transient V_tA second programming pass while in state to store additional data at the memory cell. The second programming pass uses the data stored at the memory cells programmed during the first memory pass.

FIG. 3 shows voltage conditions or states of memory cells in accordance with some embodiments of the present disclosure. In general, the various operations of FIG. 3 may be performed on a memory cell by voltage condition component 113 of FIG. 1.

As shown in fig. 3, may be for the memory cellA first programming operation 310 is performed. For example, as part of a first programming pass, the first programming operation 310 may store data at the memory cells. In some embodiments, the memory cells may store data corresponding to a plurality of memory pages, and the first programming pass may store data corresponding to a portion of a memory page. After the first program operation 310 is performed on the memory cell 320, the memory cell 320 may be in an initial state. For example, when programming data to memory cell 320, memory cell 320 may be at an instantaneous V_tStatus. Over time or other program/erase operations performed on immediately adjacent memory cells, memory cell 320 may be oriented toward a stable V_tThe state advances. Thus, the memory cell may never be in fewer errors (e.g., corresponding to the transient V)_tReduced error rate of states) to a state transition where data stored at a memory cell may be read with more errors (e.g., corresponding to a stable V)_tIncreased error rate of states) read the state of data stored at the memory cell. After memory cell 320 has transitioned to a stable V_tAfter the state, a read operation 330 (or another type of operation that applies a voltage to the memory cell 320) may be performed on the memory cell 320 to slow the memory cell's stable V_tStatus. For example, read operation 330 may restore the instantaneous V of memory cell 320_tStatus. After an amount of time that depends on the temperature of the memory system, memory cell 320 may revert to the transient V_tStatus. In some embodiments, a certain amount of time passes to cause the memory cell to be at the instant V_tAfter state, a second programming pass may be initiated or may begin. After a read operation 330 has been performed on the memory cell 320 to recover the transient V_tState or starting instant V_tAfter the recovery of the state, a second programming operation 340 may be performed on the memory cell 320. Thus, a transient V is restored in memory cell 320_tAfter the state, a second programming operation 340 may be performed on the memory cell 320.

FIG. 4 is a flow diagram of an example method 400 for determining whether to perform an operation on a memory cell to change a voltage condition of the memory cell based on other memory cells, in accordance with some embodiments of the present disclosure. In general, method 400 may be performed by processing logic that may comprise hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. The method 400 may be performed by the voltage condition component 113 of FIG. 1.

As shown in FIG. 4, at block 410, processing logic determines that a programming operation is to be performed on a particular memory cell. The programming operation may be part of a second programming pass. For example, a particular memory cell may store data from a previous programming operation from a first programming pass performed at a previous time and not yet store data from a second programming pass. At block 420, processing logic identifies a number of operations that have been performed on memory cells immediately adjacent to the particular memory cell. Memory cells on the same word line, same plane, and/or same die as a particular memory cell may be considered immediately adjacent to the particular memory cell. In some embodiments, memory cells within a particular distance of a particular memory cell may be considered immediately adjacent to the memory cell. Operations that have been performed on immediately adjacent memory cells may include a program operation (e.g., storage of data) at the immediately adjacent memory cells and/or an erase operation to remove data at the immediately adjacent memory cells. At block 430, processing logic determines whether the number of operations satisfies a threshold number. When the number of operations is equal to or exceeds the threshold number, the number of operations performed on the immediately adjacent memory cells may be considered to satisfy the threshold number (i.e., the threshold condition), and when the number of operations is less than the threshold number, the number of operations may be considered not to satisfy the threshold number. If the number of operations satisfies the threshold number or threshold condition, then at block 440, processing logic performs a read operation on the particular memory cell. For example, a read operation may be performed on a particular memory cell to bring the voltage condition of the particular memory cell from a state of increased error (e.g., a stable V) for data read at the memory cell_tState) to be changed toAnother state of reduced error (e.g., transient V) of the data read at the memory cell_tStatus). At block 450, processing logic performs a programming operation on the particular memory cell. For example, after a read operation is performed on a particular memory cell to change the voltage condition of the particular memory cell, data may be programmed to the particular memory cell.

Referring to FIG. 4, if the number of operations performed on the immediately adjacent memory cells satisfies a threshold number or threshold condition, then at block 460, processing logic determines that a read operation is not to be performed on the particular memory cell. For example, it may be determined not to perform a transition for a particular memory cell to a transient V_tRead operation of state, since it can be assumed that the memory cell is not at stable V_tStatus. In some embodiments, the intent to transition a particular memory cell to transient V may not be performed_tThe read operation of a state is the performance of other read operations from the host system for retrieving data stored at a particular memory cell. At block 470, processing logic performs a programming operation on the particular memory cell. For example, as part of the second programming pass, additional data may be stored at a particular memory cell.

FIG. 5A shows operations of memory cells for immediately adjacent data blocks that change voltage conditions of memory cells in a particular data block, according to some embodiments of the present disclosure. In general, the voltage condition component 113 of FIG. 1 can change the voltage condition of memory cells of a particular data block based on operations that have been performed on immediately adjacent data blocks.

As shown in fig. 5A, data may be stored at a particular data block 550. In some embodiments, a data block includes a set of memory cells. Data blocks 510, 520, 530, 540, 560, 570, 580, and 590 are immediately adjacent to a particular data block cell 550 (e.g., on the same word line, plane, or die). The number of operations performed at the immediately adjacent data blocks may be used to determine whether to perform a read operation on a particular memory data block 550 to restore the voltage condition of the particular data block 550. For example, an operation has been performed on the memory cells of data block 510, and data has been processedThe memory cells of block 560 perform two operations and three operations have been performed on the memory cells of data block 580. Thus, the number of operations performed on the data block immediately adjacent to the particular data block 550 is six operations. Each of the six operations may contribute to the memory cells of a particular data block 550 traveling to a stable V_tStatus. When a threshold number of operations have been performed at the immediate data block, it may be assumed that a particular data block 550 is at a stable V_tStatus. For example, if the threshold number is ten, then six operations that have been performed on immediately adjacent data blocks do not exceed the threshold number of operations. Thus, a particular data block may be considered to be still at the instant V_tStatus.

FIG. 5B illustrates operations for immediately adjacent data blocks that change the voltage condition of a particular data block such that the voltage condition is to be mitigated, in accordance with some embodiments of the present disclosure. In general, the voltage condition component 113 of FIG. 1 can change the voltage condition of a particular data block based on operations that have been performed on immediately adjacent data blocks.

As shown in FIG. 5B, ten operations have been performed on the memory cells of the immediately adjacent data block. Since ten operations are equal to the threshold number, the operations that have been performed on the immediately adjacent data blocks may be considered to change the voltage condition of the memory cells of a particular data block 550 to a stable V_tStatus. Thus, a read operation may be performed on particular data block 550 to move the memory cells of particular data block 550 from a stable V_tState transition to instantaneous V_tStatus. In some embodiments, a read operation may be performed on each memory cell of a particular data block 550.

FIG. 6 is a flow diagram of an example method 600 for determining whether to perform an operation on a memory cell to change a voltage condition based on an elapsed time in accordance with some embodiments of the present disclosure. In general, method 600 may be performed by processing logic that may comprise hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. Method 600 may be performed by voltage condition component 113 of FIG. 1.

As shown in FIG. 6, at block 610, processing logic identifies that a first programming operation has been performed on the memory cells. The first programming operation may be part of a first programming pass that stores data at memory cells of the data block. Further, the processing logic may determine that another programming operation of a second programming pass for storing additional data at the memory cell has not been performed at the memory cell. At block 620, processing logic determines an amount of time that has elapsed since the first programming operation was performed on the memory cell. The amount of time elapsed may correspond to the memory cell having gone from the instant V_tState transition to stable V_tAssumption of state. In the same or alternative embodiments, the amount of time that elapses may correspond to when a read operation should be performed to maintain the memory cells of the data block at the transient V_tStatus. At block 630, processing logic determines whether the amount of time exceeds a threshold amount of time. When the amount of elapsed time exceeds (or is equal to) a threshold amount of time (i.e., a threshold time condition), it may be assumed that the memory cells of the data block have been from the instant V_tState transition to stable V_tStatus. In some embodiments, the threshold amount of time may correspond to an amount of time that a memory subsystem having a memory component containing a block of data has been powered down or not operating. If the amount of time elapsed since the first programming operation was performed on the memory cells of the data block exceeds the threshold amount of time, then at block 640, processing logic performs a read operation on the memory cells to change the voltage condition of the memory cells. The read operation may be an operation performed without a request from a host system to retrieve data stored at the memory cell. At block 650, processing logic performs a second programming operation on the memory cells. For example, after a read operation is performed on the memory cell to change a voltage condition of the memory cell or to maintain the voltage condition of the memory cell, a second program operation may be performed. Conversely, if the amount of time elapsed since the first programming operation was performed on the memory cells does not exceed the threshold amount of time, then at block 660 processing logic determines that a read operation is not to be performed on the memory cells of the data block. Further, at block 670, the pair of processing logicsThe memory cell performs a second program operation.

In some embodiments, a read operation may be performed on each memory cell of the block of data at the memory component of the memory subsystem that is not programmed with the second programming pass. When the memory subsystem has been initialized or re-powered after being powered down or not running for a threshold amount of time, a read operation may be performed on the memory cells.

FIG. 7 is a flow diagram of an example method 700 for mitigating voltage conditions of a memory cell based on a read offset, in accordance with some embodiments of the present disclosure. In general, method 700 may be performed by processing logic that may comprise hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. Method 700 may be performed by voltage condition component 113 of FIG. 1.

Aspects of the present disclosure may mitigate voltage conditions of memory cells by applying a read offset that is used to assume that a transient V has been driven_tChange of state to a stable V_tThe particular memory cell in the state performs a read operation. For example, as described below, the surrogate changes may have transitioned to a stable V_tVoltage condition of memory cell in state when memory cell is considered to have gone from transient V_tState transition to stable V_tIn the state, the read offset value may be used to retrieve data stored at the memory cell.

As shown in FIG. 7, at block 710, processing logic identifies that a programming operation has been performed to store data at the memory cells. For example, a first programming pass may be performed on the memory cells. At block 720, processing logic determines that the memory cell has changed voltage conditions. When the threshold condition is satisfied, it may be determined that the memory cell has been driven from the transient V_tChange of state to a stable V_tStatus. For example, as previously described, when a threshold number of operations have been performed on immediately adjacent memory cells or when a threshold amount of time has elapsed since a programming operation was performed to store data at the memory cells, a threshold amount of time may be elapsedTo satisfy the threshold condition. At block 730, processing logic receives a read offset based on the changed voltage condition. The read offset may specify a particular threshold voltage to apply to read data stored at the memory cell programmed during the first programming pass. For example, when the memory cell is at a transient V_tIn one state, a first threshold voltage can be applied to read data stored at the memory cell, and when the memory cell is at a stable V_tIn the state, a different second threshold voltage based on the read offset may be applied to read data stored at the memory cell.

At block 740, processing logic performs a read operation based on the read offset to retrieve the data at the memory cell. For example, data can be retrieved from a memory cell by applying a threshold voltage to the memory cell defined by the read offset. Thus, by applying and withdrawing at the instant V_tThe memory cells in the state read data with different threshold voltages from being at a stable V_tThe memory cells of the state read the data and a second programming pass can be performed. At block 750, processing logic performs a subsequent programming operation on the memory cells based on the data retrieved from the read operation. For example, a second programming pass may be performed on the memory cells, wherein the additional data stored at the memory cells as a result of the second programming pass is based on values of data of the first programming pass performed on the memory cells at an earlier time.

Fig. 8 illustrates an example machine of a computer system 800 within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 800 may correspond to a host system (e.g., the host system 120 of fig. 1) that includes, is coupled to, or utilizes a memory subsystem (e.g., the memory subsystem 110 of fig. 1) or may be used to perform the operations of a controller (e.g., to execute an operating system to perform operations corresponding to the voltage condition component 113 of fig. 1). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and/or the internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

The machine may be a Personal Computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

The example computer system 800 includes a processing device 802, a main memory 804 (e.g., Read Only Memory (ROM), flash memory, Dynamic Random Access Memory (DRAM) such as synchronous DRAM (sdram) or Rambus DRAM (rdram), etc.), static memory 806 (e.g., flash memory, Static Random Access Memory (SRAM), etc.), and a data storage system 818 that communicate with each other over a bus 830.

The processing device 802 represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, Reduced Instruction Set Computing (RISC) microprocessor, Very Long Instruction Word (VLIW) microprocessor, or processor implementing other instruction sets or processors implementing a combination of instruction sets. The processing device 802 may also be one or more special-purpose processing devices such as an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Digital Signal Processor (DSP), network processor, or the like. The processing device 802 is configured to execute instructions 826 for performing the operations and steps discussed herein. The computer system 800 may further include a network interface device 808 for communicating over a network 820.

The data storage system 818 may include a machine-readable storage medium 824 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 826 or software embodying any one or more of the methodologies or functions described herein. The instructions 826 may also reside, completely or at least partially, within the main memory 804 and/or within the processing device 802 during execution thereof by the computer system 800, the main memory 804 and the processing device 802 also constituting machine-readable storage media. The machine-readable storage media 824, data storage system 818, and/or main memory 804 may correspond to memory subsystem 110 of fig. 1.

In one embodiment, the instructions 826 include instructions for implementing functions corresponding to a voltage condition component (e.g., the voltage condition component 113 of FIG. 1). While the machine-readable storage medium 824 is shown in an example embodiment to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media that store the one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, considered to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may relate to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the required purposes, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), Random Access Memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the disclosure as described herein.

The present disclosure may be provided in the form of a computer program product or software which may include a machine-readable medium having stored thereon instructions which may be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) -readable storage medium, such as a read only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, and so forth.

In the foregoing specification, embodiments of the disclosure have been described with reference to specific exemplary embodiments thereof. It will be evident that various modifications may be made thereto without departing from the broader spirit and scope of embodiments of the disclosure as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.