阅读说明：本技术 一种存储设备 (Storage device ) 是由 李旺 于 2020-07-17 设计创作，主要内容包括：本发明公开了一种存储设备,本申请在内存颗粒模块的预设位置设置了振荡消除电路,其可以消除处理器输出的时钟信号中的振荡,如此一来,即使处理器输出的时钟信号的频率较高,内存颗粒模块也能够稳定地进行数据处理,保证了高频率下的数据处理的可靠性,可以大幅度地提高数据处理效率,促进了存储设备的发展。(The invention discloses a storage device, which is characterized in that an oscillation elimination circuit is arranged at a preset position of a memory particle module and can eliminate oscillation in a clock signal output by a processor, so that the memory particle module can stably process data even if the frequency of the clock signal output by the processor is higher, the reliability of data processing under high frequency is ensured, the data processing efficiency can be greatly improved, and the development of the storage device is promoted.)

1. A storage device, comprising:

the processor is used for outputting a clock signal with a preset frequency and a data processing instruction;

the memory particle module is used for processing the data specified by the data processing instruction according to the clock signal;

and the oscillation elimination circuit is arranged at the preset position of the memory grain module and is used for eliminating the oscillation in the clock signal.

2. The memory device of claim 1, wherein the predetermined location is a location between the memory granule module and a clock signal output of the processor.

3. The memory device of claim 2, wherein the oscillation cancellation circuit is a filter circuit.

4. The memory device of claim 3, wherein the filter circuit is a capacitor connected in parallel with a clock signal output of the processor.

5. The memory device of claim 1, wherein the processor is a CPU.

6. The memory device of claim 1, wherein the memory grains in the memory grain module are Double Data Rate (DDR) 4 memory grains.

7. The storage device of any one of claims 1 to 6, further comprising:

and the signal waveform prompting circuit is arranged in the memory particle module and is used for acquiring and prompting the waveform of the clock signal received by each memory particle in the memory particle module.

8. The memory device according to claim 7, wherein the signal waveform prompting circuit comprises an oscilloscope disposed at a clock signal input of each of the memory grains in the memory grain module;

the oscilloscopes correspond to the memory particles one to one.

Technical Field

The invention relates to the field of data storage, in particular to a storage device.

Background

The memory device is widely used in various industries and generally comprises a processor and a memory granule module, wherein the memory granule module can perform data processing according to a clock signal and a data processing instruction output by the processor, and the higher the frequency of the clock signal is, the faster the data processing speed is, but in general, the higher the frequency of the clock signal output by the processor is, the larger the oscillation of the clock signal is, and the more error is prone to occurring in the data processing process, so in order to ensure the reliability of the data processing process, in the prior art, the frequency of the clock signal output by the processor is usually set to a lower level, for example 667MHz, in which case the efficiency of data processing is also lower, and the development of the memory device is limited.

Therefore, how to provide a solution to the above technical problem is a problem that needs to be solved by those skilled in the art.

Disclosure of Invention

The invention aims to provide a storage device, which ensures the reliability of data processing at high frequency, can greatly improve the data processing efficiency and promotes the development of the storage device.

To solve the above technical problem, the present invention provides a storage device, including:

the processor is used for outputting a clock signal with a preset frequency and a data processing instruction;

the memory particle module is used for processing the data specified by the data processing instruction according to the clock signal;

and the oscillation elimination circuit is arranged at the preset position of the memory grain module and is used for eliminating the oscillation in the clock signal.

Preferably, the preset position is a position between the memory granule module and a clock signal output end of the processor.

Preferably, the oscillation elimination circuit is a filter circuit.

Preferably, the filter circuit is a capacitor connected in parallel to a clock signal output terminal of the processor.

Preferably, the processor is a CPU.

Preferably, the memory granules in the memory granule module are double data rate DDR4 memory granules.

Preferably, the storage device further comprises:

and the signal waveform prompting circuit is arranged in the memory particle module and is used for acquiring and prompting the waveform of the clock signal received by each memory particle in the memory particle module.

Preferably, the signal waveform prompting circuit includes an oscilloscope disposed at a clock signal input end of each memory particle in the memory particle module;

the oscilloscopes correspond to the memory particles one to one.

The invention provides a storage device, which is characterized in that an oscillation elimination circuit is arranged at a preset position of a memory particle module, and the oscillation elimination circuit can eliminate oscillation in a clock signal output by a processor, so that the memory particle module can stably process data even if the frequency of the clock signal output by the processor is higher, the reliability of data processing under high frequency is ensured, the data processing efficiency can be greatly improved, and the development of the storage device is promoted.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed in the prior art and the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

FIG. 1 is a schematic structural diagram of a storage device according to the present invention;

fig. 2 is a schematic structural diagram of another storage device provided in the present invention.

Detailed Description

The core of the invention is to provide a storage device, which ensures the reliability of data processing under high frequency, can greatly improve the data processing efficiency and promotes the development of the storage device.

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a storage device provided in the present invention, where the storage device includes:

the processor 1 is used for outputting a clock signal with a preset frequency and a data processing instruction;

the memory grain module 2 is used for processing data specified by the data processing instruction according to the clock signal;

and the oscillation elimination circuit 3 is arranged at a preset position of the memory grain module 2 and is used for eliminating oscillation in the clock signal.

Specifically, in view of the technical problems in the background art, in the embodiment of the present invention, the oscillation eliminating circuit 3 is disposed at the preset position of the memory granule module 2, and because the oscillation eliminating circuit 3 can eliminate the oscillation part in the clock signal to a certain extent, so that the clock signal can maintain a standard stable waveform, in this case, a worker can set a higher preset frequency, and some oscillations exist in the clock signal with the higher preset frequency in time, but the oscillation eliminating circuit 3 can eliminate the oscillations of the part, thereby ensuring the standard and stable waveform of the clock signal, so that the memory granule module 2 can perform fast and efficient data processing according to the clock signal with the higher preset frequency, and greatly improving the data processing efficiency.

The oscillation eliminating circuit 3 can ensure that the clock signal received by the memory grain module 2 does not have too strong oscillation, so that stable data processing work can be performed.

The preset frequency can be set autonomously, and since the oscillation eliminating circuit 3 in the present application can eliminate the oscillation part in the clock signal, even if a higher preset frequency is set, the oscillation of the clock signal with the higher preset frequency can be eliminated by the oscillation eliminating circuit 3, and certainly, the preset frequency cannot be set arbitrarily without limitation, and can be set autonomously by a worker, which is not limited herein.

Specifically, the data processing instruction may be of various types, for example, the data processing instruction may include a read data instruction or a write data instruction, the data stored in the memory granule module 2 may be read through the read data instruction, and the specified data may be written into the memory granule module 2 through the write data instruction, which is not limited in this embodiment of the present invention.

The invention provides a storage device, which is characterized in that an oscillation elimination circuit is arranged at a preset position of a memory particle module, and the oscillation elimination circuit can eliminate oscillation in a clock signal output by a processor, so that the memory particle module can stably process data even if the frequency of the clock signal output by the processor is higher, the reliability of data processing under high frequency is ensured, the data processing efficiency can be greatly improved, and the development of the storage device is promoted.

On the basis of the above-described embodiment:

as a preferred embodiment, the predetermined position is a position between the memory granule module 2 and the clock signal output terminal of the processor 1.

Specifically, considering that the memory granule module 2 usually has a plurality of memory granules (the topology structure of the plurality of memory granules may be various, for example, a daisy chain topology, etc., the embodiment of the present invention is not limited herein), specific experiments show that the oscillation elimination circuit 3 disposed at different positions in the memory granule module 2 will generate different oscillation elimination effects, in order to ensure that each memory granule can receive a clock signal with a standard stable waveform, researchers have previously performed simulation experiments of various topology structures to verify that when the oscillation elimination circuit 3 is disposed at different positions in the memory granule module 2, the oscillation elimination effect of the clock signal received by each memory granule is stable, and after simulation verification, when the oscillation elimination module is disposed at the clock signal output end of the processor 1, the waveform of the clock signal received by each memory granule is relatively stable, therefore, in the embodiment of the present invention, the oscillation canceling circuit 3 may be disposed at a position between the particle storage module and the clock signal output end of the processor 1, and the oscillation canceling circuit 3 may first perform oscillation canceling on the clock signal output by the processor 1, and then the clock signal may enter the memory particle module 2, so that it is ensured that all the memory particles receive the clock signal having a standard stable waveform, thereby further improving the stability of data processing.

Of course, the preset position may be other specific positions besides the preset position described above, and the embodiment of the present invention is not limited herein.

As a preferred embodiment, the oscillation canceling circuit 3 is a filter circuit.

Specifically, the filter circuit has the advantages of simple structure and good oscillation elimination effect, and is generally low in cost.

Of course, the oscillation canceling circuit 3 may be of various types other than the filter circuit, and the embodiment of the present invention is not limited herein.

As a preferred embodiment, the filter circuit is a capacitor connected in parallel to the clock signal output of the processor 1.

Specifically, the capacitor itself can be used as a filter, and the capacitor has a simple structure, low cost and a long service life.

The capacitor may be of various types, for example, an electrolytic capacitor, and the embodiment of the present invention is not limited herein.

Specifically, the specific capacitance value of the capacitor may be set autonomously, and the oscillation cancellation effect of different capacitance values is different, for example, the capacitance value may be set to 2.2pF, and the like.

Of course, besides the capacitors connected in parallel to the clock signal output terminal of the processor 1, the filter circuit may be of other types, and the embodiment of the present invention is not limited herein.

As a preferred embodiment, the processor 1 is a CPU.

Specifically, the CPU has the advantages of long lifetime, strong processing performance, strong reliability, and the like.

Of course, the processor 1 may be of various types other than the CPU, and the embodiment of the present invention is not limited herein.

In a preferred embodiment, the memory granule in the memory granule module 2 is a double data rate DDR4 memory granule.

Specifically, the DDR (Double Data Rate) 4 has the advantages of high processing speed, long lifetime, high reliability, and the like.

Of course, the memory granules in the memory granule module 2 may be of other types besides DDR4, for example, DDR3 or DDR5, and the embodiment of the present invention is not limited herein.

As a preferred embodiment, the storage device further comprises:

and the signal waveform prompting circuit 4 is arranged in the memory granule module 2 and is used for acquiring and prompting the waveform of the clock signal received by each memory granule in the memory granule module 2.

Specifically, considering that the oscillation eliminating circuit 3 or the processor 1 may have a fault, when the fault occurs, the waveform of the clock signal received by the memory particle module 2 may have a strong oscillation or other errors, which affects data processing work of the storage device, for example, the oscillation eliminating circuit 3 loses the capability of eliminating the oscillation after being damaged, or the processor 1 cannot normally output the clock signal after being damaged, and the like, in the embodiment of the present invention, the waveform of the clock signal received by each memory particle may be obtained and prompted by the signal waveform prompting circuit 4, so that a worker can quickly know and perform corresponding processing through the prompter when the waveform of the clock signal is abnormal, thereby improving maintenance efficiency, and also improving utilization rate of the storage device.

The prompting form may be various, so that a worker can more intuitively see the clock signal waveform, and the waveform may be directly displayed on a display, which is not limited herein.

As a preferred embodiment, the signal waveform prompting circuit 4 includes an oscilloscope which is arranged at a clock signal input end of each memory grain in the memory grain module 2;

wherein, the oscilloscopes correspond to the memory particles one by one.

Specifically, the oscilloscope has the functions of acquiring and displaying waveforms, so that the oscilloscope is selected as the signal waveform prompting circuit 4 in the embodiment of the invention, and the oscilloscope also has the advantages of long service life, small size and the like.

In order to ensure that each memory particle can receive a clock signal with a normal stable waveform, a plurality of oscilloscopes corresponding to the memory particles one to one may be provided, and each oscilloscope may be provided at a clock signal input end of the corresponding memory particle.

Of course, in order to save cost and reduce size, only one oscilloscope may be provided, and the oscilloscope may be provided at the output end of the oscillation canceling circuit 3, and is used to detect and display the waveform of the clock signal after the oscillation canceling circuit 3 is applied, which is not limited herein in the embodiment of the present invention.

Of course, the signal waveform prompting circuit 4 may be of various types other than an oscilloscope, and the embodiment of the present invention is not limited herein.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. It should also be noted that, in the present specification, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.