Method of operating an H-bridge circuit and corresponding driver device
阅读说明：本技术 操作h桥电路的方法和对应的驱动器设备 (Method of operating an H-bridge circuit and corresponding driver device ) 是由 G·L·托里希 D·A·M·波尔图 C·鲁塞尔 于 2020-04-17 设计创作，主要内容包括：本公开的实施例总体上涉及操作H桥电路的方法和对应的驱动器设备。H桥电路包括电源电压节点、第一对晶体管和第二对晶体管。每对晶体管中的第一晶体管具有通过第一晶体管的电流路径,该电流路径分别被包括在电源节点与第一输出节点之间以及在电源节点与第二输出节点之间的电流流动线中。每对晶体管中的第二晶体管具有通过第二晶体管的电流路径,该电流路径分别耦合至第三输出节点和第四输出节点。第一输出节点和第三输出节点互相彼此隔离,并且第二输出节点和第四输出节点互相彼此隔离。H桥电路可以以在第一模式、第二模式和第三模式中选择的一个模式中进行操作。(Embodiments of the present disclosure generally relate to a method of operating an H-bridge circuit and a corresponding driver device. The H-bridge circuit includes a supply voltage node, a first pair of transistors, and a second pair of transistors. The first transistor of each pair has a current path through the first transistor included in the current flow line between the power supply node and the first output node and between the power supply node and the second output node, respectively. The second transistor of each pair of transistors has a current path through the second transistor that is coupled to the third output node and the fourth output node, respectively. The first output node and the third output node are isolated from each other, and the second output node and the fourth output node are isolated from each other. The H-bridge circuit may operate in a selected one of a first mode, a second mode, and a third mode.)
1. A method for driving an H-bridge circuit, wherein the H-bridge circuit comprises:
a power supply node configured to be coupled to a power supply voltage, and a first pair of transistors and a second pair of transistors, each pair of transistors comprising a first transistor and a second transistor,
wherein: the first transistor of the two pairs of transistors having a current path through the first transistor, the current path being included in respective current flow lines between the power supply node and a first output node and between the power supply node and a second output node, respectively, and the second transistor of the two pairs of transistors having a current path through the second transistor, the current paths being coupled to a third output node and a fourth output node, respectively, the first output node and the third output node being isolated from each other and the second output node and the fourth output node being isolated from each other,
the method comprises the following steps:
selecting to operate the H-bridge circuit in one of a plurality of modes, the plurality of modes including a first mode, a second mode, and a third mode, wherein:
i) operating in the first mode comprises:
shorting the first output node to the third output node to provide a first output terminal and shorting the second output node to the fourth output node to provide a second output terminal,
arranging the second transistor of the two pairs of transistors, wherein the current path through the second transistor is coupled between the first output terminal and ground and between the second output terminal and ground, respectively, and
wherein, due to the first transistor of the first pair of transistors, the second transistor of the second pair of transistors, the first transistor of the second pair of transistors and the second transistor of the first pair of transistors being respectively conducting, an inter-output terminal electrical load coupled between the first output terminal and the second output terminal is traversed in opposite directions by a current flowing through the inter-output terminal electrical load;
ii) operating in the second mode comprises:
the second transistor arranged in the two pairs of transistors, wherein the current path through the second transistor is coupled between the third output node and ground and between the fourth output node and ground, respectively,
wherein a first inter-output node electrical load and a second inter-output node electrical load are coupled between the first output node and the third output node and between the second output node and the fourth output node, respectively, wherein the first and second inter-output node electrical loads are configured to be powered due to the first and second transistors of the first pair of transistors being conductive and the first and second transistors of the second pair of transistors being conductive, respectively;
iii) operating in the third mode comprises:
coupling the third output node and the fourth output node to respective supply voltages,
a second transistor arranged in the two pairs of transistors, wherein the current path through the second transistor is coupled to a respective ground reference load referenced to ground opposite the third output node and the fourth output node, wherein the respective ground reference load is configured to be powered as a result of the second transistor in the first pair of transistors and the second transistor in the second pair of transistors being turned on, and
coupling the first output node load to the first output node, wherein the first output node load is configured to be powered as a result of the first transistor of the first pair of transistors being turned on; and
coupling the second output node load to the second output node, wherein the second output node load is configured to be powered as a result of the first transistor of the second pair of transistors being turned on.
2. The method of claim 1, further comprising:
coupling a first pair of transistor drive pins to respective control terminals of the first pair of transistors;
coupling a second pair of transistor drive pins to respective control terminals of the second pair of transistors; and
coupling a charge pump circuit to the first pair of transistor drive pins and the second pair of transistor drive pins to provide charge to the first pair of transistor drive pins and the second pair of transistor drive pins.
3. The method of claim 2, wherein operating in the third mode further comprises coupling the charge pump circuit with the transistor drive pin configured to be coupled to the control terminal of the first transistor of the first and second pairs of transistors and keeping the charge pump circuit decoupled from the transistor drive pin configured to be coupled to the control terminal of the second transistor of the first and second pairs of transistors.
4. The method of claim 2, wherein operating in the third mode further comprises keeping the charge pump circuit decoupled from the transistor drive pin configured to be coupled to the control terminal of the first transistor of the first and second pairs of transistors and coupling the charge pump circuit to the transistor drive pin configured to be coupled to the control terminal of the second transistor of the first and second pairs of transistors.
5. An H-bridge circuit driver device configured to drive an H-bridge circuit comprising a supply node configured to be coupled to a supply voltage and first and second pairs of transistors, each pair comprising a first and second transistor, wherein the first transistor of the two pairs has a current path through the first transistor, the current paths being included in respective current flow lines between the supply node and a first output node and between the supply node and a second output node, respectively, and the second transistor of the two pairs has a current path through the second transistor, the current paths being coupled to third and fourth output nodes, respectively, the first and third output nodes being isolated from each other, and the second output node and the fourth output node are isolated from each other, the H-bridge circuit driver apparatus comprising:
a first pair of transistor drive pins configured to be coupled to respective control terminals of the first pair of transistors in the H-bridge circuit;
a second pair of transistor drive pins configured to be coupled to respective control terminals of the second pair of transistors in the H-bridge circuit;
a first output node pin, a second output node pin, a third output node pin, and a fourth output node pin configured to be coupled to the first output node, the second output node, the third output node, and the fourth output node, respectively;
at least one power supply node pin;
logic control circuitry coupled to the first and second pairs of transistor drive pins, the first, second, third, and fourth output node pins, and the at least one power supply node pin:
i) wherein the logic control circuitry, in a first mode of operation, is configured to:
shorting the first output node pin to the third output node pin and the second output node pin to the fourth output node pin, an
Activating the transistor drive pin for the first transistor of the first pair of transistors and the second transistor of the second pair of transistors, and the drive pin for the first transistor of the second pair of transistors and the second transistor of the second pair of transistors, respectively, to turn on the transistors, wherein the inter-output terminal electrical load is traversed by current flowing through the inter-output terminal electrical load;
ii) wherein the logic control circuitry, in a second mode of operation, is configured to:
activating the transistor drive pins for the first and second transistors of the first pair of transistors and the first and second transistors of the second pair of transistors, respectively, to turn on the transistors, wherein the first and second inter-output-node electrical loads are powered;
iii) wherein the logic control circuitry, in a third mode of operation, is configured to:
coupling the third output node pin and the fourth output node pin to the respective supply voltages,
activating the transistor drive pins for the second transistor of the first pair of transistors and the second transistor of the second pair of transistors to turn on the transistors, wherein the respective ground reference loads are powered; and
activating the transistor drive pin for the first transistor of the first pair of transistors to turn on the transistor, wherein the first output load is powered; and
activating the transistor drive pin for the first transistor in the second pair of transistors to turn on the transistor, wherein the second output load is powered.
6. The H-bridge circuit driver device of claim 5, further comprising a charge pump circuit configured to be coupled to the first and second pairs of transistor drive pins to provide charge to the first and second pairs of transistor drive pins.
7. The H-bridge circuit driver device of claim 6, wherein in the third mode of operation, the logic control circuitry is further configured to couple the charge pump circuit with the transistor drive pin configured to be coupled to the control terminal of the first transistor of the first and second pairs of transistors and to keep the charge pump circuit decoupled from the transistor drive pin configured to be coupled to the control terminal of the second transistor of the first and second pairs of transistors.
8. The H-bridge circuit driver device of claim 6, wherein in the third mode of operation, the logic control circuitry is further configured to keep the charge pump circuit decoupled from the transistor drive pin configured to be coupled to the control terminal of the first transistor of the first and second pairs of transistors and to couple the charge pump circuit with a transistor drive pin configured to be coupled to the control terminal of the second transistor of the first and second pairs of transistors.
9. The H-bridge circuit driver apparatus of claim 5, further comprising:
a memory comprising a register set, wherein:
a) at least one register of the register set is configured to provide a signal to the logic control circuitry in the H-bridge circuit driver device to operate the H-bridge circuit in a selected one of the first, second and third modes of operation, an
b) At least one other register of the register set is configured to store a binary value indicating a selected one of the first, second, and third operating modes.
Technical Field
The present description relates to driving an H-bridge circuit.
One or more embodiments may be applied to drive components, for example, for consumer electronics and industrial control, as well as dc motor control.
Background
Various control circuits may be employed to drive the bi-directional dc motor.
For example, the motor may be driven via four MOSFET transistors in an H-bridge configuration, which can switch the polarity of a signal applied to the load.
To provide a driver that can operate in a manner independent of load type, the H-bridge driver may embed separate multiple Intellectual Property (IP) items for each different application mode. In electronic design, a semiconductor intellectual property core, an IP core, or an IP block is a term of art that refers to a reusable unit designed for the layout of logic, cells, or integrated circuits (commonly referred to as "chips") of one party's intellectual property.
One solution as described above involves replicating the internal circuitry. This presents significant drawbacks in terms of die size (area increase) and packaging (additional pin count), leading to undesirable additional costs.
Embedding multiple IPs is therefore a difficult option to imagine in the case of Standard Products (SPs) that are expected to be small and inexpensive in order to be attractive and competitive to the market.
Accordingly, there is a need in the art to provide such an improved solution.
Disclosure of Invention
One or more embodiments may relate to a corresponding H-bridge circuit driver apparatus.
A method of operating the H-bridge circuit in multiple modes may be an example of such a method.
One or more embodiments may include a flexibly adaptable architecture to address a number of different applications.
One or more embodiments may include related diagnostic structures that operate under all different conditions.
One or more embodiments may provide independent driving of external MOSFET transistors (e.g., in a so-called "quad mode").
One or more embodiments may facilitate operation with a single stage charge pump topology, reduce cost, and optimize price.
Drawings
One or more embodiments will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which:
fig. 1 and 2 are examples of H-bridge circuits;
FIGS. 3-5 are exemplary diagrams of one or more embodiments of a method for driving an H-bridge circuit;
FIGS. 6 and 7 are exemplary diagrams of one or more embodiments of an application of a method for driving an H-bridge circuit; and is
Fig. 8 is a schematic view of a portion of fig. 7.
Detailed Description
In the following description, one or more specific details are illustrated to provide a thorough understanding of examples of embodiments of the present description. Embodiments may be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments.
Reference to "an embodiment" or "one embodiment" within the framework of the specification is intended to indicate that a particular configuration, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment" or "in one embodiment" that may be present in one or more points of the specification do not necessarily refer to one and the same embodiment.
Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
References used herein are provided for convenience only and thus do not limit the extent of protection or the scope of the embodiments.
The drawings are in simplified form and are not to precise scale. For simplicity, directional (up/down, etc.) or motional (forward/backward, etc.) terms may be used with respect to the figures. The term "coupled" and similar terms do not necessarily denote a direct connection or an immediate connection, but also include a connection through intermediate elements or devices.
As illustrated in fig. 1 and 2, the H-bridge circuit 10 may include a power supply node VDD configured to be coupled to a supply voltage, e.g., a Direct Current (DC) source such as a battery or charge pump, providing the voltage VDD, and the source terminal of the low-side device is connected to ground GND, as well as a first pair of "left-leg" transistors QH1, QL1 (e.g., MOSFET transistor devices) of the bridge and a second pair of "right-leg" transistors QH2, QL2 (e.g., MOSFET transistor devices) of the bridge. In other words, the H-bridge circuit 10 may employ a pair of "high-side" MOSFET transistor devices QH1, QH2 and a pair of "low-side" MOSFET transistor devices QL1, QL 2. The H-bridge 10 may be discussed as having "left" and "right" legs, each having a high-side transistor QH1, QH2 and a low-side transistor QL1, QL2, respectively.
In one or more embodiments, a pair of output terminals E1, E2 between current paths through the left side transistors QH1, QL1 and the right side transistors QH2, QL2 may be configured to be connected to a load Z, such as a bi-directional motor load Z.
A control circuit D may be provided that is configured to operate the transistors (e.g., on/off) the high side QH1, QH2 device and the low side QL1, QL2 device such that the transistors QH1, QH2, QL1, QL2 may be modeled as switches to drive current through the motor Z, e.g., in a direction through its windings to rotate the motor Z rotor in a clockwise or counterclockwise direction. For the sake of simplicity, the electrical connection of the control circuit D is represented by an arrow pointing to the H-bridge circuit 10.
If an application involves driving more than one load, it is possible to use a "half-bridge", e.g. using two transistors QH1, QL1 in one branch of the H-bridge 10, similar to a class AB amplifier solution.
For example, as shown in fig. 2, the half-bridges may be controlled via respective controllers Da, Db to drive two motor loads Za, Zb, wherein the H-bridge 10 may be considered as comprising two parallel half-bridges 10a, 10 b.
Existing H-bridge driver solutions do not provide full flexibility as they may only be able to drive motor type loads, e.g. using H-bridge or half-bridge topologies.
In some cases, an Integrated Circuit (IC) driver may facilitate driving the half-bridges independently in so-called "dual modes" when considering driving the loads Z, Za, Zb in topologies other than that provided by an H-bridge operating in a conventional manner.
In some cases, the same IC device may not be able to drive different applications in which the external transistors QH1, QL1, QH2, QL2 may be configured in any selected manner, such as a high side or a low side. For example, the driver may not be able to operate independently of the type of load.
Fig. 3 shows a diagram of an H-bridge
In the following, for the sake of simplicity, the components in the
In one or more embodiments, as illustrated in fig. 3, the H-bridge circuit 10 may include a power supply node configured to be coupled to a power supply voltage VDD and a first pair of "left-leg" transistors QH1, QL1 and a second pair of "right-leg" transistors QH2, QL2, each pair including a first transistor QH1, QH2 and a second transistor QL1, QL 2.
In one or more embodiments, the two pairs of transistors QH1, QL1 and QH2, the first transistor QH1, QH2 in QL2 have current paths through the first transistors QH1, QH2 in respective current flow lines between the power supply node VDD and the first output node EH1 and between the power supply node VDD and the second output node EH2, respectively.
In one or more embodiments, the second transistor QL1, QL2 in the "left" pair of transistors QH1, QL1 and the "right" pair of transistors QH2, QL2, respectively, has a current path through the current path, which is coupled to the third output node EL1 and the fourth output node EL2, respectively.
In one or more embodiments (see fig. 5), the first output node EH1 and the third output node EL1 may be isolated from each other, and the second output node EH2 and the fourth output node EL2 may be isolated from each other.
As illustrated in fig. 3, the logic
a first pair of transistor drive pins GH1, GL1 and a second pair of transistor drive pins GH2, GL2 configured to be coupled to respective control terminals of a first pair of transistors QH1, QL1 and a second pair of transistors QH2, QL2 in the H-bridge circuit 10;
first and second output node pins SH1 and SH2 and third and fourth output node pins DL1 and DL2 configured to be coupled to first and second output nodes EH1 and EH2 and third and fourth output nodes EL1 and EL2, respectively;
-at least one power supply node pin VS;
In one or more embodiments, the
In one or more embodiments, the H-
a set of paired
a set of pairs of pull-up resistors, for example, two pairs of resistors RH1, RH 2; RL1, RL2 for off-state diagnostics;
a pair of
a set of switch pairs 21, 22; 51, 52; 81. 82 which are operable via signals provided to respective
In one or more embodiments, the resistances in the resistance sets RH1, RL1 may have the same value, e.g., RH1 RL 1kOhm 20kOhm (1kOhm 103Ohm)。
Fig. 4 is an exemplary illustration of a possible use of the H-
In the example considered:
the first pair of
the second pair of
In one or more embodiments, the drive bridge may be used in half-bridge mode (dual mode) for two separate motors in a manner known per se, for example by setting the dual mode bit DM-1 in a dedicated logic circuit block control or status register, as discussed below.
Fig. 5 is an exemplary diagram of possible use of the
In the example considered:
the first pair of
the second pair of
As illustrated in fig. 5:
the first inter-output-node load Z10 may be coupled between the first pin SH1 and ground GND or between the first pin SH1 and the second pin DL1,
the second inter-output-node load Z20 may be coupled between the third pin SH2 and ground GND or between the third pin SH2 and the fourth pin DL2,
thus, in one or more embodiments, the high-side transistor may drive a heating application (while the low-side transistor may ground or "float" the heater).
In one or more embodiments as illustrated in fig. 7, it is possible to have up to four transistors QH1, QL1, QH2, QL2 all operate as "high-side" drivers to make IP more flexible.
In this particular case, it may be necessary to include an additional pair of operational amplifiers (abbreviated as op-amps) for lower device drain-source monitoring in order to perform a comprehensive diagnosis. In fact, due to this configuration, the operational amplifiers (simply referred to as operational amplifiers) 71 and 72 cannot perform both open load diagnosis and drain-source diagnosis (see, for example, fig. 8).
In one or more embodiments, for example, in a cost/size optimized solution, such as for Application Specific Standard Products (ASSPs) that employ a low power single stage charge pump CP, a solution is provided to handle CP current capability.
In one or more embodiments, the third transistor QL1 and the fourth transistor QL2 may also be driven as "high-side" transistors, alternating sequentially (not simultaneously) with the other two transistors QH1, QH 2.
As discussed below, such an arrangement may advantageously facilitate avoiding modifications in the charge pump CP fan-out, while facilitating flexible adoption of a "four high side" H-bridge arrangement.
In one or more embodiments, the driver circuits may include respective control logic blocks 101, 102.
In one or more embodiments of the
In one or more embodiments, the respective
Hereinafter, the drain terminals of the low-side transistors are indicated as auxiliary load nodes SL1 and SL2, respectively, and may be "floating" rather than coupled to ground GND.
In the example considered, for example:
the low-side transistor QL1, QL2 may be operated to provide current to a load coupled to the SL1, SL2 drain terminal node only when the switches CP _ GOOD _1, CP _ GOOD _2 are in the first state, e.g., only when the switches CP _ GOOD _1, CP _ GOOD _2 are "closed";
the high-side transistors QH1, QH2 may be operated to provide current to a load coupled to the third node DL1 and the fourth node DL2 only when the switches CP _ GOOD _1, CP _ GOOD _2 are in the second state, e.g., only when CP _ GOOD _1 and CP _ GOOD _2 are "off.
In one or more embodiments, the switches CP _ GOOD _1 and CP _ GOOD _2 may be operated via the respective signals "CP _ GOOD".
In one or more embodiments, CP fanout may be maintained, due to the solution discussed herein, while facilitating driving up to four transistors to provide current to a load.
Fig. 7 is an exemplary diagram of the use of a driver circuit D to provide current to four loads, e.g., a blower motor Z40, a mist eliminator Z30, a pair of heater impedances Z10, Z20. Such an arrangement of the loads Z10, Z20, Z30, Z40 can be used advantageously, for example, in a body control module for automotive applications.
Since the signals are issued on respective conductors and their values can be stored in dedicated registers C _ reg, S _ reg coupled to the
For example:
the control register C reg can store binary data comprising information about how to change the pairs of switch pairs 21, 22 of the
the status register S reg may store binary data including information about the pairs of
In one or more embodiments, microcontroller MP may host software code portions to provide data to such registers, e.g., through SPI communication, and may provide binary data therein to driver
In one or more embodiments, the control register C _ reg and the status register S _ reg may have a given number of bits, e.g., 24 bits. The value of such a bit may be assigned to have a certain binary value depending on the state of the switch for activation, e.g. if the 22 nd bit has a value of "0", the switch is activated to "off".
In the following, the table summarizes which bits (denoted by reference for their e.g. QM, QMDIR) may be provided or added to the control register C reg in order to activate the first mode, the second mode or the third mode, e.g. "quad mode", or e.g. direct drive for existing pin DIRH and PWMH configurations. Other bits may also be added for independent drain-source monitoring of the transistor.
For example, when the 20 th bit in the register in the control register, indicated as QM, has a first value, then the H-bridge driver may be operated to drive four loads with two charge pumps. For example, the default value of the bit QM may be "0", and when set to the value "1", the bit may enable driving of four loads.
Table I below shows an example of values of Most Significant Bits (MSBs) in a control register for setting one mode of the H-bridge driver.
TABLE I
In one or more embodiments, the 19 th bit in control register C reg indicated as QMDIR _2 and the bits indicated as QMDIR _1, QMDIR _0 may be configured to select a drive configuration. In particular, in one or more embodiments, the setting of the bits indicated as QMDIR _2, QMDIR _1, and QMDIR _0 may help to select a pair of input pins DIRH, which of PWMH may actually be used (e.g., directly) to drive any of the transistor groups QH1, QH2, QL1, or QL 2. For example, as indicated in the following table:
in one or more embodiments, the mode of operation in, for example, the last row of table II, may be set to a default mode of operation.
Table II below is an example of possible selections of input pins to drive any of the transistor groups QH1, QH2, QL1, or QL 2.
TABLE II
Note that these configurations may be valid if bit QM has a first value, e.g., QM equals "1". In other cases, the pins follow either "single" or "double" mode behavior depending on the selected mode of operation.
In one or more embodiments, a bit indicated as QMPLUS may facilitate operating all MOSFETs in the H-bridge 10 as high-side transistors. For example, when QM has a first value, e.g., QM equals "0", the third operation mode is disabled, and if QM has a second value, e.g., QM equals "1", the third operation mode is enabled.
Furthermore, as previously mentioned, the status register S reg may also be updated to facilitate control by the
Table III below shows a summary of the values of the status register bits, in particular the Status Register (SR) Least Significant Bit (LSB) values.
TABLE III
As illustrated in fig. 8, representing a portion of fig. 7, and in particular the left-hand portion of the "quad high-side" arrangement of fig. 7, one or more embodiments may include a dedicated operational amplifier 91 coupled between the drain and source (e.g., of transistor QL1 on the left) to facilitate drain-source monitoring, e.g., detection of a possible short-circuit condition to ground GND. In particular, such an op-amp 91 may be used to detect such a condition during the on-state of the transistor QL 1.
A method according to one or more embodiments may include:
a) providing an H-bridge circuit comprising a power supply node configured to be coupled to a power supply voltage (e.g., VDD) and a first pair of transistors (e.g., QH1, QL1) and a second pair of transistors (e.g., QH2, QL2), each pair of transistors comprising a first transistor (e.g., QH1, QH2) and a second transistor (e.g., QL1, QL2), wherein:
a first transistor of the two pairs of transistors may have a current path through the first transistor, the current path being included in respective current flow lines between the supply node and a first output node (e.g. EH1) and between the supply node and a second output node (e.g. EH2), respectively, and
the second transistor of the two pairs of transistors may have a current path through the second transistor, the current path being coupled to a third output node (e.g. EL1) and a fourth output node (e.g. EL2), respectively, the first and third output nodes being isolated from each other and the second and fourth output nodes being isolated from each other,
b) operating the H-bridge circuit in a selected one of a plurality of modes including a first mode, a second mode, and a third mode, wherein:
-i) in the first mode:
-shorting the first output node to the third output node to provide a first output terminal (EH1, EL1), and shorting the second output node to the fourth output node to provide a second output terminal,
a second transistor of the two pairs of transistors is arranged to have a current path through the current path, the current path being coupled between the first output terminal and ground (e.g. GND) and between the second output terminal and ground (e.g. GND), respectively,
an inter-output terminal electrical load (e.g., Z1) may be coupled between a first output terminal (e.g., EH1, EL1) and a second output terminal (e.g., EL1, EL2), wherein the inter-output terminal electrical load is configured to be traversed in opposite directions by current flowing through the inter-output terminal electrical load due to a first transistor (e.g., QH1) in the first pair of transistors, a second transistor (e.g., QL2) in the second pair of transistors, a first transistor (e.g., QH2) in the second pair of transistors, and a second transistor (e.g., QL1) in the first pair of transistors, respectively, being turned on.
-ii) in the second mode:
a second transistor of the two pairs of transistors (e.g. QL1, QL2) is arranged to have a current path through the second transistor, the current path being coupled between the third output node and ground and the fourth output node and ground, respectively,
a first inter-output-node electrical load (e.g., Z10) and a second inter-output-node electrical load (e.g., Z20) may be coupled between the first output node (e.g., EH1) and the third output node (e.g., EL2) and the second output node (e.g., EH2) and the fourth output node (e.g., EL2), respectively, wherein the first inter-output-node electrical load and the second inter-output-node electrical load are configured to be powered due to the first transistor and the second transistor of the first pair of transistors being conductive and the first transistor and the second transistor of the second pair of transistors being conductive, respectively;
-iii) in the third mode:
the third output node and the fourth output node may be coupled to respective supply voltages (e.g. VS),
-a second transistor of the two pairs of transistors is arranged to have a current path through the second transistor, the current path being coupleable to a respective ground reference load (e.g. Z10, Z20) with a reference ground (e.g. GND) opposite the third output node (e.g. EL1) and the fourth output node (e.g. EL2), wherein the respective ground reference load (e.g. Z20) is configured to be powered as a result of the second transistor of the first pair of transistors and the second transistor of the second pair of transistors being conductive,
a first output node load (e.g., Z30) may be coupled to the first output node (e.g., EH1), wherein the first output load is configured to be powered as a result of a first transistor of a first pair of transistors being turned on,
-a second output node load (e.g. Z40) may be coupled to the second output node, wherein the second output node load (e.g. Z40) is configured to be powered as a result of the first transistor of the second pair of transistors being turned on.
In one or more embodiments, the method may include:
-providing a first pair of transistor drive pins (e.g. GH1, GL1) and a second pair of transistor drive pins (e.g. GH2, GL2) configured to be coupled to respective control terminals of the first and second pairs of transistors in the H-bridge circuit;
-providing a charge pump circuit (e.g. CP) configured to be coupled to the first and second pairs of transistor drive pins to provide charge to the first and second pairs of transistor drive pins.
In one or more embodiments, in the third mode, the method may include any one of:
-coupling a charge pump circuit (e.g. CP) with a transistor drive pin (e.g. GH1, GH2) configured to be coupled to a control terminal of a first transistor of the first and second pairs of transistors and keeping the charge pump circuit decoupled from a transistor drive pin configured to be coupled to a control terminal of a second transistor of the first and second pairs of transistors, and
-keeping the charge pump circuit decoupled from the transistor drive pin configured to be coupled to the control terminal of the first transistor of the first and second pairs of transistors, and coupling the charge pump circuit to the transistor drive pin configured to be coupled to the control terminal of the second transistor of the first and second pairs of transistors.
One or more embodiments may include an H-bridge circuit driver device configured to drive an H-bridge circuit using the method of any one of the preceding claims, the H-bridge circuit comprising a power supply node configured to be coupled to a power supply voltage (e.g., VDD) and a first pair of transistors (e.g., QH1, QL1) and a second pair of transistors (e.g., QH2, QL2), each pair of transistors comprising a first transistor (e.g., QH1, QH2) and a second transistor (e.g., QL1, QL2), wherein a first transistor (e.g., QH1, QH2) of the two pairs of transistors (e.g., QH1, QL 1; QH2, QL2) has a current path through the first transistor, the current paths being included in respective current lines between the power supply node (e.g., VDD) and a first output node (e.g., EH1) and between the power supply node (e.g., EH2) and a second output node (e.g., EH2), and a second transistor of the two pairs of transistors has a current path through the second transistor, the current path coupled to a third output node (e.g., EL1) and a fourth output node (e.g., EL2), respectively, the first output node and the third output node being isolated from each other and the second output node and the fourth output node being isolated from each other.
In one or more embodiments, a driver device may include:
-a first pair of transistor drive pins (e.g. GH1, GL1) and a second pair of transistor drive pins (e.g. GH2, GL2) configured to be coupled to respective control terminals of a first pair of transistors (e.g. QH1, QL1) and a second pair of transistors (e.g. QH2, QL2) in the H-bridge circuit;
a first output node pin (e.g. SH1), a second output node pin (e.g. SH2), a third output node pin (e.g. DL1) and a fourth output node pin (e.g. DL2) configured to be coupled to a first output node, a second output node, a third output node and a fourth output node, respectively;
-at least one power supply node pin (e.g. VS);
-logic control circuitry (e.g. 101, 102) coupled to the first and second pairs of transistor drive pins, the first, second, third and fourth output node pins and the at least one power supply node pin (e.g. VS), the logic control circuitry (101, 102) configured to:
-i) in the first mode:
shorting the first output node pin to the third output node pin and the second output node pin (e.g. SH2) to the fourth output node pin (e.g. DL2),
-activating a transistor drive pin (e.g. GH1, GL2) for a first transistor of the first pair of transistors and a second transistor of the second pair of transistors (e.g. GH2, GL2), respectively, to render the transistors conductive, wherein the inter-output terminal electrical load (e.g. Z1) is traversed by a current flowing through the inter-output terminal electrical load;
-ii) in the second mode:
-activating transistor drive pins for a first transistor and a second transistor of the first pair of transistors (e.g. GH1, GL1) and for a first transistor and a second transistor of the second pair of transistors, respectively, to turn on the transistors, wherein the first inter-output node electrical load (e.g. Z10) and the second inter-output node electrical load (e.g. Z20) are powered.
-iii) in the third mode:
-coupling a third output node pin and a fourth output node pin to the respective supply voltage (e.g. VS),
-activating transistor drive pins (e.g. GL1, GL2) for a second transistor of the first pair and a second transistor of the second pair of transistors to turn on the transistors, wherein the respective ground reference loads (e.g. Z20) are powered,
-activating a transistor drive pin (e.g. GH1) for a first transistor of a first pair of transistors to turn on the transistor, wherein the first output load (e.g. Z30) is powered;
-activating a transistor drive pin (e.g. GH2) for a first transistor of a second pair of transistors to turn on the transistor, wherein the second output load (e.g. Z40) is powered.
In one or more embodiments, the H-bridge circuit driver device may include a charge pump circuit (e.g., CP) configured to be coupled to the first and second pairs of transistor drive pins to provide charge to the first and second pairs of transistor drive pins.
In one or more embodiments, in the third mode, the H-bridge circuit may include any one of:
-coupling the charge pump circuit with a transistor drive pin configured to be coupled to a control terminal of a first transistor of the first and second pairs of transistors and keeping the charge pump circuit decoupled from a transistor drive pin configured to be coupled to a control terminal of a second transistor of the first and second pairs of transistors, and
-keeping the charge pump circuit decoupled from the transistor drive pin configured to be coupled to the control terminal of the first transistor of the first and second pairs of transistors, and coupling the charge pump circuit to the transistor drive pin configured to be coupled to the control terminal of the second transistor of the first and second pairs of transistors.
One or more embodiments of a system may include:
one or more embodiments of an H-bridge circuit driver device, and
-a memory (e.g. MP) comprising a register set (e.g. S _ reg, C _ reg), wherein:
a) at least one register (e.g., C _ reg) in a register set (e.g., S _ reg, C _ reg) may be configured to provide signals to the logic control circuitry (e.g., 101, 102) in the H-bridge circuit driver device to operate the H-bridge circuit in a selected one of a plurality of modes, including a first mode, a second mode, and a third mode, and
b) at least one other register (e.g., S reg) in the register set may be configured to store a binary value indicating a selected one of a plurality of modes including a first mode, a second mode, and a third mode for operating the H-bridge circuit driver.
It will also be appreciated that the various individual implementation options illustrated throughout the drawings accompanying this specification are not necessarily intended to be employed in the same combination illustrated in the drawings. Thus, one or more embodiments may employ these options alone and/or in different combinations relative to the combinations exemplified in the figures (again, not mandatory).
The claims are an integral part of the technical guidance provided herein with reference to the examples.
Without prejudice to the underlying principles, the details and the embodiments may vary, even significantly, with respect to what has been described purely by way of example, without thereby departing from the scope of protection. The scope of protection is defined by the appended claims.
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