阅读说明：本技术 存储装置以及存储装置的制造方法 (Memory device and method for manufacturing memory device ) 是由 园田康幸 于 2019-08-12 设计创作，主要内容包括：实施方式提供一种更高性能的存储装置和存储装置的制造方法。实施方式涉及的存储装置的制造方法包括在基底之上隔开间隔形成第1层叠体以及第2层叠体。形成具有第1层叠体的侧面上的第1部分、第2层叠体的侧面上的第2部分、以及第1层叠体与第2层叠体之间的基底之上的第3部分的第1绝缘体。利用离子束,一边使第1绝缘体的第3部分残留,一边使第1绝缘体的第1部分的一部分和第2部分的一部分变薄。在第1绝缘体的第1部分与第1绝缘体的第2部分之间形成第2绝缘体。(Embodiments provide a higher-performance memory device and a method of manufacturing the memory device. The method for manufacturing a memory device according to an embodiment includes forming a 1 st stacked body and a 2 nd stacked body at intervals on a substrate. A 1 st insulator is formed having a 1 st portion on a side of the 1 st stack, a 2 nd portion on a side of the 2 nd stack, and a 3 rd portion over the substrate between the 1 st and 2 nd stacks. The ion beam thins a part of the 1 st portion and a part of the 2 nd portion of the 1 st insulator while leaving the 3 rd portion of the 1 st insulator. A 2 nd insulator is formed between the 1 st portion of the 1 st insulator and the 2 nd portion of the 1 st insulator.)

1. A method of manufacturing a memory device, comprising:

forming a 1 st stacked body and a 2 nd stacked body at intervals over a substrate;

forming a 1 st insulator, the 1 st insulator having a 1 st portion on a side of the 1 st stack, a 2 nd portion on a side of the 2 nd stack, and a 3 rd portion over the substrate between the 1 st stack and the 2 nd stack;

thinning a portion of the 1 st portion and a portion of the 2 nd portion of the 1 st insulator by an ion beam while leaving the 3 rd portion of the 1 st insulator; and

forming a 2 nd insulator between the 1 st portion of the 1 st insulator and the 2 nd portion of the 1 st insulator.

2. The method of manufacturing a memory device according to claim 1,

the 2 nd insulator includes a 1 st portion having a 1 st surface and a 2 nd surface opposite to the 1 st surface, the 1 st surface being in contact with the 1 st portion of the 1 st stacked body, and the 2 nd surface being in contact with the 2 nd portion of the 2 nd stacked body.

3. The method of manufacturing a memory device according to claim 1,

the 1 st stack or the 2 nd stack includes an element exhibiting a magnetoresistance effect.

4. The method of manufacturing a memory device according to claim 1,

thinning the 1 st portion of the 1 st insulator and the 2 nd portion of the 1 st insulator comprises: irradiating an ion beam having a 1 st angle with respect to an extending direction of the side surface of the 1 st stacked body or the side surface of the 2 nd stacked body.

5. The method of manufacturing a memory device according to claim 1,

the 1 st stack or the 2 nd stack includes a bidirectional switching element.

6. A storage device is provided with:

a 1 st stacked body which is located on the substrate and includes an element exhibiting a magnetoresistance effect;

a 2 nd stack spaced apart from the 1 st stack over the substrate and including an element exhibiting a magnetoresistance effect; and

and an insulator including a 1 st portion having a 1 st surface and a 2 nd surface opposite to the 1 st surface, the 1 st surface being in contact with a side surface of the 1 st stacked body, and the 2 nd surface being in contact with a side surface of the 2 nd stacked body.

Technical Field

Background

A memory device using a magnetoresistance effect element is known.

Disclosure of Invention

The present invention is directed to provide a method for manufacturing a higher-performance memory device.

Drawings

Fig. 1 shows functional blocks of a storage device according to embodiment 1.

Fig. 2 is a circuit diagram of one memory cell of embodiment 1.

Fig. 3 shows a structure of a part of the memory cell array of embodiment 1.

Fig. 4 shows an example of the laminate and a state of magnetization in embodiment 1.

Fig. 5 shows a state between manufacturing processes of a part of the memory device according to embodiment 1.

Fig. 6 shows a state following fig. 5.

Fig. 7 shows a state following fig. 6.

Fig. 8 shows a state following fig. 7.

Fig. 9 shows a state following fig. 8.

Fig. 10 shows a state following fig. 9.

Fig. 11 shows a state between manufacturing processes of a memory device for reference.

Fig. 12 shows functional blocks of the storage device according to embodiment 2.

Fig. 13 is a circuit diagram of one memory cell of embodiment 2.

Fig. 14 shows a structure of a part of the memory cell array according to embodiment 2.

Fig. 15 shows an example of the laminate according to embodiment 2 and a state of magnetization.

Fig. 16 shows a state between manufacturing steps of a part of the memory device according to embodiment 2.

Fig. 17 shows a state following fig. 16.

Fig. 18 shows a state following fig. 17.

Fig. 19 shows a state following fig. 18.

Fig. 20 shows a state following fig. 19.

Description of the reference symbols

1a storage device; 11 an array of memory cells; 12 input/output circuits; 13 a control circuit; 14 row selection circuits; 15 column select circuits; 16 a write circuit; 17 a readout circuit; an MC memory cell; a WL word line; BL,/BL bit lines; a VR resistance change element; an ST selection transistor; 20 a substrate; 21a lower electrode; 22 an interlayer insulator; 24a laminate; 26 interlayer insulators; 31a buffer layer; a 32MTJ element; 321a ferromagnetic body; 322 an insulator; 323a ferromagnetic body; 33a cap layer; 34a hard mask; 36a variable resistance material; 43 inter-stack region.

Embodiments generally relate to a memory device and a method of manufacturing the memory device.