阅读说明：本技术 用于降低电平移位器的输出偏斜和转换延迟的设备和方法 (Apparatus and method for reducing output skew and transition delay of level shifter ) 是由 陈智伟 于 2019-10-24 设计创作，主要内容包括：提供了用于降低电平移位器的输出偏斜和转换延迟的设备和方法。根据一个实施例,所述设备包括：电平移位器电路,被配置为输出电压Vo1+和Vo1-；以及输出校准电路,被配置为输出由Vo1+和Vo1-的组合的边沿触发的电压Vo+和Vo-,并且其中,在对电平移位器电路的输入的转换之前,通过Vo1+和Vo1-的高状态设置Vo+和Vo-。(An apparatus and method for reducing output skew and transition delay of a level shifter are provided. According to one embodiment, the apparatus comprises: a level shifter circuit configured to output voltages Vo1+ and Vo 1-; and an output calibration circuit configured to output voltages Vo + and Vo-triggered by edges of a combination of Vo1+ and Vo1-, and wherein Vo + and Vo-are set by high states of Vo1+ and Vo1-, prior to a transition to an input of the level shifter circuit.)

1. An apparatus for reducing output skew and transition delay of a level shifter, comprising:

a level shifter circuit configured to output voltages Vo1+ and Vo 1-; and

an output calibration circuit configured to output voltages Vo + and Vo-triggered by the combined edges of Vo1+ and Vo1-, and wherein Vo + and Vo-are set by the high states of Vo1+ and Vo 1-prior to a transition to the input of the level shifter circuit.

2. The apparatus of claim 1, wherein the output calibration circuit comprises:

a first inverter configured to receive a first input signal;

a second inverter configured to receive a second input signal that is an inverted signal of the first input signal;

a third inverter connected to the first inverter;

a fourth inverter connected to the second inverter;

a logic circuit connected to the first, second, third, and fourth inverters and configured to reduce output skew and conversion delay between the first and second input signals; and

a flip-flop connected to the logic circuit and configured to latch the reduced output skew and the transition delay between the first input signal and the second input signal.

3. The apparatus of claim 2, wherein the logic circuitry comprises:

a first nand gate connected to the first inverter and the third inverter;

a second nand gate connected to the second inverter and the fourth inverter;

a third nand gate connected to the second inverter and the first nand gate; and

and the fourth NAND gate is connected to the first inverter and the second NAND gate.

4. The apparatus of claim 1, wherein the level shifter circuit is a low-to-high voltage level shifter circuit.

5. The apparatus of claim 4, wherein the low-to-high voltage level shifter circuit comprises:

a fifth inverter configured to receive a third input signal and including a power input terminal connected to the first power voltage VDD1 and a ground input terminal connected to the second power voltage VSS 1;

a first n-channel transistor comprising: a source connected to the second power supply voltage VSS1, a gate connected to an output terminal of the fifth inverter, and a drain;

a second n-channel transistor comprising: a source connected to the second power supply voltage VSS1, a gate connected to an input terminal of the fifth inverter, and a drain;

a first p-channel transistor comprising: a drain connected to the drain of the first n-channel transistor, a gate connected to a third power supply voltage VSS2, and a source;

a second p-channel transistor comprising: a drain connected to the drain of the second n-channel transistor, a gate connected to a third power supply voltage VSS2, and a source;

a third p-channel transistor comprising: a drain connected to the source of the first p-channel transistor, a gate, and a source connected to a fourth power supply voltage VDD 2;

a fourth p-channel transistor comprising: a drain connected to the source of the second p-channel transistor and the gate of the third p-channel transistor, a gate connected to the drain of the third p-channel transistor, and a source connected to a fourth power supply voltage VDD 2;

a first buffer connected between a drain of the fourth p-channel transistor and the second inverter, and including: a power input terminal connected to a fourth power supply voltage VDD2 and a ground input terminal connected to a third power supply voltage VSS 2; and

a second buffer connected between the source of the first p-channel transistor and the first inverter, and including: a power input terminal connected to a fourth power supply voltage VDD2 and a ground input terminal connected to a third power supply voltage VSS 2.

6. The apparatus of claim 5, wherein:

the first n-channel transistor and the second n-channel transistor are each an n-channel laterally diffused metal oxide semiconductor field effect transistor;

the first p-channel transistor and the second p-channel transistor are each p-channel laterally diffused metal oxide semiconductor field effect transistors; and

the third p-channel transistor and the fourth p-channel transistor are each p-channel metal oxide semiconductor field effect transistors.

7. The device of claim 5, wherein VSS1 is 0 volts, VDD1 is 6 volts, VSS2 is 17 volts, and VDD2 is 23 volts.

8. The apparatus of claim 1, wherein the level shifter circuit is a high-to-low voltage level shifter circuit.

9. The apparatus of claim 8, wherein the high-to-low voltage level shifter circuit comprises:

a sixth inverter configured to receive a fourth input signal and comprising: a power input terminal connected to a fourth power supply voltage VDD2 and a ground input terminal connected to a third power supply voltage VSS 2;

a fifth p-channel transistor comprising: a source connected to a fourth power supply voltage VDD2, a gate connected to an output terminal of the sixth inverter, and a drain;

a sixth p-channel transistor comprising: a source connected to a fourth power supply voltage VDD2, a gate connected to an input of the sixth inverter, and a drain;

a third n-channel transistor comprising: a drain connected to the drain of the fifth p-channel transistor, a gate connected to a first power supply voltage VDD1, and a source;

a fourth n-channel transistor comprising: a drain connected to the drain of the sixth p-channel transistor, a gate connected to a first power supply voltage VDD1, and a source;

a fifth n-channel transistor comprising: a drain connected to the source of the third n-channel transistor, a gate, and a source connected to a second power supply voltage VSS 1;

a sixth n-channel transistor comprising: a drain connected to the source of the fourth n-channel transistor and the gate of the fifth n-channel transistor, a gate connected to the drain of the fifth n-channel transistor, and a source connected to a second power supply voltage VSS 1;

a seventh inverter connected between the source of the third n-channel transistor and the second inverter, and including: a power input terminal connected to a first power supply voltage VDD1 and a ground input terminal connected to a second power supply voltage VSS 1; and

an eighth inverter connected between the drain of the sixth n-channel transistor and the first inverter, and including: a power input terminal connected to a first power supply voltage VDD1 and a ground input terminal connected to a second power supply voltage VSS 1.

10. The apparatus of claim 9, wherein:

the fifth p-channel transistor and the sixth p-channel transistor are each a p-channel laterally diffused metal oxide semiconductor field effect transistor;

the third n-channel transistor and the fourth n-channel transistor are each an n-channel laterally diffused metal oxide semiconductor field effect transistor; and

the fifth n-channel transistor and the sixth n-channel transistor are each n-channel metal oxide semiconductor field effect transistors, and wherein VSS1 is 0 volts, VDD1 is 6 volts, VSS2 is 17 volts, and VDD2 is 23 volts.

11. A method for reducing output skew and transition delay of a level shifter, comprising:

the voltages Vo1+ and Vo 1-are output by the level shifter circuit; and

the voltages Vo + and Vo-triggered by the combined edges of Vo1+ and Vo 1-are output by the output calibration circuit, and wherein Vo + and Vo-are set by the high states of Vo1+ and Vo 1-prior to a transition to the input of the level shifter circuit.

12. The method of claim 11, further comprising:

inverting the first input signal by a first inverter;

inverting, by a second inverter, a second input signal that is an inverted signal of the first input signal;

inverting an output of the first inverter by the third inverter;

inverting an output of the second inverter by the fourth inverter;

reducing, by a logic circuit connected to the first inverter, the second inverter, the third inverter, and the fourth inverter, an output skew and a conversion delay between the first input signal and the second input signal; and

the reduced output skew and transition delay between the first input signal and the second input signal is latched by a flip-flop connected to the logic circuit.

13. The method of claim 12, wherein the logic circuit comprises:

a first nand gate connected to the first inverter and the third inverter;

a second nand gate connected to the second inverter and the fourth inverter;

a third nand gate connected to the second inverter and the first nand gate; and

and the fourth NAND gate is connected to the first inverter and the second NAND gate.

14. The method of claim 11, further comprising: the voltage is shifted from a low voltage to a high voltage level shifter circuit.

15. The method of claim 14, wherein the low-to-high voltage level shifter circuit comprises:

a fifth inverter configured to receive a third input signal and comprising: a power input terminal connected to a first power supply voltage VDD1 and a ground input terminal connected to a second power supply voltage VSS 1;

a first n-channel transistor comprising: a source connected to the second power supply voltage VSS1, a gate connected to an output terminal of the fifth inverter, and a drain;

a second n-channel transistor comprising: a source connected to the second power supply voltage VSS1, a gate connected to an input terminal of the fifth inverter, and a drain;

a first p-channel transistor comprising: a drain connected to the drain of the first n-channel transistor, a gate connected to a third power supply voltage VSS2, and a source;

a second p-channel transistor comprising: a drain connected to the drain of the second n-channel transistor, a gate connected to a third power supply voltage VSS2, and a source;

a third p-channel transistor comprising: a drain connected to the source of the first p-channel transistor, a gate, and a source connected to a fourth power supply voltage VDD 2;

a fourth p-channel transistor comprising: a drain connected to the source of the second p-channel transistor and the gate of the third p-channel transistor, a gate connected to the drain of the third p-channel transistor, and a source connected to a fourth power supply voltage VDD 2;

a first buffer connected between a drain of the fourth p-channel transistor and the second inverter, and including: a power input terminal connected to a fourth power supply voltage VDD2 and a ground input terminal connected to a third power supply voltage VSS 2; and

a second buffer connected between the source of the first p-channel transistor and the first inverter, and including: a power input terminal connected to a fourth power supply voltage VDD2 and a ground input terminal connected to a third power supply voltage VSS 2.

16. The method of claim 15, wherein:

the first n-channel transistor and the second n-channel transistor are each an n-channel laterally diffused metal oxide semiconductor field effect transistor;

the first p-channel transistor and the second p-channel transistor are each p-channel laterally diffused metal-semiconductor field effect transistors; and

the third p-channel transistor and the fourth p-channel transistor are each p-channel metal oxide semiconductor field effect transistors.

17. The method of claim 15, wherein VSS1 is 0 volts, VDD1 is 6 volts, VSS2 is 17 volts, and VDD2 is 23 volts.

18. The method of claim 11, further comprising: the voltage is shifted by a high-to-low voltage level shifter circuit.

19. The method of claim 18, wherein the high-to-low voltage level shifter circuit comprises:

a sixth inverter configured to receive a fourth input signal and comprising: a power input terminal connected to a fourth power supply voltage VDD2 and a ground input terminal connected to a third power supply voltage VSS 2;

a fifth p-channel transistor comprising: a source connected to a fourth power supply voltage VDD2, a gate connected to an output terminal of the sixth inverter, and a drain;

a sixth p-channel transistor comprising: a source connected to a fourth power supply voltage VDD2, a gate connected to an input terminal of the sixth inverter, and a drain;

a third n-channel transistor comprising: a drain connected to the drain of the fifth p-channel transistor, a gate connected to a first power supply voltage VDD1, and a source;

a fourth n-channel transistor comprising: a drain connected to the drain of the sixth p-channel transistor, a gate connected to a first power supply voltage VDD1, and a source;

a fifth n-channel transistor comprising: a drain connected to the source of the third n-channel transistor, a gate, and a source connected to a second power supply voltage VSS 1;

a sixth n-channel transistor comprising: a drain connected to the source of the fourth n-channel transistor and the gate of the fifth n-channel transistor, a gate connected to the drain of the fifth n-channel transistor, and a source connected to a second power supply voltage VSS 1;

a seventh inverter connected between the source of the third n-channel transistor and the second inverter, and including: a power input terminal connected to a first power supply voltage VDD1 and a ground input terminal connected to a second power supply voltage VSS 1; and

an eighth inverter connected between the drain of the sixth n-channel transistor and the first inverter, and including: a power input terminal connected to a first power supply voltage VDD1 and a ground input terminal connected to a second power supply voltage VSS 1.

20. The method of claim 19, wherein:

the fifth p-channel transistor and the sixth p-channel transistor are each a p-channel laterally diffused metal oxide semiconductor field effect transistor;

the third n-channel transistor and the fourth n-channel transistor are each an n-channel laterally diffused metal oxide semiconductor field effect transistor; and

the fifth n-channel transistor and the sixth n-channel transistor are each n-channel metal oxide semiconductor field effect transistors, and wherein VSS1 is 0 volts, VDD1 is 6 volts, VSS2 is 17 volts, and VDD2 is 23 volts.

Technical Field

The present disclosure relates generally to electronic circuits and, more particularly, to an apparatus and method for reducing output skew and transition delay of a level shifter.

Background

A Power Management Integrated Circuit (PMIC) may include multiple supply voltages and power management functions within a single Integrated Circuit (IC). The PMIC may include a high voltage level shifter circuit.

High voltage level shifter circuits (e.g., laterally diffused Metal Oxide Semiconductor Field Effect Transistor (MOSFET) (LDMOS), extended drain MOSFET (demos)) use large and slow high voltage devices to handle large voltage differences (e.g., from 0 volts (V) to 6V, for example, and from 17V to 23V, for example). Due to the cross-coupled transistor pair structure, the positive and negative output transitions experience large skew over process, voltage, and temperature (PVT) variations. Such large skew may cause timing problems for subsequent blocks/stages of the circuit. In addition, the slower output transition edges limit overall speed.

Disclosure of Invention

The present disclosure provides an apparatus and method for reducing output skew and transition delay of a level shifter.

According to one embodiment, an apparatus comprises: a level shifter circuit configured to output voltages Vo1+ and Vo 1-; and an output calibration circuit configured to output voltages Vo + and Vo-triggered by edges of a combination of Vo1+ and Vo1-, and wherein Vo + and Vo-are set by high states of Vo1+ and Vo1-, prior to a transition to an input of the level shifter circuit.

According to one embodiment, a method comprises: outputting, by the output calibration circuit, voltages Vo + and Vo-triggered by the combined edges of Vo1+ and Vo 1-; and wherein Vo + and Vo-are set by the high states of Vo1+ and Vo1 prior to a transition to the input of the level shifter circuit.

According to the present disclosure, output skew and transition delay of a level shifter may be reduced by an apparatus and method according to embodiments.

Drawings

The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a diagram of a low voltage to high voltage level shifter;

FIG. 2 is a timing diagram of the low voltage to high voltage level shifter of FIG. 1;

FIG. 3 is a diagram of a high-to-low voltage level shifter;

FIG. 4 is a timing diagram of the high-to-low voltage level shifter of FIG. 3;

FIG. 5 is a graphical representation of voltage transitions of a low-to-high voltage level shifter and a high-to-low voltage level shifter;

FIG. 6 is a diagram of a low voltage to high voltage level shifter, according to one embodiment;

FIG. 7 is a diagram of an output calibration device of the low-voltage to high-voltage level shifter of FIG. 6, according to one embodiment;

FIG. 8 is a timing diagram of the low to high voltage level shifter of FIG. 6 according to one embodiment;

FIG. 9 is a timing diagram of the low to high voltage level shifter of FIG. 6 according to one embodiment;

FIG. 10 is a diagram of a high voltage to low voltage level shifter according to one embodiment; and

FIG. 11 is a flow diagram of a method of calibrating an output of a voltage level shifter, according to one embodiment.

Detailed Description

Fig. 1 is a diagram of a low voltage to high voltage level shifter 100.

Referring to fig. 1, a low-to-high voltage level shifter 100 includes: inverter 101, first n-channel ldmos (NLDMOS) transistor 103, second NLDMOS transistor 105, first p-channel ldmos (PLDMOS) transistor 107, second PLDMOS transistor 109, first p-channel mosfet (PMOS) transistor 111, second PMOS transistor 113, first buffer 115, and second buffer 117.

The inverter 101 includes: an input for receiving a voltage input signal In +, a power input for receiving a first power supply voltage VDD1, a ground input for receiving a second power supply voltage VSS1, and an output for outputting an output voltage In-, wherein In-is an inverted signal of In +. The first NLDMOS transistor 103 includes: a drain terminal, a gate terminal connected to the output terminal of the inverter 101, and a source terminal connected to the second power supply voltage VSS 1. The second NLDMOS transistor 105 includes: a drain terminal, a gate terminal connected to the input terminal of the inverter 101, and a source terminal connected to the second power supply voltage VSS 1. The first PLDMOS transistor 107 includes: a drain terminal connected to the drain terminal of the first NLDMOS transistor 103, a gate terminal connected to the third supply voltage VSS2, and a source terminal. The second PLDMOS transistor 109 includes: a drain terminal connected to the drain terminal of the second NLDMOS transistor 105, a gate terminal connected to the third power supply voltage VSS2, and a source terminal. The first PMOS transistor 111 includes: a drain terminal connected to the source terminal of the first PLDMOS transistor 107, a gate terminal, and a source terminal connected to a fourth power supply voltage VDD 2. The second PMOS transistor 113 includes: a drain terminal connected to the source terminal of second PLDMOS transistor 109, a gate terminal connected to the drain terminal of first PMOS transistor 111 and the source terminal of first PLDMOS transistor 107, and a source terminal connected to fourth power supply voltage VDD 2. The first buffer 115 includes: an input terminal connected to a source terminal of the first PLDMOS transistor 107, a drain terminal of the first PMOS transistor 111, and a gate terminal of the second PMOS transistor 113, a power supply input terminal connected to the fourth power supply voltage VDD2, a ground input terminal connected to the third power supply voltage VSS2, and an output terminal for outputting a voltage Vo +. The second buffer 117 includes: an input terminal connected to a source terminal of the second PLDMOS transistor 109, a gate terminal of the first PMOS transistor 111, and a drain terminal of the second PMOS transistor 113, a power supply input terminal connected to the fourth power supply voltage VDD2, a ground input terminal connected to the third power supply voltage VSS2, and an output terminal for outputting a voltage Vo-, where Vo-is an inverted signal of Vo +. However, it is to be understood that the n-channel transistors 103, 105 each being an NLDMOS transistor, the p-channel transistors 107, 109 each being a PLDMOS transistor, and the p-channel transistors 111, 113 each being a PMOS transistor are merely one example, and the specific types of the n-channel transistors 103, 105, p-channel transistors 107, 109, 111, 113 are not limited thereto and may be varied as needed.

Fig. 2 is a timing diagram of the low-to-high voltage level shifter 100 of fig. 1.

Referring to fig. 2, the low-to-high voltage level shifter 100 has a large output skew due to weak cross-coupled transistor pairs and large high-voltage device parasitics. The output skew varies over different PVTs. Output skew (duration of falling edge of voltage signal (Td)_fall)<Duration of rising edge (Td) of voltage signal_rise) May lead to timing problems for subsequent stages. The timing performance or speed of the low-to-high voltage level shifter 100 is converted by the slower output (in this case Td)_rise) And (4) limiting.

Fig. 3 is a diagram of a high-to-low voltage level shifter 300.

Referring to fig. 3, the high-to-low voltage level shifter 300 includes: inverter 301, first PLDMOS transistor 303, second PLDMOS transistor 305, first NLDMOS transistor 307, second NLDMOS transistor 309, first n-channel mosfet (NMOS) transistor 311, second NMOS transistor 313, first buffer 315, and second buffer 317.

The inverter 301 includes: an input for receiving a voltage input signal In +, a power input for receiving a first power supply voltage VDD2, a ground input for receiving a second power supply voltage VSS2, and an output for outputting an output voltage In-, wherein In-is an inverted signal of In +. The first PLDMOS transistor 303 includes: a drain terminal, a gate terminal connected to the output terminal of the inverter 301, and a source terminal connected to the first power voltage VDD 2. The second PLDMOS transistor 305 includes: a drain terminal, a gate terminal connected to the input terminal of the inverter 301, and a source terminal connected to the first power supply voltage VDD 2. The first NLDMOS transistor 307 includes: a drain terminal connected to the drain terminal of the first PLDMOS transistor 303, a gate terminal connected to the third power supply voltage VDD1, and a source terminal. The second NLDMOS transistor 309 includes: a drain terminal connected to the drain terminal of second PLDMOS transistor 305, a gate terminal connected to third supply voltage VDD1, and a source terminal. The first NMOS transistor 311 includes: a drain terminal connected to the source terminal of the first NLDMOS transistor 307, a gate terminal, and a source terminal connected to a fourth power supply voltage VSS 1. The second NMOS transistor 313 includes: a drain terminal connected to the source terminal of the second NLDMOS transistor 309 and the gate terminal of the first NMOS transistor 311, a gate terminal connected to the drain terminal of the first NMOS transistor 311 and the source terminal of the first NLDMOS transistor 307, and a source terminal connected to the fourth power supply voltage VSS 1. The first buffer 315 includes: an input terminal connected to the source terminal of the first NLDMOS transistor 307, the drain terminal of the first NMOS transistor 311, and the gate terminal of the second NMOS transistor 313, a power supply input terminal connected to the third power supply voltage VDD1, a ground input terminal connected to the fourth power supply voltage VSS1, and an output terminal for outputting a voltage Vo +. The second buffer 317 includes: an input terminal connected to a source terminal of the second NLDMOS transistor 309, a gate terminal of the first NMOS transistor 311, and a drain terminal of the second NMOS transistor 313, a power supply input terminal connected to a third power supply voltage VDD1, a ground input terminal connected to a fourth power supply voltage VSS1, and an output terminal for outputting a voltage Vo-, where Vo-is an inverted signal of Vo +. However, it is to be understood that the p-channel transistors 303, 305 are each a PLDMOS transistor, the n-channel transistors 307, 309 are each an NLDMOS transistor, and the n-channel transistors 311, 313 are each an NMOS transistor is merely an example, and the specific types of the p-channel transistors 303, 305, n-channel transistors 307, 309, 311, 313 are not limited thereto and may be varied as needed.

Fig. 4 is a timing diagram of the high-to-low voltage level shifter 300 of fig. 3.

Referring to fig. 4, the output skew of the high-to-low voltage level shifter 300 varies over PVT. Output skew (Td)_fall>Td_rise) May lead to timing problems for subsequent stages. The speed of the high-to-low voltage level shifter 300 may be converted by the slower output (in this case, Td)_fall) And (4) limiting.

Fig. 5 is a graphical representation of voltage transitions of a low-to-high voltage level shifter and a high-to-low voltage level shifter.

Referring to fig. 5, the low-to-high voltage level shifter and the high-to-low voltage level shifter may each have a power supply voltage VSS1 of 0V, a power supply voltage VDD1 of 6V, a power supply voltage VSS2 of 17V, and a power supply voltage VDD2 of 23V. However, the present disclosure is not limited to these particular voltages, and the present disclosure may use different voltages for VSS1, VDD1, VSS2, and VDD 2.

Fig. 6 is a diagram of a low-to-high voltage level shifter 600 according to one embodiment.

Referring to fig. 6, a low-to-high voltage level shifter 600 includes: inverter 601, first NLDMOS transistor 603, second NLDMOS transistor 605, first PLDMOS transistor 607, second PLDMOS transistor 609, first PMOS transistor 611, second PMOS transistor 613, first buffer 615, second buffer 617, and output calibration device 619.

The inverter 601 includes: an input for receiving a voltage input signal In +, a power input for receiving a first power supply voltage VDD1, a ground input for receiving a second power supply voltage VSS1, and an output for outputting an output voltage In-, wherein In-is an inverted signal of In +. The first NLDMOS transistor 603 includes: a drain terminal, a gate terminal connected to the output terminal of the inverter 601, and a source terminal connected to the second power supply voltage VSS 1. The second NLDMOS transistor 605 includes: a drain terminal, a gate terminal connected to the input terminal of the inverter 601, and a source terminal connected to the second power supply voltage VSS 1. The first PLDMOS transistor 607 includes: a drain terminal connected to the drain terminal of the first NLDMOS transistor 603, a gate terminal connected to the third supply voltage VSS2, and a source terminal. The second PLDMOS transistor 609 includes: a drain terminal connected to the drain terminal of second NLDMOS transistor 605, a gate terminal connected to third supply voltage VSS2, and a source terminal. The first PMOS transistor 611 includes: a drain terminal connected to the source terminal of the first PLDMOS transistor 607, a gate terminal, and a source terminal connected to a fourth power supply voltage VDD 2. The second PMOS transistor 613 includes: a drain terminal connected to the source terminal of the second PLDMOS transistor 609 and the gate terminal of the first PMOS transistor 611, a gate terminal connected to the drain terminal of the first PMOS transistor 611 and the source terminal of the first PLDMOS transistor 607, and a source terminal connected to a fourth power supply voltage VDD 2. The first buffer 615 includes: an input terminal connected to the source terminal of the first PLDMOS transistor 607, the drain terminal of the first PMOS transistor 611, and the gate terminal of the second PMOS transistor 613, a power supply input terminal connected to the fourth power supply voltage VDD2, a ground input terminal connected to the third power supply voltage VSS2, and an output terminal for outputting a voltage Vo1 +. The second buffer 617 includes: an input terminal connected to a source terminal of the second PLDMOS transistor 609, a gate terminal of the first PMOS transistor 611, and a drain terminal of the second PMOS transistor 613, a power input terminal connected to a fourth power voltage VDD2, a ground input terminal connected to a third power voltage VSS2, and an output terminal for outputting a voltage Vo1-, wherein Vo 1-is an inverted signal of Vo1 +. The output calibration device 619 includes: a first input terminal connected to an output terminal of the first buffer 615 to receive Vo1+ as the input voltage In +, a second input terminal connected to an output terminal of the second buffer 617 to receive Vo 1-as the input voltage In-, a first output terminal for outputting the output voltage Vo +, and a second output terminal for outputting the output voltage Vo-. However, it is to be understood that the n- channel transistors 603, 605 are each NLDMOS transistors, the p- channel transistors 607, 609 are each PLDMOS transistors, and the p- channel transistors 611, 613 are each PMOS transistors are merely one example, and the specific types of the n- channel transistors 603, 605, the p- channel transistors 607, 609, 611, 613 are not limited thereto and may be varied as needed.

The low to high voltage level shifter 600 provides minimal output skew and outputs Vo + and Vo-, where Vo + and Vo-have similar delays (e.g., Td) independent of PVT variations_fall＝Td_rise). The low-to-high voltage shifter 600 provides faster switching speed (e.g., shorter delay, Td)_fall/rise)。

FIG. 7 is a diagram of an output calibration apparatus 619 of the low-voltage to high-voltage level shifter 600 of FIG. 6, according to one embodiment.

Referring to fig. 7, the output calibration apparatus 619 includes: a first inverter 701, a second inverter 703, a third inverter 705, a fourth inverter 707, a first NAND (NAND) gate 709, a second NAND gate 711, a third NAND gate 713, a fourth NAND gate 715, and a reset-set (RS) flip-flop 717.

The first inverter 701 includes: an input terminal for receiving the voltage Vo1+ as an input voltage In +, and an output terminal for outputting an inverted signal of Vo1 +. The second inverter 703 includes: an input terminal for receiving the voltage Vo 1-as the input voltage In-, and an output for outputting an inverted signal of Vo 1-. The third inverter 705 includes: an input terminal connected to an output terminal of the first inverter 701, and an output terminal for outputting an inverted signal of an output of the first inverter 701, wherein the third inverter 705 provides a Delay (DLY). The fourth inverter 707 includes: an input terminal connected to the output terminal of the second inverter 703, and an output terminal for outputting an inverted signal of the output of the second inverter 703, wherein the fourth inverter 707 provides a Delay (DLY).

The first nand gate 709 includes: a first input terminal connected to the output terminal of the first inverter 701, a second input terminal connected to the output terminal of the third inverter 705, and an output terminal. The second nand gate 711 includes: a first input terminal connected to the output terminal of the second inverter 703, a second input terminal connected to the output terminal of the fourth inverter 707, and an output terminal. The third nand gate 713 includes: a first input connected to the output of the second inverter 703, a second input connected to the output of the first nand gate 709, and an output. The fourth nand gate 715 includes: a first input connected to the output of the first inverter 701, a second input connected to the output of the second nand gate 711, and an output. The logic circuit composed of the first nand gate 709, the second nand gate 711, the third nand gate 713, and the fourth nand gate 715 can reduce output skew and conversion delay between the input voltage In + and the input voltage In-, and the specific configuration of the logic circuit shown In fig. 7 is only one example, and the configuration of the logic circuit is not limited thereto. The RS flip-flop 717 can latch reduced output skew and transition delay between the input voltage In + and the input voltage In-, and includes: a first input (R) connected to an output of the third nand gate 713 to receive the Reset Signal (RST), a second input (S) connected to an output of the fourth nand gate 715 to receive the SET Signal (SET), a first output (QB) for outputting the voltage Vo-, and a second output (Q) for outputting the voltage Vo +.

Fig. 8 is an illustration of a timing diagram of the low-to-high voltage level shifter 600 of fig. 6.

Referring to FIG. 8, Td_fallEqual to Td_rise。

The present disclosure is not limited to the use of nand gates in the output calibration device 619 of figure 7. The present disclosure includes any combination of logic gates implementing equivalent logic of the output calibration apparatus 619 of fig. 7 and satisfies the timing diagram of fig. 8.

FIG. 9 is a timing diagram of the low-to-high voltage level shifter 600 of FIG. 6 according to one embodiment.

Referring to FIG. 9, both outputs Vo + and Vo-are triggered by the earlier edges (in this case, falling edges) of inputs Vo1+ and Vo1-, respectively, which results in no output skew and less delay. When there is initially no input transition, the high states of the inputs Vo1+ and Vo 1-are used to set the output state.

Fig. 10 is a diagram of a high-voltage to low-voltage level shifter 1000 according to one embodiment.

Referring to fig. 10, the high-to-low voltage level shifter 1000 includes: a first inverter 1001, a first PLDMOS transistor 1003, a second PLDMOS transistor 1005, a first NLDMOS transistor 1007, a second NLDMOS transistor 1009, a first NMOS transistor 1011, a second NMOS transistor 1013, a second inverter 1015, a third inverter 1017, and an output calibration means 1019.

The first inverter 1001 includes: an input for receiving a voltage input signal In +, a power input for receiving a first power supply voltage VDD2, a ground input for receiving a second power supply voltage VSS2, and an output for outputting an output voltage In-, wherein In-is an inverted signal of In +. The first PLDMOS transistor 1003 includes: a drain terminal, a gate terminal connected to an output terminal of the first inverter 1001, and a source terminal connected to the first power voltage VDD 2. The second PLDMOS transistor 1005 includes: a drain terminal, a gate terminal connected to an input terminal of the first inverter 1001, and a source terminal connected to the first power voltage VDD 2. The first NLDMOS transistor 1007 includes: a drain terminal connected to the drain terminal of first PLDMOS transistor 1003, a gate terminal connected to third supply voltage VDD1, and a source terminal. The second NLDMOS transistor 1009 includes: a drain terminal connected to the drain terminal of second PLDMOS transistor 1005, a gate terminal connected to third supply voltage VDD1, and a source terminal. The first NMOS transistor 1011 includes: a drain terminal connected to the source terminal of the first NLDMOS transistor 1007, a gate terminal, and a source terminal connected to a fourth power supply voltage VSS 1. The second NMOS transistor 1013 includes: a drain terminal connected to the source terminal of the second NLDMOS transistor 1009 and the gate terminal of the first NMOS transistor 1011, a gate terminal connected to the drain terminal of the first NMOS transistor 1011 and the source terminal of the first NLDMOS transistor 1007, and a source terminal connected to the fourth power supply voltage VSS 1. The second inverter 1015 includes: an input terminal connected to a source terminal of the first NLDMOS transistor 1007, a drain terminal of the first NMOS transistor 1011, and a gate terminal of the second NMOS transistor 1013, a power supply input terminal connected to the third power supply voltage VDD1, a ground input terminal connected to the fourth power supply voltage VSS1, and an output terminal for the output voltage Vo 1-. The third inverter 1017 includes: an input terminal connected to a source terminal of the second NLDMOS transistor 1009, a gate terminal of the first NMOS transistor 1011, and a drain terminal of the second NMOS transistor 1013, a power supply input terminal connected to the third power supply voltage VDD1, a ground input terminal connected to the fourth power supply voltage VSS1, and an output terminal for outputting a voltage Vo1+, wherein Vo 1-is an inverted signal of Vo1 +. The output calibration means 1019 includes: a first input terminal connected to an output terminal of the third inverter 1017 to receive Vo1+ as the input voltage In +, a second input terminal connected to an output terminal of the second inverter 1015 to receive Vo 1-as the input voltage In-, a first output terminal for outputting the output voltage Vo +, and a second output terminal for outputting the output voltage Vo-. However, it is to be understood that the p-channel transistors 1003, 1005 are each a PLDMOS transistor, the n-channel transistors 1007, 1009 are each a NLDMOS transistor, and the n-channel transistors 1011, 1013 are each an NMOS transistor is merely one example, and the specific types of the p-channel transistors 1003, 1005, n-channel transistors 1007, 1009, 1011, 1013 are not limited thereto and may be changed as needed.

The timing diagram of fig. 10 is the same as the timing diagram of fig. 8.

In fig. 10, a second inverter 1015 and a third inverter 1017 are used instead of the buffers (i.e., the first buffer 615 and the second buffer 617) in fig. 6.

The output calibration means 1019 may be used to minimize the output skew and transition delay of the level shifter. The earlier transition edges of the inputs In + and In-are used to trigger the outputs Vo + and Vo-. When there is no input transition, the input level information (e.g., high state) is used to guarantee the output state. In case a similar signal calibration is required, such a calibration method provided by the output calibration means 1019 may be used.

According to one embodiment, the high-to-low voltage level shifter 1000 may be part of a PMIC for providing signals to a display device (e.g., a Liquid Crystal Display (LCD) driver).

According to one embodiment, the high-to-low voltage level shifter with output calibration 1000 includes: a level shifter circuit having outputs Vo1+ and Vo 1-; and an output calibration circuit electrically connected to the output of the level shifter circuit, wherein the output calibration circuit has outputs Vo + and Vo-triggered by earlier edges of Vo1+ or Vo1-, and wherein the outputs Vo + and Vo-are set by high states of Vo1+ and Vo 1-when there is initially no input transition.

FIG. 11 is a flow diagram of a method of calibrating an output of a voltage level shifter, according to one embodiment.

Referring to fig. 11, in step 1101, a voltage level is shifted by a voltage level shifter. The voltage level shifter may be the same as or similar to the low voltage to high voltage level shifter 100 of fig. 1. The voltage level shifter may be the same as or similar to the high-voltage to low-voltage level shifter 300 of fig. 3. The voltage level shifter may be the same as or similar to the low voltage to high voltage level shifter 600 of fig. 6. The voltage level shifter may be the same as or similar to the high-voltage to low-voltage level shifter 1000 of fig. 10.

In step 1103, the output of the shifted voltage level is calibrated by the voltage level shifter.

The voltage level shifter according to various embodiments may be part of an electronic device. The electronic device according to various embodiments may be one of various types of electronic devices. The electronic device may include, for example, a portable communication device (e.g., a smartphone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, or a home appliance. According to the embodiments of the present disclosure, the electronic apparatus is not limited to the above-described electronic apparatus.

While specific embodiments of the present disclosure have been described in the detailed description thereof, the disclosure may be modified in various forms without departing from the scope of the disclosure. Accordingly, the scope of the present disclosure should be determined not only based on the described embodiments, but also based on the appended claims and their equivalents.