阅读说明：本技术 电平移位器电路 (Level shifter circuit ) 是由 E·乔达 J·贝克尔 于 2019-03-05 设计创作，主要内容包括：电平移位器(300)包括信号输入端子(342)、第一信号输出节点(350)、第一晶体管(308)、第二晶体管(314)、第三晶体管(332)和第一电容器(334)。第一晶体管(308)包括耦合到信号输入端子(342)的控制端子(352)。第二晶体管(314)包括耦合到第一晶体管(308)的输入端子(360)的输出端子(362)。第一电容器(334)包括耦合到第二晶体管(314)的输入端子(363)的底板(364)。第三晶体管(332)包括耦合到第一电容器(334)的顶板(392)的控制端子(366)和耦合到第一信号输出节点(350)的输出端子(368)。(A level shifter (300) includes a signal input terminal (342), a first signal output node (350), a first transistor (308), a second transistor (314), a third transistor (332), and a first capacitor (334). The first transistor (308) includes a control terminal (352) coupled to the signal input terminal (342). The second transistor (314) includes an output terminal (362) coupled to the input terminal (360) of the first transistor (308). The first capacitor (334) includes a bottom plate (364) coupled to an input terminal (363) of the second transistor (314). The third transistor (332) includes a control terminal (366) coupled to the top plate (392) of the first capacitor (334) and an output terminal (368) coupled to the first signal output node (350).)

1. A level shifter, comprising:

a signal input terminal;

a first signal output node;

a first transistor comprising a control terminal coupled to the signal input terminal;

a second transistor comprising an output terminal coupled to an input terminal of the first transistor;

a first capacitor comprising a bottom plate coupled to an input terminal of the second transistor; and

a third transistor, comprising: a control terminal coupled to a top plate of the first capacitor; and an output terminal coupled to the first signal output node.

2. The level shifter of claim 1, further comprising a resistor, the resistor comprising: a first terminal coupled to the top plate of the first capacitor; and a second terminal coupled to the first power supply terminal.

3. The level shifter of claim 1, wherein an input terminal of the third transistor is coupled to a first power supply terminal.

4. The level shifter of claim 1, further comprising:

a first inverter including input terminals coupled to the signal input terminals;

a second output node;

a fourth transistor comprising a control terminal coupled to an output terminal of the first inverter;

a fifth transistor comprising an output terminal coupled to an input terminal of the fourth transistor;

a second capacitor comprising a bottom plate coupled to an input terminal of the fifth transistor; and

a sixth transistor, comprising: a control terminal coupled to a top plate of the second capacitor; and an output terminal coupled to the second signal output node.

5. The level shifter of claim 4, wherein an input terminal of the sixth transistor is coupled to a first power supply terminal.

6. The level shifter of claim 4, further comprising a resistor, the resistor comprising: a first terminal coupled to the top plate of the second capacitor; and a second terminal coupled to the first power supply terminal.

7. The level shifter of claim 4, further comprising:

a second inverter comprising: an input terminal coupled to the first output node; and an output terminal coupled to the second output node;

a third inverter comprising: an input terminal coupled to the second output node; and an output terminal coupled to the first output node.

8. The level shifter of claim 4, wherein: the input terminal of the second transistor is coupled to the second output node; and the input terminal of the fifth transistor is coupled to the first output node.

9. A level shifter, comprising:

an input circuit coupled to the low voltage rail and configured to receive an input signal;

an output circuit coupled to a high voltage rail and configured to generate an output signal at a voltage of the high voltage rail; and

an interface circuit configured to transmit a signal from the input circuit to the output circuit;

wherein the output circuit comprises:

a first output node; and

a first boost circuit comprising a first transistor capacitively coupled to the interface circuit, the first transistor configured to drive the voltage of the high voltage rail onto the first output node in response to a first signal received from the interface circuit.

10. The level shifter of claim 9, wherein the output circuit comprises a second output node and the interface circuit is configured to drive the first signal onto the second output node.

11. The level shifter of claim 10, wherein the output circuit comprises a first inverter configured to drive the first output node in response to a signal present on the second output node.

12. The level shifter of claim 9, wherein the output circuit comprises:

a second output node; and

a second boost circuit comprising a second transistor capacitively coupled to the interface circuit, the second transistor configured to drive the voltage of the high voltage rail onto the second output node in response to a second signal received from the interface circuit.

13. The level shifter of claim 12, wherein the interface circuit is configured to drive the second signal onto the first output node.

14. The level shifter of claim 9, wherein the output circuit comprises a second inverter configured to drive the second output node in response to a signal present on the first output node.

15. The level shifter of claim 9, wherein the first boost circuit comprises: a capacitor coupling the interface circuit to a gate terminal of the first transistor; and a resistor coupling the gate terminal of the first transistor to the high voltage rail.

16. A switched mode power supply, comprising:

a power transistor configured to drive an inductor;

a gate driver coupled to the power transistor and configured to drive a control terminal of the power transistor; and

a level shifter coupled to the gate driver, the level shifter comprising: a low-voltage rail; a high voltage rail; an input circuit powered via the low voltage rail; an interface circuit coupled to the input circuit; an output circuit coupled to the interface circuit and powered via the high voltage rail.

The output circuit includes:

a first boost circuit comprising a first transistor capacitively coupled to the interface circuit, the first transistor configured to switchably connect the high voltage rail to a first output node in response to a first signal received from the interface circuit; and

a second boost circuit comprising a second transistor capacitively coupled to the interface circuit, the second transistor configured to switchably connect the high voltage rail to a second output node in response to a second signal received from the interface circuit.

17. The switched mode power supply of claim 16, wherein the interface circuit is configured to: driving the first signal onto the second output node; and driving the second signal onto the first output node.

18. The switched mode power supply of claim 16, wherein the output circuit comprises: a first inverter configured to drive the first output node in response to a signal present on the second output node; and a second inverter configured to drive the second output node in response to a signal present on the first output node.

19. The switched mode power supply of claim 16, wherein the first boost circuit comprises: a capacitor coupling the interface circuit to a gate terminal of the first transistor; and a resistor coupling the gate terminal of the first transistor to the high voltage rail.

20. The switched mode power supply of claim 16, wherein the second boost circuit comprises: a capacitor coupling the interface circuit to a gate terminal of the second transistor; and a resistor coupling the gate terminal of the second transistor to the high voltage rail.

Background

Electronic systems often have circuits powered by different supply voltages or circuits that require different signal levels to activate circuit elements. In such systems, level shifting circuits (level shifters) are used to convert signals from one voltage level to another. For example, a level shifter may be used to convert a signal from a lower voltage to a higher voltage, or to convert a signal from a higher voltage to a lower voltage. In a switched mode power supply, a level shifter is used to transition/convert a control signal to a voltage that enables the power transistor of the power supply to have a desired drive capability.

Disclosure of Invention

In one example, a level shifter includes a signal input terminal, a first signal output node, a first transistor, a second transistor, a third transistor, and a first capacitor. The first transistor includes a control terminal coupled to the signal input terminal. The second transistor includes an output terminal coupled to the input terminal of the first transistor. The first capacitor includes a bottom plate coupled to the input terminal of the second transistor. The third transistor includes a control terminal coupled to a top plate of the first capacitor and an output terminal coupled to the first signal output node.

In another example, a level shifter includes an input circuit, an output circuit, and an interface circuit. An input circuit is coupled to the low voltage rail and configured to receive an input signal. An output circuit is coupled to the high voltage rail and configured to generate an output signal at a voltage of the high voltage rail. The interface circuit is configured to transmit a signal from the input circuit to the output circuit. The output circuit includes a first output node and a first boost circuit. The first boost circuit includes a first transistor capacitively coupled to the interface circuit. The first transistor is configured to drive a voltage of the high voltage rail onto a first output node in response to a first signal received from the interface circuit.

In yet another example, a switched mode power supply includes a power transistor, a gate driver, and a level shifter. The power transistor is configured to drive the inductor. The gate driver is coupled to the power transistor and configured to drive a control terminal of the power transistor. The level shifter is coupled with the gate driver. The level shifter comprises a low-voltage rail, a high-voltage rail, an input circuit, an interface circuit and an output circuit. The input circuit is powered via the low voltage rail. The interface circuit is coupled to the input circuit. An output circuit is coupled to the high voltage rail and the interface circuit. The output circuit includes a first boost circuit and a second boost circuit. The first boost circuit includes a first transistor capacitively coupled to the interface circuit. The first transistor is configured to switchably connect the high voltage rail to the first output node in response to a first signal received from the interface circuit. The second boost circuit includes a second transistor capacitively coupled to the interface circuit. The second transistor is configured to switchably connect the high voltage rail to the second output node in response to a second signal received from the interface circuit.

Drawings

Fig. 1 shows a block diagram of an example of a switched mode power supply comprising a level shifter according to the present description.

Fig. 2 shows a block diagram of an example of a level shifter according to the present description.

Fig. 3 shows a schematic diagram of an example of a level shifter according to the present description.

Fig. 4 and 5 show timing diagrams of signals in a level shifter according to the present description.

Detailed Description

In this specification, the term "coupled" means either an indirect or direct wired or wireless connection. Thus, if a first device couples to a second device, that connection may be through a direct connection or through an indirect connection via other devices and connections. In addition, in this specification, the statement "based on" means "based at least in part on". Thus, if X is based on Y, X may be a function of Y and any number of other factors.

Level shifters enable communication between circuits operating at different power supply voltages. In order to make the circuit have high-speed characteristics, it is desirable to reduce the propagation delay by the level shifter. Level shifter embodiments include various circuits to reduce propagation delay. Some level shifter embodiments include a feed forward circuit that reduces delay by capacitively coupling an input circuit to an output circuit of the level shifter. The feed forward capacitor provides direct dynamic control from input to output. However, the reduction in propagation delay decreases as the input circuit supply voltage decreases, and embodiments require high voltage capacitors that are not available for all semiconductor processes or increase manufacturing costs. Furthermore, a clamp circuit is required to reduce the possibility of overvoltage damage in the input circuit.

Other level shifter implementations add a set/reset latch to the output circuit. Such embodiments rely on the discharge path through the low voltage circuit to quickly switch the logic state of the high voltage circuit output. Resolving the meta-stability in the latch requires the addition of a synchronization circuit that operates in the high voltage domain of the level shifter, which can be a problem.

The level shifter described herein includes a boost circuit in the high voltage circuit to reduce the propagation delay of the low-to-high output signal transition. The boost circuit uses a path through the transistors of the low voltage circuit to trigger a fast charge of the high voltage circuit output. No high voltage capacitors and associated clamping or latch synchronization circuits are required. Since the boost circuit rapidly pulls up the high voltage output, the size of various other components of the level shifter (e.g., the high voltage pull-up and clamping devices) may be reduced.

Fig. 1 shows a block diagram of an example of a switched mode power supply 100 comprising a level shifter according to the present description. The switched mode power supply 100 includes a controller 102, a high side level shifter 104, a low side level shifter 106, a high side driver 108, a low side driver 110, a high side power transistor 112, a low side power transistor 114, and an inductor 116. For clarity, the switched mode power supply 100 may include additional elements omitted from fig. 1.

The controller 102 generates output pulses that control the switching of the low-side power transistor 114 and the high-side power transistor 112. For example, the controller 102 may compare the voltage at the load side of the inductor 116 to a reference voltage to generate an error signal and apply the error signal to control the pulse width modulator. The output of the pulse width modulator is a pulse that controls the switching of the low side power transistor 114 and the high side power transistor 112.

The high-side power transistor 112 and the low-side power transistor 114 each connect an inductor 116 to the power supply rail under control of an output signal generated by the controller 102. The high-side power transistor 112 and the low-side power transistor 114 may be n-channel metal oxide semiconductor transistors (MOSFETs). A low side power transistor 114 is coupled to the low side driver 110. The low side driver 110 provides the current needed to quickly charge the gate capacitance of the low side power transistor 114. A low side driver 110 is coupled to the low side level shifter 106. The low side level shifter 106 shifts the signals received from the controller 102 to a higher voltage to effectively drive the low side power transistor 114. Because the low-side power transistor 114 is coupled to ground 118, the high-voltage circuitry of the low-side level shifter 106 may also be referenced to ground.

The high-side driver 108 is coupled to a high-side power transistor 112. The high-side driver 108 provides the current needed to quickly charge the gate capacitance of the high-side power transistor 112. A high side driver 108 is coupled to the high side level shifter 104. The high-side level shifter 104 shifts the signal received from the controller 102 to a higher voltage to effectively drive the high-side power transistor 112. Because high-side power transistor 112 is not referenced to ground 118, the high-voltage circuitry of high-side level shifter 104 may also not be referenced to ground 118, while the low-voltage circuitry of high-side level shifter 104 may be referenced to ground 118. The high side level shifter 104 includes a boost circuit that reduces the rise time of the output signal of the high side level shifter 104.

Fig. 2 shows a block diagram of a level shifter 200 according to the present description. Level shifter 200 may be an implementation of high-side level shifter 104. The level shifter 200 includes an input circuit 202, an interface circuit 204, and an output circuit 206. The input circuit 202 is coupled to a low voltage power supply. For example, the input circuit 202 may be powered by a 1.8 volt power supply. The input circuit 202 receives an input signal 214 and provides the received signal to the output circuit 206 via the interface circuit 204. The input circuit 202 may provide an inverted version (e.g., signal 224) and a non-inverted version (e.g., signal 226) of the received signal 214 to the interface circuit 204.

Interface circuit 204 includes a clamp that passes the output signal (224 and 226) of input circuit 202 to output circuit 206 and limits the voltage of the signal received by output circuit 206 from not falling below the reference voltage (e.g., ground) of the high voltage power supply that powers output circuit 206. The voltage of the high voltage power supply may be, for example, 10 volts and the ground reference provided by the high voltage power supply may be at a higher voltage than the ground reference provided by the low voltage power supply coupled to the input circuit 202.

The output circuit 206 includes a cross-coupling circuit 208, the cross-coupling circuit 208 receiving a signal 220 and a signal 222 provided by the interface circuit 204 and driving an output of the output circuit 206 to a voltage provided by the high voltage power supply in response to the received signals. Cross-coupling circuit 208 includes a boost circuit 210 and a boost circuit 212. Boost circuit 210 and boost circuit 212 are capacitively coupled to the output of interface circuit 204. Due to cross-coupling, the falling edge of signal 220 causes output 218 to be pulled up quickly by boost circuit 210, while the falling edge of signal 222 causes output 216 to be pulled up quickly by boost circuit 210. Therefore, the boost circuit 210 and the boost circuit 212 increase the output edge rate of the level shifter 200 and reduce the propagation delay.

Fig. 3 shows a schematic diagram of a level shifter 300 according to the present description. Level shifter 300 is one of several implementations of high-side level shifter 104 and level shifter 200. The level shifter 300 generates one or more output signals at a voltage higher than that of the input signal. Fig. 4 shows an example of signals received and output by the level shifter 300. Level shifter 300 includes an input terminal 342 for receiving an input signal generated using a "lower" supply voltage, and includes an output node 348 and an output node 350 for generating an output signal corresponding to the received input signal at a higher voltage. Fig. 4 shows an input signal 402 generated between the power supply rails VCC _ LOW and GND _ LOW. Signal 406 at output node 348 is an inverted version of signal 402, which signal 406 has a propagation delay t generated between power supply rails VCC _ UP and GND _ UP_d. The signal 404 at the output node 350 is a non-inverted version of the signal 402, the signal 404 having a propagation delay t generated between the power supply rails VCC _ UP and GND _ UP_d. In practice, the propagation delay between an edge of input signal 402 and edges of signals 404 and 406 may differ based on whether the edges of signals 404 and 406 rise or fall.

The level shifter 300 includes an input circuit 302, an interface circuit 304, and an output circuit 306, a signal input terminal 342, an inverting output node 348, and a non-inverting output node 350. The input circuit 302 is coupled to the low voltage rail 338 and the low voltage rail 340. Output circuit 306 is coupled to high voltage rail 344 and high voltage rail 346. The high voltage rail 344 may also be referred to as a high voltage power supply terminal. Input circuit 302 is one of several implementations of input circuit 202, interface circuit 304 is one of several implementations of interface circuit 204, and output circuit 306 is one of several implementations of output circuit 206.

Input circuit 302 includes transistor 308, inverter 310, and transistor 312. Transistor 308 and transistor 312 may be n-channel MOSFETs (possibly with drain extensions). The transistor 308 includes a control terminal 352 (e.g., a gate terminal) coupled to the signal input terminal 342 of the level shifter 300. The inverter 310 includes an input terminal 354 coupled to the signal input terminal 342 of the level shifter 300 and an output terminal 356 coupled to a control terminal 358 (e.g., a gate terminal) of the transistor 312.

The interface circuit 304 includes a transistor 314 and a transistor 316. Transistors 314 and 316 may be p-channel MOSFETs (possibly with drain extensions). An input terminal 360 (e.g., a drain terminal) of transistor 308 is coupled to an output terminal 362 (e.g., a drain terminal) of transistor 314. An input terminal 378 (e.g., a drain terminal) of the transistor 312 is coupled to an output terminal 374 (e.g., a drain terminal) of the transistor 316. An input terminal 363 (e.g., a source terminal) of the transistor 314 is coupled to the inverting output node 348. An input terminal 375 (e.g., a source terminal) of the transistor 316 is coupled to the non-inverting output node 350. Activating transistor 308 generates a current in transistor 314, and transistor 308 pulls the inverting output node 348 to the high voltage ground 346. Activating transistor 312 generates a current in transistor 316, and transistor 312 pulls non-inverting output node 350 to high voltage ground 346.

The output circuit 306 includes a cross-coupled circuit that drives the inverting output node 348 based on the state of the non-inverting output node 350 and drives the non-inverting output node 350 based on the state of the inverting output node 348. The cross-coupled circuit of output circuit 306 includes inverter 318, inverter 320, boost circuit 322, and boost circuit 324. Inverter 318 includes an output terminal 395 coupled to inverting output node 348 and an input terminal 394 coupled to non-inverting output node 350. Inverter 320 includes an output terminal 397 coupled to non-inverting output node 350 and an input terminal 396 coupled to inverting output node 348.

Boost circuit 322 includes transistor 326, capacitor 328, and resistor 330. Transistor 326 may be a p-channel MOSFET. Capacitor 328 capacitively couples transistor 326 to non-inverting output node 350 such that when non-inverting output node 350 is pulled down by transistor 312 via transistor 316, transistor 326 is momentarily activated to pull up inverting output node 348, thereby increasing the low-to-high transition rate (rising edge rate) of inverting output node 348. The capacitor 328 includes a bottom plate 376 coupled to the non-inverting output node 350 and a top plate 390 coupled to a control terminal 380 (e.g., a gate terminal) of the transistor 326. An input terminal 384 (e.g., a source terminal) of the transistor 326 is coupled to the high voltage rail 344. An output terminal 382 (e.g., a drain terminal) of the transistor 326 is coupled to the inverting output node 348. Resistor 330 includes a terminal 386 coupled to control terminal 380 of transistor 326 and a terminal 388 coupled to high voltage rail 344. Resistor 330 provides a reset for boost circuit 322.

The boost circuit 324 includes a transistor 332, a capacitor 334, and a resistor 336. Transistor 332 may be a p-channel MOSFET. Capacitor 334 capacitively couples transistor 332 to inverting output node 348 so that when inverting output node 348 is pulled down by transistor 308 via transistor 314, transistor 332 is momentarily activated to pull up non-inverting output node 350, thereby increasing the low-to-high transition rate (rising edge rate) of non-inverting output node 350. The capacitor 334 includes a bottom plate 364 coupled to the inverting output node 348 and a top plate 392 coupled to a control terminal 366 (e.g., a gate terminal) of the transistor 332. An input terminal 374 (e.g., a source terminal) of the transistor 332 is coupled to the high voltage rail 344. An output terminal 368 (e.g., a drain terminal) of the transistor 332 is coupled to the non-inverting output node 350. Resistor 336 includes a terminal 370 coupled to control terminal 366 of transistor 332 and a terminal 372 coupled to high voltage rail 344. Resistor 336 provides a reset for boost circuit 324.

Fig. 5 shows a timing diagram of signals in a level shifter according to the present description. In fig. 4, when the input signal 504 rises at edge 502, transistor 308 is activated and the signal 506 at the inverting output node 348 is pulled down quickly to the high voltage ground rail 346 via transistor 314. Pulling inverting output node 348 to ground momentarily pulls control terminal 366 of transistor 332 to high voltage ground rail 346 and activates transistor 332 to quickly pull non-inverting output node 350 up to high voltage rail 344, forming a fast rising edge 510 on signal 508. As illustrated by edge 512, in an embodiment of a level shifter that lacks boost circuit 324, the rising edge of signal 508 may be quite slow.

Accordingly, the boost circuit 322 and the boost circuit 324 increase the rising edge rate of the signals on the inverting output node 348 and the non-inverting output node 350, thereby reducing the propagation delay of the level shifter 300. The nominal voltage of capacitor 328 and capacitor 334 may be lower than the voltage of the capacitor used in the level shifter that capacitively couples the input circuit to the output circuit, which simplifies circuit fabrication. Since the level shifter 300 does not include set-reset latches on the inverting 348 and non-inverting 350 output nodes, no synchronization circuitry is needed to prevent metastability. Furthermore, because boost circuit 322 and boost circuit 324 provide high rising edge drive, the size of inverter 318, inverter 320, transistor 314, and transistor 316 may be reduced relative to some implementations of a level shifter.

The described embodiments may be modified and other embodiments may be modified within the scope of the claims.