阅读说明：本技术 一种芯片和终端 (Chip and terminal ) 是由 刘君 于 2020-06-30 设计创作，主要内容包括：本申请实施例提供了一种芯片和终端,涉及芯片技术领域。所述芯片包括：第一接口控制模块、第二接口控制模块、多路复用模块和共用物理层接口；第一接口控制模块和第二接口控制模块分别与多路复用模块耦合,第一接口控制模块和第二接口控制模块分别对应不同类型的物理层接口；多路复用模块与共用物理层接口通信耦合；其中,共用物理层接口用于接收来自外部芯片的第一数据,和/或用于向外部芯片发送第二数据。本申请实施例只需要设置一个物理层接口,即可实现第一接口控制模块对应的物理层接口和第二接口控制模块对应的物理层接口的功能,在保证了兼容性的情况下,降低了芯片的占用面积。(The embodiment of the application provides a chip and a terminal, and relates to the technical field of chips. The chip includes: the system comprises a first interface control module, a second interface control module, a multiplexing module and a shared physical layer interface; the first interface control module and the second interface control module are respectively coupled with the multiplexing module, and the first interface control module and the second interface control module respectively correspond to different types of physical layer interfaces; the multiplexing module is communicatively coupled with the shared physical layer interface; the shared physical layer interface is used for receiving first data from the external chip and/or sending second data to the external chip. According to the embodiment of the application, only one physical layer interface needs to be arranged, functions of the physical layer interface corresponding to the first interface control module and the physical layer interface corresponding to the second interface control module can be achieved, and the occupied area of a chip is reduced under the condition that compatibility is guaranteed.)

1. A chip, wherein the chip comprises: the system comprises a first interface control module, a second interface control module, a multiplexing module and a shared physical layer interface;

the first interface control module and the second interface control module are respectively coupled with the multiplexing module, and the first interface control module and the second interface control module respectively correspond to different types of physical layer interfaces;

the multiplexing module is communicatively coupled with the common physical layer interface;

the common physical layer interface is used for receiving first data from an external chip and/or sending second data to the external chip.

2. The chip of claim 1, wherein the common physical layer interface is integrated with the multiplexing module.

3. The chip of claim 2, wherein the common physical layer interface is configured to be in an operating mode of the first interface control module or an operating mode of the second interface control module.

4. The chip of claim 1, wherein the common physical layer interface and the multiplexing module are separately provided.

5. The chip of claim 4,

the common physical layer interface is configured to be in an operating mode of the first interface control module, and the multiplexing module is also configured to be in an operating mode of the first interface control module;

alternatively, the first and second electrodes may be,

the common physical layer interface is configured to be in an operating mode of the second interface control module, and the multiplexing module is also configured to be in an operating mode of the second interface control module.

6. The chip according to any of claims 1 to 5,

responding to the chip being in the working mode of the first interface control module, wherein the shared physical layer interface is used for sending the first data to the multiplexing module, and the multiplexing module is used for sending the first data to the first interface control module;

responding to the chip being in the working mode of the first interface control module, wherein the first interface control module is configured to send the second data to the multiplexing module, the multiplexing module sends the second data to the common physical layer interface, and the common physical layer interface is configured to send the second data to the external chip;

responding to the chip being in the working mode of the second interface control module, wherein the shared physical layer interface is used for sending the first data to the multiplexing module, and the multiplexing module is used for sending the first data to the second interface control module;

and in response to the chip being in the operating mode of the second interface control module, the second interface control module is configured to send the second data to the multiplexing module, the multiplexing module is configured to send the second data to the common physical layer interface, and the common physical layer interface is configured to send the second data to the external chip.

7. The chip according to any of claims 1 to 5, wherein the different types of physical layer interfaces operate in compliance with the same transport protocol.

8. The chip of any one of claims 1 to 5, wherein the first interface control module comprises a Universal Serial Bus (USB) control module, the second interface control module comprises a bus and interface standard (PCIe) control module, and the different types of physical layer interfaces comprise a USB physical layer interface and a PCIe physical layer interface.

9. The chip of any of claims 1 to 5, wherein the chip comprises a co-processing chip.

10. A terminal, characterized in that the terminal comprises a first chip;

the first chip includes: the system comprises a first interface control module, a second interface control module, a multiplexing module and a shared physical layer interface;

the first interface control module and the second interface control module are respectively coupled with the multiplexing module, and the first interface control module and the second interface control module respectively correspond to different types of physical layer interfaces;

the multiplexing module is communicatively coupled with the common physical layer interface;

the common physical layer interface is used for receiving first data from an external chip and/or sending second data to the external chip.

11. The terminal of claim 10, wherein the terminal further comprises a second chip, and wherein the external chip comprises the second chip;

the first chip is coupled with the second chip through the common physical layer interface.

Technical Field

The embodiment of the application relates to the technical field of chips, in particular to a chip and a terminal.

Background

The co-processing chip is a chip for assisting the main chip to perform some specific functions.

In the related art, data interaction between the host chip and the co-processing chip requires a specific high-speed interface to be implemented, for example, a USB (Universal Serial Bus) 3.0 interface and a PCIe (peripheral component Interconnect Express) interface. In consideration of compatibility, the co-processing chip needs to have both a USB3.0 interface and a PCIe interface.

However, the above related art co-processing chip occupies a large area.

Disclosure of Invention

The embodiment of the application provides a chip and a terminal. The technical scheme is as follows:

in one aspect, an embodiment of the present application provides a chip, where the chip includes: the system comprises a first interface control module, a second interface control module, a multiplexing module and a shared physical layer interface;

the first interface control module and the second interface control module are respectively coupled with the multiplexing module, and the first interface control module and the second interface control module respectively correspond to different types of physical layer interfaces;

the multiplexing module is communicatively coupled with the common physical layer interface;

the common physical layer interface is used for receiving first data from an external chip and/or sending second data to the external chip.

In another aspect, an embodiment of the present application provides a terminal, where the terminal includes a first chip;

the first chip includes: the system comprises a first interface control module, a second interface control module, a multiplexing module and a shared physical layer interface;

the first interface control module and the second interface control module are respectively coupled with the multiplexing module, and the first interface control module and the second interface control module respectively correspond to different types of physical layer interfaces;

the multiplexing module is communicatively coupled with the common physical layer interface;

the common physical layer interface is used for receiving first data from an external chip and/or sending second data to the external chip.

The technical scheme provided by the embodiment of the application can bring the following beneficial effects:

the multiplexing module can forward the data of the first interface control module or the data of the second interface control module to the shared physical layer interface or forward the data of the shared physical layer interface to the first interface control module or the second interface control module by arranging the multiplexing module and the shared physical layer interface in the chip, and the functions of the physical layer interface corresponding to the first interface control module and the physical layer interface corresponding to the second interface control module can be realized only by arranging one physical layer interface in the embodiment of the application.

Drawings

FIG. 1 is a schematic diagram of a chip provided by one embodiment of the present application;

FIG. 2 is a schematic diagram of a chip provided in another embodiment of the present application;

fig. 3 is a schematic diagram of a terminal provided by an embodiment of the present application;

fig. 4 is a schematic diagram of a terminal provided in another embodiment of the present application;

fig. 5 to 8 show schematic diagrams of a first chip provided in an embodiment of the present application.

Detailed Description

To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

Referring to fig. 1, a schematic diagram of a chip according to an embodiment of the present application is shown. The chip 100 includes: a first interface control module 110, a second interface control module 120, a multiplexing module 130, and a common physical layer interface 140.

The first interface control module 110 and the second interface control module 120 are respectively coupled with the multiplexing module 130.

The multiplexing module 130 is communicatively coupled to a common physical layer interface 140.

In an embodiment of the application, the common physical layer interface is used for receiving first data from an external chip and/or for sending second data to the external chip.

The first interface control module 110 mainly implements the protocol and control of the physical layer interface of its corresponding type, and the second interface control module 120 mainly implements the protocol and control of the physical layer interface of its corresponding type. In the embodiment of the present application, the first interface control module 110 and the second interface control module 120 correspond to different types of physical layer interfaces, respectively.

The multiplexing module (Multiplexer)130 may also be referred to as a data selection module. The multiplexing module 130 can make the multiplexed data information share one channel, and this sharing can be achieved when the data streams on the multiplexing lines are continuous.

In a possible implementation, the multiplexing module 130 is used to separate the received data according to the channels and send them to the corresponding output lines. In the embodiment of the present application, the multiplexing module 130 receives data from the common physical layer interface 140 and forwards the data to the first interface control module 110 or forwards the data to the second interface control module 120.

In a possible implementation, the multiplexing module 130 can select and forward a signal from a plurality of analog or digital input signals, and output different selected signals to the same output line. In this embodiment, the multiplexing module 130 may output the data sent by the first interface control module 110 and the second interface control module 120 to the same output line, and send the data sent by the first interface control module 110 to the shared physical layer interface 140 through the output line, or send the data sent by the second interface control module 120 to the shared physical layer interface 140 through the output line.

In the embodiment of the present application, the common physical layer interface 140 may implement the functions of the different types of physical layer interfaces described above. For example, the first interface control module 110 corresponds to a first type of physical layer interface, and the second interface control module 120 corresponds to a second type of physical layer interface, so that the shared physical layer interface 140 can implement the functions of the first type of physical layer interface and the second type of physical layer interface.

In a possible implementation, the multiplexing module 130 in the embodiment of the present application is a multiplexer, which is an alternative device. At this time, the multiplexer includes 3 lines: line 1, line 2 and line 3, the multiplexer performs data transmission with the first interface controller 110 through line 1, the multiplexer performs data transmission with the second interface controller 120 through line 2, and the multiplexer performs data transmission with the common physical layer interface 140 through line 3. The multiplexer transmits data transmitted by the first interface controller 110 through the line 1 or transmits data transmitted by the second interface controller 120 through the line 2 to the common physical layer interface 140 through the line 3; in addition, the common physical layer interface 140 transmits the data via line 3 to the multiplexer, which forwards the data to the first interface controller 110 via line 1 or to the second interface controller 120 via line 2 depending on the operating mode.

In a possible implementation, in response to the chip 100 being in the operating mode of the first interface control module 110, the common physical layer interface 140 is configured to send the first data to the multiplexing module 130, and the multiplexing module 130 is configured to send the first data to the first interface control module 110.

In a possible implementation, in response to the chip 100 being in the operating mode of the first interface control module 110, the first interface control module 110 is configured to send the second data to the multiplexing module 130, the multiplexing module 130 sends the second data to the common phy interface 140, and the common phy interface 140 is configured to send the second data to an external chip.

In a possible implementation, in response to the chip 100 being in the operating mode of the second interface control module 120, the common physical layer interface 140 is configured to send the first data to the multiplexing module 130, and the multiplexing module 130 is configured to send the first data to the second interface control module 120.

In a possible implementation, in response to the chip 100 being in the operating mode of the second interface control module 120, the second interface control module 120 is configured to send the second data to the multiplexing module 130, the multiplexing module 130 is configured to send the second data to the common phy interface 140, and the common phy interface 140 is configured to send the second data to an external chip.

In a possible implementation, the different types of physical layer interfaces described above operate following the same transport protocol. For example, the first interface control module 110 is a control module corresponding to a first type of physical layer interface, and the second interface control module 120 is a control module corresponding to a second type of physical layer interface, where the first type of physical layer interface and the second type of physical layer interface both conform to the same transmission protocol. When the physical layer interfaces of different types work according to the same transmission protocol, the complexity of the chip can be reduced, and the occupied area of the chip can be reduced.

In a possible implementation manner, the first interface control module includes a USB control module, the second interface control module includes a PCIe control module, and the different types of physical layer interfaces include a USB physical layer interface and a PCIe physical layer interface. The USB control module mainly realizes the protocol and control of the USB physical layer interface, and the PCIe control module mainly realizes the protocol and control of the PCIe physical layer interface. USB is an external bus standard and is also a specification for input/output interfaces. PCIe is a high-speed serial computer expansion bus standard, and its original name is "3 GIO (Input/Output) bus standard)", and belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission, and connected devices allocate an exclusive channel bandwidth, do not share a bus bandwidth, and mainly support functions such as active power management, error reporting, end-to-end reliability transmission, hot plug, and QOS (Quality of Service). Its main advantage is high data transmission rate.

In a possible implementation manner, the USB control module and the USB physical layer interface are a USB3.0 control module and a USB3.0 physical layer interface, and the USB3.0 physical layer interface and the PCIe physical layer interface have the characteristics of high bandwidth, full duplex, and the like. The USB3.0 physical layer Interface and the PCIe physical layer Interface both operate in compliance with the same transmission protocol PIPE (PHY Interface for the PCI Express). The USB3.0 physical layer interface and the PCIe physical layer interface have differences in some configurations and signals, and may be implemented as a common physical layer interface 140, where the common physical layer interface 140 includes all functions of USB3.0 and PCIe, and may implement operations in different modes according to configurations.

In a possible implementation, the chip comprises a co-processing chip. The co-processing chip may also be referred to as a co-processing module. The co-processing chip is a chip developed and applied to assist the main chip to complete the processing work which cannot be executed or has low execution efficiency or low effect, and can be used for relieving the specific processing task of the main chip. There are many tasks that the master chip cannot perform, such as signal transmission between devices, management of access devices, etc.; the low execution efficiency and low effect include graphics processing, audio processing, and AI (artificial Intelligence) processing. The co-processing chip comprises a math co-processing chip, a graph co-processing chip, an AI co-processing chip and the like. The math co-processing chip can control digital processing. The graphics co-processing chip can process video drawing, and is a processing chip specially used for accelerating the processing and displaying speed of high-resolution video images. The graphic acceleration board containing the graphic co-processing chip can accelerate the display speed of the graphic user interface, and the graphic acceleration board can greatly improve the capability of the system for displaying the application program by transferring the graphic processing task from the main chip to the graphic co-processing chip. The AI co-processing chip may be dedicated to a module that handles a large number of computational tasks in artificial intelligence applications.

In the related art, if a first interface control module and a second interface control module are arranged in a chip, a physical layer interface corresponding to the first interface control module and a physical layer interface corresponding to the second interface control module need to be correspondingly arranged, and at this time, the chip occupies a large area and has high cost; the chip in the embodiment of the application reduces one physical layer interface under the condition of ensuring compatibility, and realizes the functions of the physical layer interface corresponding to the first interface control module and the physical layer interface corresponding to the second interface control module through sharing the physical layer interface, thereby reducing the occupied area of the chip and the cost of the chip.

The embodiment of the application can be applied to data transmission service between chips.

To sum up, in the technical solution provided in this application embodiment, by setting the multiplexing module and the shared physical layer interface in the chip, the multiplexing module can forward the data of the first interface control module or the data of the second interface control module to the shared physical layer interface, or forward the data of the shared physical layer interface to the first interface control module or the second interface control module.

In an exemplary embodiment, as shown in FIG. 2, the common physical layer interface 140 is integrated with the multiplexing module 130.

In a possible implementation, the common physical layer interface 140 is configured to be in an operating mode of the first interface control module 110 or an operating mode of the second interface control module 120. Since the common phy interface 140 is integrated with the multiplexing module 130, for example, the multiplexing module 130 is integrated in the common phy interface 140, configuring the common phy 140 is equivalent to configuring the common phy interface 140 and the multiplexing module 130 at the same time.

In one example, when the common phy interface 140 is configured to be in an operating mode of the first interface control module 110, indicating that both the common phy interface 140 and the multiplexing module 140 are in an operating mode of the first interface control module 110, the common phy interface 140 may implement the functionality of the phy interface corresponding to the first interface control module 110. At this time, the chip 100 may be coupled to an external chip provided with a physical layer interface corresponding to the first interface control module 110 through the common physical layer interface 140. The common physical layer interface 140 receives the first data sent by the external chip, and sends the first data to the multiplexing module 130, the multiplexing module 130 forwards the first data to the first interface control module 110, and then the first interface control module 110 may process the first data, for example, store the first data in a specified location, or send the first data to a corresponding video playing module, or send the first data to a corresponding audio playing module, or perform image processing on the first data, and the like, which is not limited in this embodiment of the application. Accordingly, the chip 100 may also forward the second data of the first interface control module 110 to the common phy interface 140 through the multiplexing module 130, and then the common phy interface transmits the second data to the external chip. After the shared phy interface 140 is configured, the first interface control module 110, the second interface control module 120, the multiplexing module 130, and the shared phy interface 140 in the chip 100 may start to operate normally after being initialized.

In another example, when the common phy interface 140 is configured to be in the operating mode of the second interface control module 120, indicating that both the common phy interface 140 and the multiplexing module 130 are in the operating mode of the second interface control module 120, the common phy interface 140 may implement the functionality of the phy interface corresponding to the second interface control module 120. At this time, the chip 100 may be coupled to an external chip provided with a physical layer interface corresponding to the second interface control module 120 through the common physical layer interface 140. The common physical layer interface 140 receives the first data sent by the external chip, and sends the first data to the multiplexing module 130, the multiplexing module 130 forwards the first data to the second interface control module 120, and then the second interface control module 120 may process the first data, for example, store the first data in a specified location, or send the first data to a corresponding video playing module, or send the first data to a corresponding audio playing module, or perform image processing on the first data, and the like, which is not limited in this embodiment of the application. Accordingly, the chip 100 may also forward the second data of the second interface control module 120 to the common phy interface 140 through the multiplexing module 130, and then the common phy interface transmits the second data to the external chip. After the shared phy interface 140 is configured, the first interface control module 110, the second interface control module 120, the multiplexing module 130, and the shared phy interface in the chip 100 may start to operate normally after being initialized.

In summary, in the technical solution provided in the embodiment of the present application, the common physical layer interface and the multiplexing module are integrated into a whole, so that integration between chips is simplified, and since only the common physical layer interface needs to be configured, mode configuration is simplified.

In an exemplary embodiment, as shown in fig. 1, the common phy interface 140 and the multiplexing module 130 are separately provided.

In one example, the common physical layer interface 140 is configured to be in an operating mode of the first interface control module 110, and the multiplexing module 130 is also configured to be in an operating mode of the first interface control module 110. When the common phy layer interface 140 and the multiplexing module 110 are configured to be in the operating mode of the first interface control module 110, the common phy layer interface 140 may implement the function of the phy layer interface corresponding to the first interface control module 110. At this time, the chip 100 may be coupled to an external chip provided with a physical layer interface corresponding to the first interface control module 110 through the common physical layer interface 140. The common physical layer interface 140 receives the first data sent by the external chip, and sends the first data to the multiplexing module 130, the multiplexing module 130 forwards the first data to the first interface control module 110, and then the first interface control module 110 may process the first data, for example, store the first data in a specified location, or send the first data to a corresponding video playing module, or send the first data to a corresponding audio playing module, or perform image processing on the first data, and the like, which is not limited in this embodiment of the application. Accordingly, the chip 100 may also forward the second data of the first interface control module 110 to the common phy interface 140 through the multiplexing module 130, and then the common phy interface transmits the second data to the external chip. After the common phy interface 140 and the multiplexing module 130 are configured, the first interface control module 110, the second interface control module 120, the multiplexing module 130, and the common phy interface 140 in the chip 100 may start to operate normally after being initialized.

In another example, the common physical layer interface 140 is configured to be in an operating mode of the second interface control module 120, and the multiplexing module 130 is also configured to be in an operating mode of the second interface control module 120. When the common phy layer interface 140 and the multiplexing module 130 are configured to be in the operating mode of the second interface control module 120, the common phy layer interface 140 may implement the function of the phy layer interface corresponding to the second interface control module 120. At this time, the chip 100 may be coupled to an external chip provided with a physical layer interface corresponding to the second interface control module 120 through the common physical layer interface 140. The common physical layer interface 140 receives the first data sent by the external chip, and sends the first data to the multiplexing module 130, the multiplexing module 130 forwards the first data to the second interface control module 120, and then the second interface control module 120 may process the first data, for example, store the first data in a specified location, or send the first data to a corresponding video playing module, or send the first data to a corresponding audio playing module, or perform image processing on the first data, and the like, which is not limited in this embodiment of the application. Accordingly, the chip 100 may also forward the second data of the second interface control module 120 to the common phy interface 140 through the multiplexing module 130, and then the common phy interface transmits the second data to the external chip. After the shared phy interface 140 is configured, the first interface control module 110, the second interface control module 120, the multiplexing module 130, and the shared phy interface in the chip 100 may start to operate normally after being initialized.

Referring to fig. 3, a schematic diagram of a terminal according to an embodiment of the present application is shown. The terminal 300 includes: a first chip 400.

The first chip 400 includes: a first interface control module 410, a second interface control module 420, a multiplexing module 430, and a common physical layer interface 440.

The first interface control module 410 and the second interface control module 420 are respectively coupled to the multiplexing module 430, and the first interface control module 410 and the second interface control module 420 respectively correspond to different types of physical layer interfaces.

The multiplexing module 430 is communicatively coupled with a common physical layer interface 440.

The common physical layer interface 440 is used for receiving first data from the external chip and/or for transmitting second data to the external chip.

In a possible implementation, the common physical layer interface 440 is integrated with the multiplexing module 430. At this time, the common physical layer interface 440 is configured to be in an operation mode of the first interface control module 410 or an operation mode of the second interface control module 420.

In a possible implementation, the common physical layer interface 440 and the multiplexing module 430 are separately provided. In one example, the common physical layer interface 440 is configured to be in an operational mode of the first interface control module 410, and the multiplexing module 430 is also configured to be in an operational mode of the first interface control module 410; in another example, the common physical layer interface 440 is configured to be in an operational mode of the second interface control module 420, and the multiplexing module 430 is also configured to be in an operational mode of the second interface control module 420.

In a possible implementation, the different types of physical layer interfaces described above operate following the same transport protocol.

In a possible implementation, the first interface control module 410 includes a USB control module, and the second interface control module 420 includes a PCIe control module, and the different types of physical layer interfaces include a USB physical layer interface and a PCIe physical layer interface.

In a possible implementation, the first chip 400 includes a co-processing chip.

It should be noted that the first chip 400 may be the chip 100 in any one of the embodiments of fig. 1 to 2, or may be a chip of the same type, and for the description of the first chip 400, reference may be made to the description of the embodiment described in fig. 1 to 2, and details are not repeated here.

The terminal 300 in this embodiment of the present application may be implemented as a terminal having a physical layer interface corresponding to the first interface control module, and may also be implemented as a terminal having a physical layer interface corresponding to the second interface control module, which is not limited in this embodiment of the present application. For example, the terminal in the embodiment of the present application may be an electronic device such as a mobile phone, a routing module, a tablet Computer, and a PC (Personal Computer).

To sum up, in the technical solution provided in this application embodiment, by setting the multiplexing module and the shared physical layer interface in the chip, the multiplexing module can forward the data of the first interface control module or the data of the second interface control module to the shared physical layer interface, or forward the data of the shared physical layer interface to the first interface control module or the second interface control module.

In addition, the integration between chips is simplified by integrating the shared physical layer interface and the multiplexing module, and the mode configuration is simplified because only the shared physical layer interface needs to be configured.

In a possible implementation, as shown in fig. 4, the terminal 300 further includes a second chip 500, the external chip includes the second chip 500, and the first chip 400 is coupled to the second chip 500 through a common physical layer interface 440.

In a possible implementation manner, the second chip 500 is provided with a first interface control module 410 and a physical layer interface corresponding to the first interface control module 410, and the second chip 500 performs data transmission with the first chip 400 through the physical layer interface corresponding to the first interface control module 410. For example, the second chip 500 sends the first data to the common physical layer interface 440 of the first chip 400 through the physical layer interface corresponding to the first interface control module 410; the common physical layer interface 440 transmits the first data to the multiplexing module 430; the multiplexing module 430 sends the first data to the first interface control module 410; then, the first interface control module 410 processes the first data. Accordingly, the first chip 400 transmits the second data of the first interface control module 410 to the common physical layer interface 440 through the multiplexing module 430; then, the common phy interface 440 transmits the second data to a phy interface corresponding to the first interface control module 410 of the second chip 500.

In a possible implementation manner, the second chip 500 is provided with a second interface control module 420 and a physical layer interface corresponding to the second interface control module 420, and the second chip 500 performs data transmission with the first chip 400 through the physical layer interface corresponding to the second interface control module 420. For example, the second chip 500 sends the first data to the common physical layer interface 440 of the first chip 400 through the physical layer interface corresponding to the second interface control module 420; the common physical layer interface 440 transmits the first data to the multiplexing module 430; the multiplexing module 430 sends the first data to the second interface control module 420; then, the second interface control module 420 processes the first data. Accordingly, the first chip 400 transmits the second data of the second interface control module 420 to the common physical layer interface 440 through the multiplexing module 430; then, the common physical layer interface 440 sends the second data to the physical layer interface corresponding to the second interface control module 420 of the second chip 500.

In a possible implementation, the first chip 400 includes a co-processing chip, and the second chip 500 includes a main chip.

In a possible implementation manner, the second chip 500 is a chip with a similar result to the first chip 400, for example, the second chip 500 also includes a first interface control module 410, a second interface control module 420, a multiplexing module 430, and a common physical layer interface 440.

The first interface control module 410 is a USB3.0 control module, the second interface control module 420 is a PCIe control module, and the second chip 500 is provided with a USB3.0 control module and a USB3.0 physical layer interface for example. The second chip 500 sends the first data to the common physical layer interface 440 of the first chip 400 through the USB3.0 physical layer interface; the common physical layer interface 440 transmits the first data to the multiplexing module 430; the multiplexing module 430 sends the first data to the USB3.0 control module. Accordingly, the first chip 400 transmits the second data of the USB3.0 control module to the common physical layer interface 440 through the multiplexing module 430; then, the common phy interface 440 transmits the second data to the USB3.0 phy interface of the second chip 500. At this time, the first chip 400 includes two schematic diagrams as shown in fig. 5 and fig. 6, in fig. 5, the common physical layer interface 440 is integrated with the multiplexing module 430; in fig. 6, the common physical layer interface 440 and the multiplexing module 430 are separately provided.

The first interface control module 410 is a USB3.0 control module, the second interface control module 420 is a PCIe control module, and the second chip 500 is provided with a PCIe control module and a PCIe physical layer interface for example. The second chip 500 sends the first data to the common physical layer interface 440 of the first chip 400 through the PCIe physical layer interface; the common physical layer interface 440 transmits the first data to the multiplexing module 430; the multiplexing module 430 sends the first data to the PCIe control module. Accordingly, the first chip 400 sends the second data of the PCIe control module to the common physical layer interface 440 through the multiplexing module 430; then, the common physical layer interface 440 sends the second data to the PCIe physical layer interface of the second chip 500. At this time, the first chip 400 includes two schematic diagrams as shown in fig. 7 and fig. 8, in fig. 7, the common physical layer interface 440 is integrated with the multiplexing module 430; in fig. 8, the common physical layer interface 440 and the multiplexing module 430 are separately provided.

It should be understood that reference herein to "and/or" describing an associative relationship of associated objects means that there may be three relationships, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.

The above description is only exemplary of the present application and should not be taken as limiting the present application, and any modifications, equivalents, improvements and the like that are made within the spirit and principle of the present application should be included in the protection scope of the present application.