阅读说明：本技术 形成具有倾斜接触件的半导体元件的元件结构 (Element structure for forming semiconductor element with inclined contact ) 是由 索尼·瓦吉斯 安东尼·雷诺 摩根·艾文斯 约翰·哈塔拉 约瑟·欧尔森 于 2018-11-27 设计创作，主要内容包括：一种存储器元件可包括至少部分地设置在第一水平中的有源元件区。存储器元件可包括至少部分地设置在高于第一水平的第二水平中的存储电容器,其中第一水平及第二水平平行于衬底平面。存储器元件还可包括接触通孔,接触通孔在存储电容器与有源元件区之间延伸,且相对于衬底平面的垂线界定非零度的倾斜角。(A memory element may include an active element region disposed at least partially in a first level. The memory element may include a storage capacitor disposed at least partially in a second level higher than the first level, wherein the first level and the second level are parallel to the substrate plane. The memory element can also include a contact via extending between the storage capacitor and the active element region and defining a non-zero degree tilt angle with respect to a perpendicular to the substrate plane.)

1. A memory element, comprising:

an active element region at least partially disposed in a first level;

a storage capacitor disposed at least partially in a second level higher than the first level, wherein the first level and the second level are parallel to a substrate plane; and

a contact via extending between the storage capacitor and the active element region and defining a non-zero degree tilt angle with respect to a perpendicular to the substrate plane.

2. The memory element according to claim 1, wherein the storage capacitor forms a non-complete overlap with the active element region in the substrate plane from a plan view perspective.

3. The memory element according to claim 1, wherein the storage capacitor does not form an overlap with the active element region in the substrate plane from a plan view perspective.

4. The memory element defined in claim 1, wherein an entire bottom portion of the contact via overlaps the active element region.

5. The memory element defined in claim 1, wherein an entire top portion of the contact via overlaps the storage capacitor.

6. The memory element of claim 1, wherein the non-zero degree of tilt angle is less than 15 degrees.

7. The memory element of claim 1, wherein the active element region and the storage capacitor form part of a Dynamic Random Access Memory (DRAM) cell, wherein the DRAM cell forms part of a DRAM element, wherein the DRAM element comprises 6F²And (5) structure.

8. The memory element of claim 1, wherein the contact via is at least partially disposed in a third level extending between the first level and the second level.

9. The memory element of claim 1, wherein the active element region and the storage capacitor form a portion of a Dynamic Random Access Memory (DRAM) cell, wherein the contact via extends through a digit line level of the dynamic random access memory cell comprising a digit line.

10. A method of fabricating a semiconductor device, comprising:

forming an active element region in a first level of the semiconductor element;

forming a contact via contacting the active element region, the contact via forming a non-zero degree tilt angle with respect to a perpendicular to a substrate plane; and

forming a storage capacitor at least partially in a second level of the semiconductor element higher than the first level, wherein the storage capacitor contacts the contact via.

11. The method of claim 10, wherein the storage capacitor does not form an overlap with the active element region in the substrate plane from a plan view perspective.

12. The method of claim 10, wherein the active element region and the storage capacitor form a portion of a Dynamic Random Access Memory (DRAM) cell, wherein the contact via extends through a digit line level of the dynamic random access memory cell including a digit line without contacting the digit line.

13. The method of claim 10, wherein forming the contact via comprises:

disposing a substrate comprising the active element region in a process chamber adjacent to a plasma chamber;

extracting an ion beam from the plasma chamber into the process chamber through an extraction aperture, wherein the ion beam forms a trace defining a non-zero angle of incidence with respect to the substrate plane; and

performing at least one scan, wherein the substrate is scanned relative to the extraction aperture while the substrate is exposed to the ion beam.

14. The method of claim 13, further comprising:

forming an insulator on the active element region before forming the contact via; and

forming a mask on the insulator, the mask defining a plurality of openings defining a first opening, wherein the ion beam forms the contact via by etching the insulator through the first opening using a reactive ion beam etching process.

15. A component structure comprising:

a first element disposed in a first element level;

a second element disposed in a second element level higher than the first element level; and

a contact via extending between the first element and the second element and defining a non-zero degree tilt angle with respect to a perpendicular to a substrate plane.

Technical Field

Embodiments of the present invention relate to semiconductor device structures, and more particularly, to the structure and processing of memory devices including dynamic random access devices.

Background

As semiconductor devices, including logic and memory devices, such as Dynamic Random Access Memory (DRAM) devices, are scaled to smaller dimensions, the ability of device patterning to improve from the smaller dimensions is increasingly limited. For example, in present day dynamic random access memory devices, known architectures include the so-called 8F²Structure and 6F²Structure (architecture), etc. Although 6F²Architecture offering ratio 8F²Higher element density and greater speed are architected, however the ability to form memory elements with appropriate properties is compromised due at least in part to patterning issues, such as overlay. As an example, 6F due to the shrinking size of DRAM cells²The architecture makes it difficult to form electrical contact between the access transistor and the structure above the access transistor, such as a bit line or a storage node capacitor. For example, the storage node capacitor may be formed in a much higher level than the level including the access transistor. In order to form the electrical connection between the storage capacitor and the access transistor, it may be desirable to form structures such as vias that pass through multiple levels including a bit line level (bit line level) and a bit line contact level (bit line contact level). The contact vias may not be properly located due to the crowding between the bit lines, word lines, and the active area forming the access transistorsThe ground contacts the active region of the transistor. For example, to avoid overlap with the bit line, the contact vias may be placed at locations of overlap between the contact vias and the storage capacitors and overlap between the contact vias and the active regions of the access transistors may be less than ideal.

In view of these and other considerations, the present disclosure is provided.

Disclosure of Invention

In one embodiment, a memory element may include an active element region disposed at least partially in a first level. The memory element may include a storage capacitor disposed at least partially in a second level higher than the first level, wherein the first level and the second level are parallel to the substrate plane. The memory element can also include a contact via extending between the storage capacitor and the active element region and defining a non-zero degree tilt angle with respect to a perpendicular to the substrate plane.

In another embodiment, a method of fabricating a semiconductor device may include forming an active device region in a first level of the semiconductor device. The method may also include forming a contact via. The contact via contacts the active device region. The contact via forms a non-zero degree tilt angle with respect to a perpendicular to the plane of the substrate. The method may further include forming a storage capacitor at least partially in a second level of the semiconductor element higher than the first level, wherein the storage capacitor contacts the contact via.

In another embodiment, an element structure may include a first element disposed in a first element level and a second element disposed in a second element level higher than the first element level. The element structure may also include a contact via extending between the first element and the second element and defining a non-zero degree tilt angle with respect to a perpendicular to the substrate plane.

Drawings

Fig. 1A illustrates a top perspective view of a component structure according to an embodiment of the present disclosure.

FIG. 1B shows a top perspective view of the component structure shown in FIG. 1B, rotated slightly from the perspective of FIG. 1B.

FIG. 1C shows a side view of a portion of the cell structure shown in FIG. 1A.

Fig. 1D shows a top plan view of a portion of the cell structure shown in fig. 1A.

Fig. 1E illustrates a top plan view of a cell structure according to further embodiments of the present disclosure.

Fig. 2A-2D illustrate element structures at various stages of fabrication according to some embodiments of the present disclosure.

Fig. 3A illustrates a side view of an apparatus according to an embodiment of the present disclosure.

FIG. 3B shows a top plan view of a portion of the apparatus shown in FIG. 3A.

FIG. 3C illustrates an enlarged top plan view of a detail of the mask geometry shown in FIG. 3B.

Fig. 4 illustrates a top plan view of a component structure according to an embodiment of the present disclosure.

FIG. 5 illustrates an exemplary process flow according to further embodiments of the present disclosure.

Detailed Description

Embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which some embodiments are shown. The subject matter of the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the subject matter to those skilled in the art. In the drawings, like numbering represents like elements throughout.

Embodiments of the present invention provide novel techniques and substrate structures to form elements including memory elements formed in a semiconductor substrate. These techniques may be particularly useful for forming dynamic random access memory elements, although other elements may also be formed in accordance with embodiments of the present disclosure. These other elements may include NAND (NAND) elements (including three-dimensional NAND elements (3DNAND)), NOR (NOR) elements, X-point memories (X-point memories), and logic elements, as well as packaging structures, where a common feature is that the linking of different components in different levels of a given element is the use of slanted vias. In various embodiments, the slanted via may be constructed in a dielectric material, polysilicon, or silicon, such as a Through Silicon Via (TSV). The embodiments are not limited in this context. Various non-limiting embodiments are particularly applicable to implementations in which a component in a first level of an element (e.g., a dynamic random access memory storage capacitor) is linked to another component in a different level of the element (e.g., an access transistor).

According to various embodiments, a memory element may comprise an active element region located in an active level (active level) and a storage capacitor located in a capacitor level (capacitor level) above the active level. Advantageously, as described below, the angled contact vias are also provided to form angled contacts extending between the storage capacitors and the active device region, wherein the angled contact vias define a non-zero degree angle of inclination with respect to a perpendicular to a device plane (device plane) as defined by the active level and the storage capacitor level. As described below, such element structures and related element structures may improve element performance by facilitating better overlap between elements that are in contact with each other at different levels.

Referring now to fig. 1A and 1B, two top perspective views of a cell structure 100 according to an embodiment of the present disclosure are shown. The element structure 100 illustrates several components of a memory element (e.g., a dynamic random access memory element). The element structure 100 includes a set of storage capacitors arranged in a storage capacitor level, shown as level 110, shown as storage capacitor 102 (see fig. 1B for further definition of the different levels of the element structure 100). As used herein, "level" may refer to a portion of an element where different levels are built up one by one as the element is fabricated, for example, by using different masking operations (masking operations) for the different levels. As used herein, "substrate plane" may refer to the X-Y plane of a Cartesian coordinate system (Cartesian coordinate system) as shown. During fabrication of the components, the different levels are typically built on each other sequentially along the Z-axis. Thus, lower levels may be generally constructed lower in the Z-axis, while higher levels may be constructed higher along the Z-axis, as shown in fig. 1B. Notably, different structures built from different mask levels may be located in the same physical level along the Z-axis or overlap in the same physical level along the Z-axis, as is known in the art.

The element structure 100 also includes an active element region 104, where the active element region 104 is disposed in an active element level shown as level 150. The active device region 104 may represent a top surface of a semiconductor structure (e.g., single crystal silicon) to serve as an active transistor element (e.g., a source/drain (S/D) structure of a transistor). A gate structure 114 is also shown, and the gate structure 114 can be used to turn a transistor on or off. Element structure 100 also includes a digit line 112 disposed in a digit line level, shown as level 130, wherein digit line 112 is electrically connected to gate structure 114 using digit line contact 116 disposed in a contact level 140. The element structure 100 further includes a set of vias, shown as contact vias 106, where the contact vias 106 extend in a level 120 of the contact vias between the storage capacitors 102 and the active element region 104. Notably, the contact vias 106 may extend through multiple levels. In the example shown in fig. 1A and 1B, two storage capacitors are shown, wherein the storage capacitor 102 is connected to a source region or a drain region of the active element region 104. It is noted that the two storage capacitors shown may contact two different transistors formed using the active element region 104.

The cell structure 100 further includes a contact via 106, the contact via 106 extending between the storage capacitor 102 and the active device region 104. The contact vias 106 may generally comprise a conductive material to form a conductive path between the active device region 104 and the storage capacitor 102. When a signal is sent along the digit line 112, the gate structure 114 can be activated by the signal through the digit line contact 116 to turn on the transistor formed by the active element region 104. When the transistor is turned on, charge may flow to the storage capacitor 102 or form from the storage capacitor 102 through the contact via 106, as is known in the art.

As shown in more detail in fig. 1C, the contact via 106 is sloped, meaning that the contact via 106 defines a non-zero degree angle of inclination, shown as θ, with respect to a perpendicular 122 to the plane of the substrate (defined in this case as the X-Z plane). This structure is in contrast to known dynamic random access memory contact vias that extend vertically between different levels, meaning at zero tilt angle relative to the vertical 122.

Fig. 1D illustrates a top plan view of a portion of the cell structure 100 shown in fig. 1A. As shown in fig. 1C and 1D, the bottom portion 106A of the contact via 106 overlaps the active element region 104. In some embodiments, the bottom portion 106A may entirely overlap the active element region 104. As also shown in fig. 1C and 1D, the top portion 106B of the contact via 106 overlaps the storage capacitor 102. In some embodiments, the top portion 106B may entirely overlap the active element region 104.

As shown in fig. 1D, the contact vias 106 allow the storage capacitors 102 to be displaced in the X-Y plane relative to the active element region 104. For example, in some embodiments as reflected in fig. 1D, the storage capacitor 102 may not overlap the active area 104. More specifically, the storage capacitor 102 does not appear to overlap the active element region 104 in the X-Y plane from a plan view perspective, although disposed in a higher level. In this manner, the contact vias 106 facilitate excellent electrical contact between the various structures disposed in different levels that are not aligned with one another at corresponding locations in the substrate plane (e.g., the X-Y plane) with respect to locations in the substrate plane (e.g., the X-Y plane). This geometry differs from the geometry of known dynamic random access memory elements in which the contact vias are vertically aligned between levels, meaning along the perpendicular to the substrate plane or element plane, imposing a constraint in which a complete overlap between the storage capacitors and the contact vias or between the contact vias and the active regions may not be possible.

Fig. 1E provides a top plan view of an implementation of the element structure 160 according to some embodiments of the present disclosure. The device structure 160 is implemented as 6F²Dynamic random access memory architecture in which active regions 104 are arranged in an array of elongated regionsDefining an angle with respect to digit lines 112 and word lines 118

In the diagram of FIG. 1E, the various structures are shown disposed in levels 110, 130, and 150. The contact vias 106 are not explicitly shown. In addition, word line 118 is disposed in a level higher than level 110. As shown, the storage capacitors 102 are arranged in a two-dimensional array. Notably, the storage capacitor 102 overlaps the digit line 112 in the X-Y plane. Meanwhile, as set forth in detail above, the contact via 106 may completely overlap the storage capacitor 102 (in the top portion 106B) and completely overlap the active element region 104. Thus, the contact vias 106 provide a large degree of freedom in placing the storage capacitor 102 in the X-Y plane relative to other structures in the horizontal plane by being arranged at a non-zero degree angle of inclination relative to the vertical. In other words, the storage capacitor 102 may be aligned directly on top of other structures in a level intermediate the level of the active element region 104 (level 150) and the storage capacitor level (level 110), forming an overlap in the X-Y plane. This geometry is achieved because the contact vias 106 used to connect the storage capacitors 102 to the active element regions 104 can be sloped to avoid contacting other structures.

Fig. 2A-2D illustrate the element structure 200 at various stages of fabrication according to some embodiments of the present disclosure. The sequence begins at the stage of fabrication of the memory device of fig. 2A, where the active device region and the transistor gates have been fabricated. The sequence shown in fig. 2A to 2D is performed by forming the inclined via hole and ends before forming the storage capacitor. In fig. 2A, an insulator 202 is disposed over the active device region 104 and the gate structure 114. The insulator 202 provides an intermediate for forming vias, as described below.

Referring to fig. 2B, the mask 204 is shown after it has been formed on the insulator 202. Mask 204 is patterned to produce an array of openings, shown as opening 206. Are given openings for forming contact vias as explained in detail below. According to various embodiments, the mask 204 may include a combination of at least one layer (e.g., known for patterning, including but not limited to nitride, carbon, oxide, or resist). In various non-limiting embodiments, the thickness of the mask 204 may be in the range of 10nm to 100 nm. The mask 104 may generally be made of a different material than the insulator 202. The mask 204 may thus be used to transfer the pattern of the opening 206 into the insulator 202.

Referring now to fig. 2C, a subsequent situation is shown in which the tilted ions 208 are directed to the mask 104. As described in detail below, the tilted ions 208 may be provided in a directional reactive ion beam etching operation that is designed to etch the insulator 202. The etch recipe including the tilted ions 208 may be designed to etch the insulator 202 selectively with respect to the mask 104. In some non-limiting embodiments, the etch selectivity may vary between approximately 5/1 and 20/1, meaning that an etch recipe including tilted ions 208 etches insulator 202 five to twenty times faster than mask 204.

Referring now to fig. 2D, therein is shown the situation after completion of the directional reactive ion beam etching operation shown in fig. 2C. At this element formation stage, angled contact vias, shown as contact via 210, have been made within insulator 202. The contact vias 210 extend at a non-zero degree oblique angle with respect to the perpendicular 122 to the X-Y plane. The contact via 210 extends to expose the active device region 104. After the operation of fig. 2D, a set of storage capacitors may be formed on top of the contact vias 210. Although not shown, the digit line can extend within the insulator 202 to make contact with the gate structure 114, as described above.

Referring now to FIG. 3A, a processing device 300 is shown in schematic form. Processing tool 300 represents a processing tool that etches a portion of a substrate, such as an insulator layer. The processing apparatus 300 may be a plasma-based processing system having a plasma chamber 302, the plasma chamber 302 being used to generate a plasma 304 therein by any convenient method known in the art. An extraction plate 306 may be provided as shown, the extraction plate 306 having extraction holes 308 that may perform selective etching to reactively etch the insulator layer with respect to the mask material. A substrate 220 is disposed in the process chamber 322, the substrate 220 including, for example, the above-described structure, i.e., the device structure 200. The substrate plane of substrate 220 is represented by the X-Y plane of the cartesian coordinate system shown, with the perpendicular to the plane of substrate 220 along the Z-axis (Z-direction).

During a tilted reactive ion beam etching operation, an ion beam 310 is extracted through an extraction aperture 308 as shown. As shown in fig. 3A, the trajectory (trajectory) of ion beam 310 forms a non-zero angle of incidence, shown as θ, with respect to perpendicular 122. The individual trajectories of ions within the ion beam 310 may be parallel to each other or may be within a narrow range of angles, such as within 10 degrees or less than 10 degrees of each other. Thus, the value of θ may represent an average of the incident angles at which the respective traces vary by a few degrees from the average. The ion beam 310 may be extracted when a voltage difference is applied using a bias power supply 320 located between the plasma chamber 302 and the substrate 220 as in known systems. The bias power source 320 may be coupled to the process chamber 322, for example, where the process chamber 322 is maintained at the same potential as the substrate 220. In various embodiments, the ion beam 310 may be extracted as a continuous beam or as a pulsed ion beam as in known systems. For example, the bias power supply 320 may be configured to supply a voltage difference between the plasma chamber 302 and the process chamber 322 as a pulsed Direct Current (DC) voltage, wherein the voltage, pulse frequency, and duty cycle of the pulsed voltage may be adjusted independently of each other.

In various embodiments, for example, ion beam 310 may be provided as a ribbon ion beam having a long axis extending along the X-direction of the cartesian coordinate system shown in fig. 3B. As also shown in fig. 3C, during the operation of fig. 3A, the mask 204 may be oriented such that the openings 206 are arranged in rows, generally aligned with the rows of active element regions 104, as viewed in the X-Y plane. As shown, the rows of openings 206 may be displaced in the X-Y plane relative to the rows of active element regions 104. The projections of the trajectories of the ions of the ion beam 310 in the X-Y plane are shown by arrows. By scanning the substrate table 314 including the substrate 220 in a scan direction 316 relative to the extraction aperture 308, and thus relative to the ion beam 310, the ion beam 310 can etch a set of tilted vias oriented at a non-zero tilt angle relative to the perpendicular 122. The ion beam 310 may be comprised of any convenient gas mixture (including inert gases, reactive gases), and may be provided along with other gaseous species in some embodiments. In a particular embodiment, the ion beam 310 and other reactive species may be provided to the substrate 220 as an etch recipe to perform a directional reactive ion etch on a target sidewall of the substrate 220. Such etch recipes may use known reactive ion etch chemistries to etch materials such as oxides or other materials, as is known in the art. The etch recipe may have selectivity to the material of the mask 204 to remove the insulator 202 without etching the mask 204 or to a lesser extent etching the mask 204.

In the example shown in fig. 3B, the substrate 220 is a circular wafer (e.g., a silicon wafer) and the extraction holes 308 are elongated holes having an elongated shape. The ion beam 310 is provided as a ribbon-shaped ion beam extending along the X direction to a beam width (beam width) sufficient to expose the entire width of the substrate 101, even at the widest portion along the X direction. Exemplary beam widths may be in the range of 10cm, 20cm, 30cm, or greater than 30cm, while exemplary beam lengths along the Y direction may be in the range of 3mm, 5mm, 10mm, or 20 mm. The embodiments are not limited in this context.

As also shown in fig. 3B, the substrate 220 may be scanned in a scan direction 316, where the scan direction 316 lies in an X-Y plane, e.g., along the Y direction. Notably, the scan direction 316 can be represented as scanning the substrate 220 in two opposite (180 degree) directions along the Y direction, or simply a left-facing scan or a right-facing scan. As shown in fig. 3B, the long axis of the ion beam 310 extends along the X-direction perpendicular to the scan direction 316. Thus, when the substrate 220 is scanned along the scan direction 316 for a sufficient length from the left side to the right side of the substrate 220, the entire substrate 220 may be exposed to the ion beam 310, as shown in fig. 3B.

As also shown in fig. 3B and 3C, the substrate 220 may be exposed to the ion beam while scanning the substrate 220 while disposed at a first rotational position (the substrate 220 is located below the location L on the extraction plate 306) as indicated by position P1 on the substrate 220. For example, the position P1 may correspond to the position of a notch or flat face on a wafer. According to various embodiments, at least one scan may be performed along the scan direction 316 to form the contact vias 106 while the substrate 220 is in a fixed rotational position. Since the ion beam 310 forms a non-zero angle of incidence with respect to the perpendicular 122, the etching of the contact via 106 may be performed in a manner that produces a via having an axis that is formed at an oblique angle generally along the non-zero angle of incidence, also shown as θ in the diagram illustrating the contact via. According to various non-limiting embodiments, the value of θ may be less than 15 degrees, and may be between 5 and 10 degrees in particular embodiments. The exact value of θ may be selected based on the amount of displacement (in the X-Y plane) of the storage capacitor 102 relative to the active device region 104 that is designed. Thus, an element structure such as that shown in fig. 2D can be produced in which a given active element in level 150 to be connected by a given storage capacitor (in level 110) is shifted to the left in the figure.

In other embodiments of the method and device structure, a set of storage capacitors may be arranged in an array in which different capacitors are tilted in different directions. Fig. 4 illustrates a top plan view of a cell structure 400 according to an embodiment of the present disclosure. The diagram of fig. 4 shows several component levels as discussed above. The element structure 400 includes a set of active regions, shown as active regions 412, for forming transistor elements. Active areas 412 are arranged in various rows, shown as active area row 410, active area row 420, active area row 430, and active area row 440. As also shown in fig. 4, the element structure 400 includes rows of various capacitors 452, including capacitor row 450 and capacitor row 460, where the capacitor rows are spaced apart between the active areas 421 with some overlap, as shown. Within capacitor row 450, capacitors 452 are alternately connected to active area 412 in active area row 410 or active area row 420, as shown. Similarly, within capacitor row 460, capacitors 452 are alternately connected to active area 412 in active area row 430 or active area row 440, as shown. This staggered connection arrangement is achieved by providing a first contact via 462 inclined in a first direction and a second contact via 464 inclined in a second direction.

To produce the structure shown in FIG. 4, the processing device 300 may operate in the following manner. As an example, when the ion beam 310 is aligned with a fixed non-zero angle of incidence with respect to the perpendicular 122, the substrate 220 may be maintained at a first rotational position (e.g., as shown in fig. 3B) during a first set of scans to form a first set of contact vias, as generally shown in fig. 2D. In the second set of scans, the ion beam 310 may be rotated through a twist angle (twist angle) of 180 degrees over the substrate 220And then arranged to have the same fixed non-zero angle of incidence with position P3 located adjacent L. In this manner, a second set of contact vias may be formed that define a non-zero angle of incidence with respect to perpendicular 122 and have the same absolute value as the first set of contact vias, while forming a mirror image of the first set of contact vias with respect to the X-Z plane. This structure enables further design flexibility in terms of relative displacement with respect to the underlying active region in the element (e.g., dynamic random access memory element).

Fig. 5 illustrates an exemplary process flow 500 according to an embodiment of the present disclosure. In block 502, an active device region is formed in a first level of semiconductor devices (e.g., in a dynamic random access memory structure). In block 504, a contact via is formed, wherein the contact via contacts the active device region and extends at a non-zero angle of incidence with respect to a perpendicular to the plane of the substrate. In block 506, a digit line is formed over the active device region, wherein the digit line is electrically coupled to the active device region, wherein the contact via does not contact the digit line. Notably, the contact vias may extend through multiple levels. At block 508, a storage capacitor is formed at least partially in a second level of the semiconductor device above the first level, wherein the storage capacitor is in electrical contact with the contact via.

Embodiments of the present invention provide various advantages over known device structures including memory devices, such as dynamic random access memory devices. For one advantage, the use of angled vias increases the contact area between different element structures so that element structures disposed in different levels do not align with each other, such as memory structures where the storage capacitor is not directly aligned over the active element region. Accordingly, using the inclined contact via, the entire top portion of the contact via may overlap the storage capacitor, while the entire bottom portion of the contact via overlaps the active element region. Another advantage is placement flexibility of a first element structure in a first level relative to placement of a second element structure in a second level. For example, the storage capacitor in the capacitor level may be shifted in the X-Y plane relative to the active element region in the active level because the contact vias connecting the storage capacitor with the active element region may compensate for the shift by the corners of the contact vias.

The scope of the present disclosure is not limited to the specific embodiments described herein. Indeed, other various embodiments of and modifications to the present disclosure, in addition to those described herein, will be apparent to those of ordinary skill in the art from the foregoing description and accompanying drawings. Accordingly, such other embodiments and modifications are intended to fall within the scope of the present disclosure. Moreover, the present disclosure has been set forth herein in the context of a particular implementation in a particular environment for a particular purpose, however, one of ordinary skill in the art will recognize that its usefulness is not limited thereto and that the present disclosure may be beneficially implemented in any number of environments for any number of purposes. Accordingly, the claims set forth below should be construed in view of the full breadth and spirit of the present disclosure as described herein.