阅读说明：本技术 接口的最低输入/输出翻转率 (Lowest input/output slew rate of interface ) 是由 索伦·劳森 罗伯特·克里奇洛 戴泽福 于 2020-02-07 设计创作，主要内容包括：一种用于实现最低翻转率保证的装置可包括第一、第二和第三电路。第一电路可基于多个内部输入/输出(IO)信号的值的序列来计算内部总线反转信号的值的序列。第二电路可通过在内部总线反转信号的值的序列和基本上随机的值的序列之间进行选择来建立外部总线反转信号的值的序列。第三电路可在各自对应的外部总线反转信号的值的序列具有第一值时将多个外部IO信号的值设置到多个内部信号的反转值,并且在各自对应的外部总线反转信号的值的序列具有第二值时将多个外部IO信号的值设置到多个内部信号的值。(An apparatus for achieving minimum slew rate assurance may include first, second, and third circuits. The first circuit may calculate a sequence of values of the internal bus inversion signal based on a sequence of values of a plurality of internal input/output (IO) signals. The second circuit may establish the sequence of values of the external bus inversion signal by selecting between the sequence of values of the internal bus inversion signal and the substantially random sequence of values. The third circuit may set the values of the plurality of external IO signals to the inverted values of the plurality of internal signals when the sequence of the values of the respectively corresponding external bus inversion signals has the first value, and set the values of the plurality of external IO signals to the values of the plurality of internal signals when the sequence of the values of the respectively corresponding external bus inversion signals has the second value.)

1. An apparatus, comprising:

a first circuit for calculating a value of an internal bus inversion signal based on values of a plurality of internal signals;

a second circuit for determining a value of a bus inversion signal of an external interface based on a value of the internal bus inversion signal and a random inversion component; and

a third circuit for setting values of a plurality of input/output (IO) signals of the external interface based on values of the plurality of internal signals and values of the bus inversion signal of the external interface.

2. The apparatus of claim 1, wherein the first and second electrodes are disposed in a common plane,

wherein the third circuit sets values of a plurality of IO signals of the external interface to inverted values of the plurality of internal signals when the bus inversion signal of the external interface has a first value; and is

Wherein the third circuit sets values of a plurality of IO signals of the external interface to values of the plurality of internal signals when the bus inversion signal of the external interface has a second value.

3. The apparatus of claim 1, wherein the first and second electrodes are disposed in a common plane,

wherein the random upset component is based on at least an output of a Pseudo Random Number Generator (PRNG) circuit.

4. The apparatus of claim 1, wherein the first and second electrodes are disposed in a common plane,

wherein the second circuit further determines a value of a bus inversion signal of the external interface based on an output of the counter circuit.

5. The apparatus of claim 1, wherein the first and second electrodes are disposed in a common plane,

wherein the random inversion component is generated to satisfy a predetermined minimum inversion rate for at least one of the plurality of IO signals of the external interface.

6. The apparatus of claim 1, wherein the first and second electrodes are disposed in a common plane,

wherein the internal bus inversion signal is determined to reduce a Simultaneous Switching Output (SSO) attribute of the plurality of IO signals of the external interface.

7. The apparatus of claim 1, wherein the first and second electrodes are disposed in a common plane,

wherein the internal bus inversion signal is determined to reduce Simultaneous Switching Noise (SSN) properties of the plurality of IO signals of the external interface.

8. The apparatus of claim 1, wherein the first and second electrodes are disposed in a common plane,

wherein the external interface is a chip-to-chip communication interface.

9. The apparatus of claim 1, wherein the first and second electrodes are disposed in a common plane,

wherein the plurality of IO signals of the external interface are clocked at a frequency of at least 1 GHz.

10. The device according to any one of claims 1 to 9,

wherein the plurality of IO signals of the external interface comprise at least one of: data signals, address signals.

11. An apparatus, comprising:

a first circuit for calculating a sequence of values of the internal bus bar inversion signal based on a sequence of values of the plurality of internal signals;

a second circuit for establishing a sequence of values of the external bus inversion signal by selecting between the sequence of values of the internal bus inversion signal and a substantially random sequence of values; and

a third circuit to: setting values of a plurality of external input/output (IO) signals to inverted values of the plurality of internal signals when the sequence of respective corresponding values of the external bus inversion signal has a first value, and setting values of the plurality of external IO signals to values of the plurality of internal signals when the sequence of respective corresponding values of the external bus inversion signal has a second value.

12. The apparatus as set forth in claim 11, wherein,

wherein the sequence of substantially random values is based on at least a sequence of pseudo-random values generated by a pseudo-random number generator (PRNG) circuit.

13. The apparatus as set forth in claim 12,

wherein the second circuit selects the sequence of values of the internal bus inversion signal when the counter circuit does not match a predetermined count value, and the second circuit selects the sequence of substantially random values when the counter circuit matches the predetermined count value.

14. The apparatus as set forth in claim 11, wherein,

wherein the external interface is a chip-to-chip communication interface.

15. The apparatus as set forth in claim 11, wherein,

wherein the sequence of substantially random values satisfies a predetermined minimum slew rate for at least one of the plurality of IO signals of the external interface.

16. The apparatus of any one of claims 11 to 15,

wherein the internal bus inversion signal is determined to reduce at least one of: a Simultaneous Switching Output (SSO) attribute of the plurality of IO signals of the external interface, a Simultaneous Switching Noise (SSN) attribute of the plurality of IO signals of the external interface.

17. A system comprising a memory, a processor coupled with the memory, and a wireless interface to allow the processor to communicate with another device, the processor comprising:

a first circuit for calculating a value of an internal bus inversion signal based on values of a plurality of internal signals;

a second circuit for determining a value of a bus inversion signal of an external interface based on a value of the internal bus inversion signal and a random inversion component; and

a third circuit to: setting values of a plurality of input/output (IO) signals of the external interface to inverted values of the plurality of internal signals when the bus inversion signal of the external interface has a first value, and setting values of the plurality of IO signals of the external interface to values of the plurality of internal signals when the bus inversion signal of the external interface has a second value.

18. The system of claim 17, wherein the first and second sensors are arranged in a single unit,

wherein the second circuit further determines a value of the bus inversion signal based on an output of a counter circuit.

19. The system of claim 17, wherein the first and second sensors are arranged in a single unit,

wherein the plurality of IO signals of the external interface are clocked at a frequency of at least 1 GHz.

20. The system of any one of claims 17 to 19,

wherein the external interface is a memory access interface.

21. A method, comprising:

calculating a value of an internal bus inversion signal based on values of the plurality of internal signals;

determining a value of a bus inversion signal of an external interface based on the value of the internal bus inversion signal and a random inversion component; and is

Setting values of a plurality of input/output (IO) signals of the external interface based on values of the plurality of internal signals and values of the bus inversion signal of the external interface.

22. The method of claim 21, wherein setting values of a plurality of IO signals of the external interface is performed when the bus inversion signal of the external interface has a first value; and wherein setting the values of the plurality of IO signals of the external interface to the values of the plurality of internal signals is performed when the bus inversion signal of the external interface has a second value.

23. The method of claim 21, wherein the random upset component is based on at least an output of a Pseudo Random Number Generator (PRNG) circuit.

24. The method of claim 21, wherein determining the value of the bus invert signal of the external interface is further based on an output of a counter circuit.

25. The method of claim 21, wherein the random rollover component is generated to satisfy a predetermined minimum rollover rate for at least one of the plurality of IO signals of the external interface.

Background

Modern chip-to-chip parallel interfaces may include relatively wide input/output (IO) buses with clock frequencies in excess of 1 gigahertz (GHz). A wide IO bus may cause various Signal Integrity (SI) problems, such as effects related to Simultaneous Switching Noise (SSN). When multiple IO output drivers switch simultaneously, they may cause a voltage drop in chip power distribution or package power distribution, and may momentarily raise the ground voltage within the device relative to system ground. For example, SSN may be related to inductance that may exist between device ground and system ground, Simultaneous Switching Output (SSO) count of the interface, and slew rate of the Output driver.

One feature of the chip-to-chip interface that may reduce SSN is a Bus Inversion (BI) signal that indicates whether data currently being transmitted on the interface is inverted. Using the BI signal, either non-inverted data or inverted data may be selected for transmission, depending on which data will have a lower SSO count. One example implementation of BI logic may be to count the total number of bits in the covered bus that have a first value (e.g., a "1" value). If the total number is greater than half the width of the covered bus, the BI bit may be set to a predetermined value (e.g., a "1" value) and the inverted data may be sent on the interface. Doing so may facilitate keeping the SSO count on the covered bus at or below half the width of the covered bus on a continuous basis, and thus may constrain the level of SSN corresponding to the covered bus.

For a synchronous chip-to-chip interface, the associated clock IO signal may be constantly toggling, while other non-clock IO signals may be toggling at a much lower frequency. At high IO clock frequencies, the timing margin (timing margin) of the interface IO acting as a group synchronization may become so tight that time factors (such as transistor aging) that were negligible may become significant. At the same time, the use of BI signals may reduce the IO slew rate, which may affect various aspects of transistor aging and may in turn affect the timing margin of the interface IO.

Drawings

Embodiments of the present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure. However, while the drawings will aid in illustration and understanding, they are merely helpful and should not be construed to limit the disclosure to the specific embodiments depicted therein.

Fig. 1 illustrates a block diagram including a synchronous chip-to-chip interface, according to some embodiments of the present disclosure.

Fig. 2A and 2B illustrate cycle-by-cycle waveforms of internal and external signals, respectively, of a bus covered by a Bus Inversion (BI) signal, according to some embodiments of the present disclosure.

Fig. 3 illustrates a cycle-by-cycle waveform of an external signal of a bus covered by a BI bitstream having a random bit value at every kth bit position, according to some embodiments of the present disclosure.

Fig. 4 illustrates a diagram of a BI circuit implementing minimum slew rate guarantees, according to some embodiments of the present disclosure.

Fig. 5A and 5B illustrate cycle-by-cycle waveforms of non-interleaved and interleaved external signals, respectively, of two buses covered by a BI signal, according to some embodiments of the present disclosure.

Fig. 6 illustrates a method for implementing minimum rollover rate assurance, according to some embodiments of the present disclosure.

Fig. 7 illustrates a computing device with a mechanism for implementing minimum rollover rate guarantees, according to some embodiments of the present disclosure.

Detailed Description

In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art that the embodiments of the disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

Note that in the respective drawings of the embodiments, signals are represented by lines. Some lines may be thicker to indicate a greater number of constituent signal paths and/or have arrows at one or more ends to indicate the direction of information flow. Such indication is not intended to be limiting. Rather, these lines are used in conjunction with one or more exemplary embodiments to facilitate easier understanding of circuits or logic elements. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented using any suitable type of signal scheme.

Throughout the specification and in the claims, the term "connected" means a direct electrical, mechanical, or magnetic connection between the things that are connected, without any intervening devices. The term "coupled" means either a direct electrical, mechanical, or magnetic connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices. The term "circuit" or "module" may refer to one or more passive and/or active components arranged to cooperate with one another to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a" and "the" includes plural references. The meaning of "in … …" includes "in … …" and "on … …".

The terms "substantially", "close", "approximately" and "approximately" generally refer to being within +/-10% of a target value. Unless otherwise specified the use of the ordinal adjectives "first", "second", and "third", etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.

It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.

The terms "left," "right," "front," "back," "top," "bottom," "over," "under," and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions.

For purposes of the embodiments, the transistors in the various circuits, modules and logic blocks are Tunnel FETs (TFETs). Some transistors of the various embodiments may include Metal Oxide Semiconductor (MOS) transistors that include a drain terminal, a source terminal, a gate terminal, and a body terminal. Transistors may also include tri-gate and FinFET transistors, fully wrapped-gate cylinder transistors, square wire, or rectangular strip transistors, or other devices like carbon nanotubes or spin devices that perform the function of a transistor. The symmetrical source and drain terminals of the MOSFET are the same terminal and may be used interchangeably herein. TFET devices, on the other hand, have asymmetric source and drain terminals. Those skilled in the art will appreciate that other transistors (e.g., bipolar junction transistors-BJTs PNP/NPN, BiCMOS, CMOS, etc.) may be used for some of the transistors without departing from the scope of the present disclosure.

For the purposes of this disclosure, the phrases "a and/or B" and "a or B" mean (a), (B), or (a and B). For the purposes of this disclosure, the phrase "A, B and/or C" means (a), (B), (C), (a and B), (a and C), (B and C), or (A, B and C).

Furthermore, the various elements of combinational and sequential logic discussed in this disclosure may relate to both physical structures (e.g., and, or exclusive or), and synthesized or otherwise optimized sets of devices that implement logic structures that are boolean equivalents of the discussed logic.

Modern chip-to-chip parallel interfaces with relatively wide input/output (IO) buses may employ a Bus Inversion (BI) signal, which may indicate whether data currently being transmitted on the interface is inverted, to reduce Simultaneous Switching Noise (SSN) effects. However, the BI signal may reduce the IO slew rate. Further, the reduced slew rate may affect various aspects of transistor aging and, thus, may affect the timing margin of the interface IO. When individual IOs are affected by different transistor aging factors, the timing margin of the entire interface may eventually be affected due to the aging effect of the aggregation.

Transistor aging can occur when Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device characteristics degrade over time, typically long periods of time measured in years. Device characteristic degradation may lead to a decrease in switching speed and may eventually accelerate the end of life of the device. Transistor aging may occur for both transistors inside the die and transistors at the IO buffer. The main causes of transistor aging may include: hot Carrier Injection (HCI), Bias Temperature Instability (BTI), and Time-Dependent Dioxide Breakdown (TDDB).

HCI is associated with the flow of high energy carriers through the device channel and injecting themselves into the dielectric layer of the transistor. As a result of HCI, the threshold voltage may gradually decrease, which may result in slower switching speeds over time. The HCI effect cannot be recovered by reversing the state of the transistor.

BTI is a degradation phenomenon (most pronounced in p-channel MOSFETs) that can occur with negative gate voltages at elevated temperatures. The associated electric field may fill some pre-existing traps in the dielectric block with carriers from the channel. When the stress voltage is removed, the BTI degradation will recover over time (e.g., a few microseconds).

TDDB is related to the electric field that randomly causes defects in the dielectric due to electron tunneling. When a conductive path between the gate and the substrate is formed, a permanent breakdown may occur.

Furthermore, IO aging delays may occur in different voltage transition directions. For example, due to the BTI effect, some IOs may acquire a faster 0-to-1 transition time and a slower 1-to-0 transition time by staying at a high voltage level (e.g., "1") for a long period of time. Alternatively, some IOs may acquire a slower 0-to-1 transition time due to HCI effects.

Various mechanisms and methods are disclosed herein for mitigating aging effects on timing margins that may cause all data IO of a covered bus to age at substantially the same speed and in substantially the same voltage transition direction as a clock signal of the covered bus. This may be achieved by flipping the data IO at a flip rate equal to or higher than the lowest flip rate r (where 0< r < 1). For example, for a defined number of clock cycles C, all data IO will be flipped at least r × C times.

With the minimum slew rate guarantee, the BTI effect can be minimized and all IOs of the overlaid bus can age at a substantially synchronous rate. Simulations indicate that a small lowest slew rate (e.g., 5%) can significantly reduce the loss of timing margin due to aging effects.

Although the aging effect may be exacerbated by the use of the BI signals, the BI signals may advantageously be utilized to ensure a minimum slew rate by occasionally or periodically repurposing them for IO slew rather than for reducing SSN. Using the BI signal, randomized flipping can be introduced on the data IO without regard to the traffic pattern on the data IO, so that a minimum flipping rate guarantee can be achieved without any cost in terms of data bandwidth at the interface.

Such a design may have various advantages. First, they may not require any logic to monitor the slew rate (e.g., of individual IOs) and thus may have lower hardware overhead. Second, they may not be compliant with traffic patterns and may have no impact on user traffic (in other words, the presence of the lowest roll-over-rate logic may be transparent to the user). Third, they may not consume any data bandwidth and thus may be used in any application scenario. Fourth, they can have lower hardware implementation costs.

The minimum slew rate guarantee may affect SSN reduction because SSN may be higher in the period in which the BI signal is repurposed for IO toggling. However, this effect can be mitigated in various ways. First, the guaranteed minimum slew rate may be set to the minimum number (e.g., 5%) desired to mitigate aging effects. Second, the period in which the BI signal is repurposed may be broken up, which may allow SSN effects to not accumulate. Third, for interfaces with multiple BI groups, different BI groups may have their BI signals repurposed in different cycles so that the impact on SSN reduction may be limited to one BI group at a time.

The mechanisms and methods disclosed herein may include a digital system for randomly flipping IO signals to establish a minimum flipping rate guarantee. These systems may utilize the BI signal to apply a substantially arbitrarily modified or randomly modified BI bitstream to a bus covered by the BI signal (e.g., to a set of signals, which may include data signals), and thus, these systems may flip those data IOs at a designed lowest flip rate. These mechanisms and methods may advantageously have no impact on user traffic and may advantageously be independent of user traffic patterns.

Fig. 1 illustrates a block diagram including a synchronous chip-to-chip interface, according to some embodiments of the present disclosure. The system 100 includes a first chip 111, a second chip 112, and at least a first chip-to-chip interface 121. In various embodiments, system 100 may also include one or more additional chip-to-chip interfaces, starting with a second chip-to-chip interface, and so on, up to an nth chip-to-chip interface 129.

The first to nth interfaces 121 to 129 may include a clock signal, a plurality of overlaid bus signals (e.g., data signals), and a BI signal overlaying the plurality of bus signals. These may be the output of the first chip 111 and the input of the second chip 112. In the system 100, there may also be multiple inputs to the first chip 111, which are outputs of the second chip 112 (which may be portions of the first to nth interfaces 121 to 129, respectively, in some embodiments). In various embodiments, the first to nth interfaces 121 to 129 may be synchronous interfaces.

The BI signals of the first to nth interfaces 121 to 129 may indicate to the receiving device (e.g., the second chip 112) whether the transmission on the overlaid bus signal (e.g., data) is inverted or non-inverted. The covered IO pin may be driven to an inverted value when the corresponding BI signal has a predetermined value (e.g., has a "1" value), and may be driven to a non-inverted value (e.g., a normal value) when the corresponding BI signal does not have the predetermined value (e.g., has a "0" value).

Fig. 2A and 2B illustrate cycle-by-cycle waveforms of internal and external signals, respectively, of a bus overlaid by a BI signal, according to some embodiments of the present disclosure. The covered bus may correspond to a set of internal signals D (which carry values before any potential inversion made by the BI signal) and a set of external signals D' (which carry values after any potential inversion made by the BI signal). The overlaid bus may send data in various "beats" relative to the corresponding clock signal. In some embodiments, there may be a single beat per clock cycle (e.g., the time between rising edges of the clock), while in other embodiments there may be two beats per clock cycle (as in double data rate signaling), or four beats per clock cycle (as in quadruple data rate signaling). For example, fig. 2A and 2B depict a clock with two beats per clock cycle (e.g., double data rate signaling).

On each beat, the value of the BI signal may be calculated according to a particular rule (e.g., whether the total number of 1 s of the covered bus signals is greater than the total number of 0 s of the covered bus signals). The BI signal may then be transmitted over the interface to the receiver along with the data.

The BI signal may have a first predetermined value (e.g., a "1" value) if it is to be indicated that the covered bus signal is inverted, and may have a second predetermined value (e.g., a "0" value) to indicate that the covered bus signal is not inverted. (in various embodiments, the behavior of the internal signal may also correspond to the behavior of the corresponding external signal when BI mode is not enabled for the interface; accordingly, the value of the internal signal may only be driven onto the external signal without inversion when BI mode is disabled.)

Thus, in fig. 2A, the internal signals 210 may include a first bus signal 211, a second bus signal 212, and a clock signal 219. Within eight beats of the depicted four clock cycles, the clock signal 219 may flip eight times, the first overlay bus signal 211 may flip 3 times, and the second overlay bus signal 212 may flip 6 times. The first bus signal 211 and the second bus signal 212 are not yet covered by the BI signal.

In fig. 2B, the external signals 220 may include a first bus signal 221, a second bus signal 222, and a clock signal 229. The clock signal 229 may be toggled eight times, as with the clock signal 219 (of the internal signal 210), for eight beats of the depicted four clock cycles. However, the first bus signal 221 and the second bus signal 222 of the external signal 220 are overwritten by the BI signal 228 as compared to the internal signal 210.

In the fourth depicted beat of fig. 2B, the BI signal 228 has a predetermined value (in this example, the value is "1"). As a result, in the beat, the values of the first bus signal 211 and the second bus signal 212 of the internal signal 210 are inverted to become the values of the first bus signal 221 and the second bus signal 222 of the external signal 220. After application of the BI signal 228, the flip count of the first bus signal 221 in the 8-beat duration changes from 3 to 5, while the flip count of the second bus signal 222 remains unchanged. (the flip count of the BI signal 228 itself is 2.) thus, the BI signal 228 may increase the flip rate of the covered bus.

In a sequence of N data beats, consecutive BI bits may constitute an N-bit BI bitstream. Fig. 3 illustrates a cycle-by-cycle waveform of an external signal of a bus covered by a BI bitstream having a random bit value at every kth bit position, according to some embodiments of the present disclosure. Waveform 300 may include clock signal 309 and one or more external bus signals 301 that are overlaid by BI signal 308.

In various embodiments, to provide the minimum roll-over-rate guarantee, a subset of the values of the N-bit BI bitstream may be replaced with random values (e.g., substantially arbitrarily determined values or substantially randomly determined values). For example, every kth bit of a BI bitstream may be assigned a random bit value r_iInstead of (where 0<＝i<＝N/k)。

For random bit values r_i|0<＝i<N/k, each bit value has an equal probability of "0" or "1" (e.g., P { r })_i＝1}＝P{r_i0} 0.5). The BI bitstream may be considered to have substream { b }_i|0<＝i<N/k, the substream includes every kth bit of the BI bitstream. Sub-stream b_iWill have a value that is inverted relative to the value they had before the random bit value substitution occurred.

After the covered bus is inverted (or not) according to the modified BI bitstream, the covered bus will be inverted in some cases where it will not be inverted by the original BI bitstream, and will not be inverted in some cases where it will be inverted by the original BI bitstream. Suppose substream b in the original BI bitstream_iIn (b), the number of 1's is different from the number of 0's (e.g., C (b)_iX, C (bi-0) y, and x! Y), then by passing a random BI stream { r }_iApplied to substream b of the original BI bitstream_iAbout half of the 1 will be inverted to 0 and about half of the 0 will be inverted to 1. As a result, if the length N of the BI bitstream is large enough, the bitstreamThe final counts of 1 and 0 in (d) will converge toward x/2 and y/2 respectively (e.g.,). Thus, random bits are applied to the non-random substream b_iWill cause the latter to become a random bit stream.

Furthermore, the expected turnover rate for any random bit stream is 50% in terms of turnover rate. At any given pointTime t, random bit stream r_i|0<＝i<Has the value r_t(wherein 0)<t<N-1). In the next cycle, at a subsequent time, a new value r_t+1 causes the flip (e.g., r)_t+1！＝r_t) The probability of (c) is 50%. As a result, the expected roll-over Rate for the entire bitstream is E [ Rate ]_toggle]＝50％。

Since the sub-streams of the modified BI stream (e.g.,) The expected turnover rate of (c) is 50%, so its expected turnover count is 50% × N/k — N/2 k. Therefore, the lowest turnover rate of the entire data bit stream is (N/2 k)/N-1/2 k- (1/2) k.

Thus, by substituting random bits into the BI bitstream at every kth bit position, all data pins covered by the BI signal (as well as the BI pin itself) will have the expected lowest turnover rate of (1/2) k. Over time, the actual minimum slew rate may converge sufficiently toward the expected minimum slew rate so that the overlaid data pins will meet the minimum slew rate guarantee. For example, when the BI signal 308 has a random value for every kth bit of the BI bitstream, the external bus signal 301 covered by the BI signal 308 may have a guaranteed minimum slew rate of (1/2) k over a sufficiently long period of time.

Fig. 4 illustrates a diagram of a BI circuit implementing minimum slew rate guarantees, according to some embodiments of the present disclosure. Design 400 may include a first circuit 410, a second circuit 420, and a third circuit 430. The first circuit 410 may calculate a value of the internal BI signal 412 based on values of a plurality of internal input/output (IO) signals 402 (which may be internal signals of the covered bus). The second circuit 420 may determine a value of the BI signal 422 of the external interface based on both the value of the internal BI signal 412 and the random flip component. The third circuit 430 may set values of a plurality of IO signals 432 of the external interface based on values of the plurality of internal signals 402 and values of a BI signal 422 of the external interface.

In some embodiments, the first circuit 410 may calculate a sequence of values of the internal BI signals 412 based on a sequence of values of a plurality of internal input/output (IO) signals 402 (e.g., for SSN and/or SSO purposes). In various embodiments, the value of the internal BI signal 412 may be deterministic and may be calculated or otherwise determined for each beat of data on the bus. For some embodiments, internal BI signals 412 may be determined to reduce SSO properties of plurality of IO signals 432. In some embodiments, internal BI signals 412 may be determined to reduce SSN properties of plurality of IO signals 432.

For some embodiments, the second circuitry 420 may establish the sequence of values of the BI signal 422 by selecting between a sequence of values of the internal BI signal 412 and a substantially random sequence of values 417. In various embodiments, the second circuit 420 may include a multiplexer that selects between the internal BI signal 412 and the sequence of substantially random values 417. In some embodiments, a random flip component (which may be part of a substantially random sequence of values 417) may be generated by additional circuitry 415. In some embodiments, the additional circuitry 415 may be a Pseudo-Random Number Generator (PRNG) circuit, which may generate a stream of Pseudo-Random bits.

In some embodiments, the random inversion component may be generated to satisfy a predetermined minimum inversion rate for at least one of the plurality of IO signals 432. For some embodiments, the second circuit 420 may determine the value of the BI signal 422 based at least in part on the output of the additional circuitry 425. In some embodiments, the additional circuitry 425 may be a counter circuit that may count to a certain value (e.g., a predetermined constant k), flip the counter output 427, and then reset. As a result, the second circuit 420 may select between a sequence of values of the internal BI signal 412 and a sequence of substantially random values 417 every kth beat.

In some embodiments, the third circuit 430 may set the value of the IO signal 432 to the inverted value of the internal signal 402 when the sequence of values of the respective corresponding BI signal 422 has a first value, and set the value of the IO signal 432 to the value of the internal signal 402 when the sequence of values of the respective corresponding BI signal 422 has a second value.

In various embodiments, the external interface may be a chip-to-chip communication interface. For some embodiments, the plurality of IO signals 432 may be clocked at a frequency of at least 1 GHz. In some embodiments, the plurality of IO signals 432 may include at least one of data signals and address signals.

In various embodiments, internal signal 402 and external IO signal 432 may correspond to N signal paths (e.g., wires), while internal BI signal 412, external BI signal 422, basic random value 417, and counter output 427 may correspond to a single signal path. In various embodiments, streams of values may be transmitted over these signal paths (e.g., at a rate of one value per beat).

Fig. 5A and 5B illustrate cycle-by-cycle waveforms of non-interleaved and interleaved external signals, respectively, of two buses covered by a BI signal, according to some embodiments of the present disclosure. The first scenario 500 may include a first set of bus signals 511 covered by a first BI signal 518, a second set of bus signals 521 covered by a second BI signal 528, and a clock signal 509. The second scenario 550 may include a first set of bus signals 561 covered by a first BI signal 568, a second set of bus signals 571 covered by a second BI signal 578, and a clock signal 559.

In a scenario like the first scenario 500, there may be up to 100% SSO in the worst case if all random bits in the BI bitstream covering different sets of bus signals occur on the same cycle. For example, when the data bus is idle, all data bits may have a "0" value; then, if all the bank bus signals covered by the BI signal happen to have a randomly established value of "1", the entire data bus may be flipped, resulting in the worst SSN.

For chip-to-chip interfaces with multiple sets of bus signals covered by BI signals, this effect on SSN can be mitigated by interleaving (or temporally interleaving) random BI bit positions for different sets of bus signals. Thus, in a scenario like the second scenario 550, by interleaving the random bit positions of the different sets of bus signals covered by the BI signal, in the worst case, only a single set of data may be flipped. As a result, the worst case SSN may be reduced to 1/g of the total number of data IOs in the interface (where g may be the number of bus signal groups covered by the BI signals).

In some embodiments, random bit position interleaving may be achieved by initializing different counter circuits (e.g., additional circuit 425) for different sets of bus signals with different initial values.

Fig. 6 illustrates a method for implementing minimum rollover rate assurance, according to some embodiments of the present disclosure. In some embodiments, method 600 may include block 610, block 620, block 630, and block 640.

In block 610, a sequence of values of the internal bus inversion signal may be calculated based on a sequence of values of the plurality of internal signals. In block 620, a sequence of values of the external bus inversion signal may be established by selecting between a sequence of values of the internal bus inversion signal and a substantially random sequence of values.

In block 630, values of the plurality of external IO signals may be set to inverted values of the plurality of internal signals when the sequence of values of the respective corresponding external bus inversion signals has a first value. In block 640, the values of the plurality of external IO signals may be set to the values of the plurality of internal signals when the sequence of values of the respective corresponding external bus inversion signals has a second value.

In some embodiments, a substantially random sequence of values may be generated by the PRNG circuit. For some embodiments, the selection of the sequence of values may additionally be based on the output of the counter circuit. In some embodiments, the sequence of substantially random values may satisfy a predetermined minimum slew rate for at least one of the plurality of IO signals of the external interface. For some embodiments, the internal bus inversion signal may be determined to decrease at least one of: SSO attributes of the plurality of IO signals of the external interface, and SSN attributes of the plurality of IO signals of the external interface.

While the actions in the flow chart with reference to fig. 6 are shown in a particular order, the order of the actions may be modified. Thus, the illustrated embodiments may be performed in a different order, and some actions may be performed in parallel. Some of the acts and/or operations listed in fig. 6 may be optional in accordance with certain embodiments. The numbering of the acts is presented for the sake of clarity and is not intended to dictate the order in which the various acts must occur. Further, operations from the various flows may be utilized in various combinations.

In some embodiments, an apparatus may comprise means for performing various acts and/or operations of the method of fig. 6.

Fig. 7 illustrates a computing device with a mechanism for implementing minimum rollover rate guarantees, according to some embodiments of the present disclosure. The computing device 700 may be a computer System, System-on-a-Chip (SoC), a tablet device, a mobile device, a smart device, or a smartphone with a mechanism for implementing minimum roll-over rate guarantees according to some embodiments of the present disclosure. It will be understood that certain components of the computing device 700 are shown in outline, and that not all components of such a device are shown in fig. 7. Additionally, while some components may be physically separate, others may be integrated within the same physical package, or even integrated on the same physical silicon die. Thus, the separation between the various components depicted in FIG. 7 may not be physical, but may be functional in some cases. It is further noted that those elements of fig. 7 having the same names or reference numbers as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

In various embodiments, the components of computing device 700 may include any of the following: processor 710, audio subsystem 720, display subsystem 730, I/O controller 740, power management component 750, memory subsystem 760, connectivity component 770, one or more peripheral connections 780, and one or more additional processors 790. In some embodiments, processor 710 may include mechanisms for implementing minimum rollover rate guarantees in accordance with some embodiments of the present disclosure. For example, one or more chip-to-chip interfaces including the mechanisms discussed herein for achieving the lowest roll-over rate guarantee may exist between processor 710 and any of audio subsystem 720, display subsystem 730, I/O controller 740, power management component 750, memory subsystem 760, connectivity component 770, peripheral connections 780, and additional processors 790.

However, in various embodiments, any component of the computing device 700 may include a mechanism for implementing minimum roll-over-rate guarantees in accordance with some embodiments of the present disclosure. Further, one or more components of the computing device 700 may include an interconnect fabric having a plurality of ports, such as a router, a router Network, or a Network-on-a-Chip (NoC).

In some embodiments, computing device 700 may be a mobile device operable to use a flat surface interface connector. In one embodiment, the computing device 700 may be a mobile computing device, such as a computing tablet device, a mobile phone or smart phone, a wireless-enabled e-reader, or other wireless mobile device. Various embodiments of the present disclosure may also include a network interface 770 (e.g., a wireless interface) such that system embodiments may be incorporated into a wireless device, such as a cellular telephone or personal digital assistant.

The processor 710 may be a general purpose processor or CPU (central processing unit). In some embodiments, processor 710 may include one or more physical devices, such as a microprocessor, application processor, microcontroller, programmable logic device, or other processing means. The processing operations performed by processor 710 may include the execution of an operating platform or operating system on which application and/or device functions may subsequently be executed. The processing operations may also include operations relating to one or more of the following: audio I/O; displaying the I/O; power management; connecting the computing device 700 to another device; and/or I/O (input/output) with a human user or with other devices.

The audio subsystem 720 may include hardware components (e.g., audio hardware and audio circuits) and software components (e.g., drivers and/or codecs) associated with providing audio functionality to the computing device 700. The audio functions may include speaker and/or headphone output, as well as microphone input. Devices for such functionality may be integrated into computing device 700 or connected to computing device 700. In one embodiment, a user interacts with the computing device 700 by providing audio commands that are received and processed by the processor 710.

Display subsystem 730 may include hardware components (e.g., a display device) and software components (e.g., a driver) that provide visual and/or tactile displays for a user to interact with computing device 700. Display subsystem 730 may include a display interface 732, which may be a specific screen or hardware device for providing a display to a user. In one embodiment, display interface 732 includes logic separate from processor 710 for performing at least some processing related to displaying. In some embodiments, display subsystem 730 includes a touch screen (or touch pad) device that provides both output and input to a user.

I/O controller 740 may include hardware devices and software components related to interaction with a user. I/O controller 740 is operable to manage hardware that is part of audio subsystem 720 and/or display subsystem 730. Further, I/O controller 740 may be a connection point for additional devices connected to computing device 700 through which a user may interact with the system. For example, devices that may be attached to computing device 700 may include a microphone device, a speaker or stereo system, a video system or other display device, a keyboard or keypad device, or other I/O devices for use with a particular application, such as a card reader or other device.

As described above, I/O controller 740 may interact with audio subsystem 720 and/or display subsystem 730. For example, input through a microphone or other audio device may provide input or commands for one or more applications or functions of computing device 700. Further, audio output may be provided instead of, or in addition to, display output. In another example, if display subsystem 730 includes a touch screen, the display device may also act as an input device, which may be managed at least in part by I/O controller 740. There may also be additional buttons or switches on computing device 700 to provide I/O functions managed by I/O controller 740.

In some embodiments, I/O controller 740 manages devices such as accelerometers, cameras, light sensors, or other environmental sensors, or other hardware that may be included in computing device 700. The input may be part of direct user interaction, and may also provide environmental input to the system to affect its operation (e.g., filtering of noise, adjusting a display for brightness detection, applying a flash to a camera, or other features).

Power management component 750 may include hardware components (e.g., power management devices and/or circuitry) and software components (e.g., drivers and/or firmware) associated with managing battery power usage, battery charging, and features related to power saving operations.

Memory subsystem 760 may include one or more memory devices for storing information in computing device 700. Memory subsystem 760 may include non-volatile memory devices (whose state does not change if power to the memory device is interrupted) and/or volatile memory devices (whose state is indeterminate if power to the memory device is interrupted). Memory subsystem 760 may store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of computing device 700.

Portions of memory subsystem 760 may also be provided in the form of a non-transitory machine-readable medium for storing computer-executable instructions (e.g., instructions to implement any other processes discussed herein). The machine-readable medium may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, Phase Change Memories (PCMs), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, some embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).

The connectivity component 770 may include a network interface, such as the cellular interface 772 or the wireless interface 774 (so that embodiments of the computing device 700 may be incorporated into a wireless device, such as a cellular telephone or personal digital assistant). In some embodiments, the connectivity components 770 include hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers and/or protocol stacks) to enable the computing device 700 to communicate with external devices. Computing device 700 may include separate devices, such as other computing devices, wireless access points or base stations, and peripherals such as headsets, printers, or other devices.

In some embodiments, the connectivity component 770 may include a variety of different types of network interfaces, such as one or more wireless interfaces, for allowing the processor 710 to communicate with another device. In general, computing device 700 is illustrated with a cellular interface 772 and a wireless interface 774. Cellular interface 772 generally refers to a wireless interface to a cellular network provided by a wireless network operator, such as a cellular network provided via GSM or variants or derivations, CDMA (code division multiple access) or variants or derivations, TDM (time division multiplexing) or variants or derivations, or other cellular service standards. Wireless interface 774 generally refers to a non-cellular wireless interface and may include a personal area network (e.g., bluetooth, near field, etc.), a local area network (e.g., Wi-Fi), and/or a wide area network (e.g., WiMax), or other wireless communication.

Peripheral connection 780 may include hardware interfaces and connectors, as well as software components (e.g., drivers and/or protocol stacks) to make the peripheral connection. It will be understood that computing device 700 may be a peripheral to other computing devices (via "to" 782), or may have peripheral devices connected to it (via "from" 784). Computing device 700 may have a "docked" connector to connect to other computing devices, for example, to manage content (e.g., download and/or upload, change, synchronize) on computing device 700. Further, a docked connector may allow computing device 700 to connect to certain peripherals that allow computing device 700 to control content output, for example, to audiovisual or other systems.

In addition to proprietary docking connectors or other proprietary connection hardware, the computing device 700 may make peripheral connections 780 via common or standard-based connectors. Common types of connectors may include Universal Serial Bus (USB) connectors (which may include any of a variety of different hardware interfaces), DisplayPort or minidisplayport (mdp) connectors, High Definition Multimedia Interface (HDMI) connectors, Firewire connectors, or other types of connectors.

Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may", "might", or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, that does not mean there is only one of the element. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional element.

Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, the first embodiment may be combined with the second embodiment wherever particular features, structures, functions or characteristics associated with the two embodiments are not mutually exclusive.

While the present disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. For example, other memory architectures, such as Dynamic RAM (DRAM), may use the discussed embodiments. The embodiments of the present disclosure are intended to embrace all such alternatives, modifications and variances that fall within the broad scope of the appended claims.

Furthermore, for simplicity of illustration and discussion, and so as not to obscure the disclosure, well-known power/ground connections to Integrated Circuit (IC) chips and other components may or may not be shown in the presented figures. Additionally, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the following facts: the specific details regarding the implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specific details should be well within the purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

The following examples relate to further embodiments. The specific details in the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented for the method or process.

Example 1 provides an apparatus comprising: a first circuit for calculating a value of an internal bus inversion signal based on values of a plurality of internal signals; a second circuit for determining a value of a bus inversion signal of an external interface based on a value of the internal bus inversion signal and a random inversion component; and a third circuit for setting values of the plurality of IO signals of the external interface based on values of the plurality of internal signals and values of a bus inversion signal of the external interface.

In example 2, the apparatus of example 1, wherein the third circuit sets values of a plurality of IO signals of the external interface to inverted values of the plurality of internal signals when a bus inversion signal of the external interface has a first value; and wherein the third circuit sets values of a plurality of IO signals of the external interface to values of the plurality of internal signals when a bus inversion signal of the external interface has a second value.

In example 3, the apparatus of any of examples 1-2, wherein the random upset component is based at least on an output of a PRNG circuit.

In example 4, the apparatus of any of examples 1 to 3, wherein the second circuit further determines a value of a bus inversion signal of the external interface based on an output of a counter circuit.

In example 5, the apparatus of any of examples 1 to 4, wherein the random inversion component is generated to satisfy a predetermined minimum inversion rate for at least one of a plurality of IO signals of the external interface.

In example 6, the apparatus of any of examples 1 to 5, wherein the internal bus inversion signal is determined to reduce SSO properties of a plurality of IO signals of the external interface.

In example 7, the apparatus of any of examples 1 to 6, wherein the internal bus inversion signal is determined to lower SSN properties of a plurality of IO signals of the external interface.

In example 8, the apparatus of any one of examples 1 to 7, wherein the external interface is a chip-to-chip communication interface.

In example 9, the apparatus of any of examples 1 to 8, wherein the plurality of IO signals of the external interface are clocked at a frequency of at least 1 GHz.

In example 10, the apparatus of any of examples 1 to 9, wherein the plurality of IO signals of the external interface comprises at least one of: data signals, and address signals.

Example 11 provides an apparatus comprising: a first circuit for calculating a sequence of values of the internal bus bar inversion signal based on a sequence of values of the plurality of internal signals; a second circuit for establishing a sequence of values of the external bus inversion signal by selecting between the sequence of values of the internal bus inversion signal and a substantially random sequence of values; and a third circuit for setting values of a plurality of external IO signals to inverted values of the plurality of internal signals when a sequence of values of respective corresponding external bus inversion signals has a first value, and setting values of the plurality of external IO signals to values of the plurality of internal signals when a sequence of values of respective corresponding external bus inversion signals has a second value.

In example 12, the apparatus of example 11, wherein the sequence of substantially random values is based at least on a sequence of pseudo-random values generated by a PRNG circuit.

In example 13, the apparatus of any one of examples 12 to 12, wherein the second circuit selects the sequence of values of the internal bus inversion signal when the counter circuit does not match a predetermined count value and selects the sequence of substantially random values when the counter circuit matches the predetermined count value.

In example 14, the apparatus of any one of examples 12 to 13, wherein the external interface is a chip-to-chip communication interface.

In example 15, the apparatus of any of examples 12 to 14, wherein the sequence of substantially random values satisfies a predetermined minimum slew rate for at least one of the plurality of IO signals of the external interface.

In example 16, the apparatus of any of examples 12 to 15, wherein the internal bus inversion signal is determined to reduce at least one of: SSO attributes of a plurality of IO signals of the external interface, and SSN attributes of a plurality of IO signals of the external interface.

Example 17 provides a system comprising a memory, a processor coupled with the memory, and a wireless interface to allow the processor to communicate with another device, the processor comprising: a first circuit for calculating a value of an internal bus inversion signal based on values of a plurality of internal signals; a second circuit for determining a value of a bus inversion signal of an external interface based on a value of the internal bus inversion signal and a random inversion component; and a third circuit to set values of the plurality of IO signals of the external interface to inverted values of the plurality of internal signals when a bus inversion signal of the external interface has a first value, and to set values of the plurality of IO signals of the external interface to values of the plurality of internal signals when the bus inversion signal of the external interface has a second value.

In example 18, the system of example 17, wherein the second circuit further determines the value of the bus inversion signal based on an output of a counter circuit.

In example 19, the system of any of examples 17 to 18, wherein the plurality of IO signals of the external interface are clocked at a frequency of at least 1 GHz.

In example 20, the system of any of examples 17 to 19, wherein the external interface is a memory access interface.

Example 21 provides a method comprising: calculating a sequence of values of the internal bus bar inversion signal based on the sequence of values of the plurality of internal signals; establishing a sequence of values of an external bus inversion signal by selecting between the sequence of values of the internal bus inversion signal and a substantially random sequence of values; setting values of a plurality of external IO signals to inverted values of the plurality of internal signals when a sequence of values of respective corresponding external bus inversion signals has a first value; and setting the values of the plurality of external IO signals to the values of the plurality of internal signals when the sequence of the values of the respective corresponding external bus inversion signals has a second value.

In example 22, the method of example 21, wherein the sequence of substantially random values is generated by a PRNG circuit; and wherein the selection of the sequence of values is further based on an output of the counter circuit.

In example 23, the method of any of examples 21 to 22, wherein the sequence of substantially random values satisfies a predetermined minimum slew rate for at least one of a plurality of IO signals of the external interface.

In example 24, the method of any of examples 21 to 23, wherein the internal bus inversion signal is determined to reduce at least one of: SSO attributes of a plurality of IO signals of the external interface, and SSN attributes of a plurality of IO signals of the external interface.

The abstract is provided to allow the reader to ascertain the nature and gist of the technical disclosure. Digest is submitted under the following understanding: it is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.