阅读说明：本技术 一种三维铁电场效应晶体管存储单元、存储器及制备方法 (Three-dimensional ferroelectric field effect transistor storage unit, memory and preparation method ) 是由 曾斌建 周益春 廖敏 于 2020-06-30 设计创作，主要内容包括：一种三维铁电场效应晶体管存储单元、存储器及制备方法,该存储单元包括：栅电极层(4)；所述栅电极层(4)的厚度方向上设置有贯穿的第一通孔(14)；从所述第一通孔(14)的内壁向靠近轴线的方向上,依次覆盖有第一介质层(9)、铁电薄膜层(10)、第二介质层(11)和沟道层(12)；所述第一介质层(9)和第二介质层(11)均为绝缘材质,用于避免所述铁电薄膜层(10)与所述栅电极层(4)和沟道层(12)接触。该存储单元中,铁电薄膜层(10)不与栅电极(4)和沟道层(12)接触,避免了界面反应和元素扩散,从而保证了铁电薄膜层(10)和存储单元的质量和性能,减小了存储器中各存储单元之间的差异性,提高存储器的可靠性。(A three-dimensional ferroelectric field effect transistor memory cell, memorizer and preparation method, the memory cell includes: a gate electrode layer (4); a first through hole (14) penetrating through the gate electrode layer (4) is formed in the thickness direction of the gate electrode layer; a first dielectric layer (9), a ferroelectric film layer (10), a second dielectric layer (11) and a channel layer (12) are sequentially covered from the inner wall of the first through hole (14) to the direction close to the axis; the first dielectric layer (9) and the second dielectric layer (11) are made of insulating materials and are used for preventing the ferroelectric thin film layer (10) from being in contact with the gate electrode layer (4) and the channel layer (12). In the memory unit, the ferroelectric film layer (10) is not in contact with the gate electrode (4) and the channel layer (12), so that interface reaction and element diffusion are avoided, the quality and performance of the ferroelectric film layer (10) and the memory unit are ensured, the difference between the memory units in the memory is reduced, and the reliability of the memory is improved.)

1. A three-dimensional ferroelectric field effect transistor memory cell, comprising:

a gate electrode layer (4);

a first through hole (14) penetrating through the gate electrode layer (4) is formed in the thickness direction of the gate electrode layer;

a first dielectric layer (9), a ferroelectric film layer (10), a second dielectric layer (11) and a channel layer (12) are sequentially covered from the inner wall of the first through hole (14) to the direction close to the axis;

the first dielectric layer (9) and the second dielectric layer (11) are made of insulating materials and are used for preventing the ferroelectric thin film layer (10) from being in direct contact with the gate electrode layer (4) and the channel layer (12), so that the first dielectric layer (9) and the second dielectric layer (11) are both used as seed layers or stress control layers for growth of the ferroelectric thin film layer (10), generation of ferroelectric phases in the ferroelectric thin film layer (10) is promoted, and the storage unit achieves a storage function.

2. The three-dimensional ferroelectric field effect transistor memory cell of claim 1, further comprising:

a filling layer (13) disposed on an inner wall of the channel layer (12) for filling the first via hole (14).

3. The three-dimensional ferroelectric field effect transistor memory cell as claimed in claim 1 or 2,

the thickness of the channel layer (12) is not greater than the thickness of a depletion layer of the channel layer (12).

4. The three-dimensional ferroelectric field effect transistor memory cell as claimed in claim 1 or 2,

the channel layer (12) is made of polycrystalline silicon (Si), polycrystalline germanium (Ge), polycrystalline silicon germanium (SiGe) or doped polycrystalline silicon (Si), doped polycrystalline germanium (Ge) or doped polycrystalline silicon germanium (SiGe), and the doping elements are one or more of boron (B), phosphorus (P) and arsenic (As).

5. The three-dimensional ferroelectric field effect transistor memory cell as claimed in claim 1 or 2,

the ferroelectric thin film layer (10) is hafnium oxide (HfO)₂) Doped HfO₂Zirconium oxide (ZrO)₂) Or doped ZrO₂One of (1); wherein the doped HfO₂The element to be doped in (b) includes one or more of silicon (Si), aluminum (Al), zirconium (Zr), lanthanum (La), cerium (Ce), strontium (Sr), lutetium (Lu), gadolinium (Gd), scandium (Sc), neodymium (Nd), germanium (Ge), nitrogen (N), and the like.

6. The three-dimensional ferroelectric field effect transistor memory cell as claimed in claim 1 or 2,

the first dielectric layer (9) is silicon oxide (SiO)₂) Silicon nitride (Si)₃N₄) Silicon oxynitride (SiON), aluminum oxide (Al)₂O₃) Hafnium oxide (HfO)₂) Zirconium oxide (ZrO)₂) Titanium oxide (TiO)₂) Lanthanum oxide (La)₂O₃) Hafnium silicon oxynitride (HfSiON), germanium oxide (GeO)₂) One or more of (a).

7. The three-dimensional ferroelectric field effect transistor memory cell as claimed in claim 1 or 2,

the second dielectric layer (11) is silicon oxide (SiO)₂) Silicon nitride (Si)₃N₄) Silicon oxynitride (SiON), aluminum oxide (Al)₂O₃) Hafnium oxide (HfO)₂) Zirconium oxide (ZrO)₂) Titanium oxide (TiO)₂) Lanthanum oxide (La)₂O₃) Hafnium silicon oxynitride (HfSiON), germanium oxide (GeO)₂) And the like.

8. A three-dimensional ferroelectric field effect transistor memory, comprising: the memory cell array comprises a substrate (1), a common source (2), a plurality of selection transistors (6) and a plurality of groups of memory cell strings (5) vertical to the substrate (1);

wherein the memory cell string (5) consists of a plurality of three-dimensional ferroelectric field effect transistor memory cells as claimed in any one of claims 1 to 7 connected in series, with a spacer layer (3) being provided between the gate electrode layers (4) of adjacent three-dimensional ferroelectric field effect transistor memory cells;

the common source electrode (2) is arranged on the substrate (1);

each of the selection transistors (6) has one end disposed on the common source (2) and the other end having the memory cell string (5) disposed on a surface thereof.

9. The three-dimensional ferroelectric field effect transistor memory as claimed in claim 8,

the selection transistor (6) comprises a gate electrode layer (4), and an isolation layer (3) is arranged between the gate electrode layer (4) of the selection transistor (6) and the common source electrode (2);

a second through hole connected with the first through hole (14) is arranged in the thickness direction of the gate electrode layer (4) of the selection transistor (6);

a selection gate dielectric layer (7) and a selection channel layer (8) are sequentially covered from the inner wall of the second through hole to the direction close to the axis;

the top end of the selection channel layer (8) is closely connected to the bottom end of the channel layer (12) in the first via (14).

10. A preparation method of a three-dimensional ferroelectric field effect transistor memory is characterized by comprising the following steps:

s1, forming a common source (2) on the substrate (1);

s2, forming a plurality of selection transistors (6) on the common source (2);

s3, depositing an isolation layer (3) and a preset number of gate electrode layers (4) on the surface of the selection transistor (6) in an overlapped mode to form a stacked layer;

s4, forming a first through hole (14) with a preset size above the plurality of selection transistors (6), wherein the first through hole (14) penetrates through the stacked layers;

s5, sequentially depositing a first dielectric layer (9), a ferroelectric thin film layer (10) and a second dielectric layer (11) on the inner wall of the first through hole (14) in the direction close to the axis;

s6, removing the second dielectric layer (11), the ferroelectric thin film layer (10) and the first dielectric layer (9) deposited at the bottom of the first through hole (14) in sequence by adopting an etching method so as to enable the first through hole (14) to penetrate to the top of the selection transistor (6);

s7, depositing a channel layer (12) with a preset thickness on the inner wall of the second medium layer (11);

s8, depositing a filling layer (13) on the inner wall of the channel layer (12) to fill the first through hole (14).

Technical Field

The invention relates to the field of memories, in particular to a three-dimensional ferroelectric field effect transistor memory unit, a memory and a preparation method.

Background

Flash memory is currently the mainstream of non-volatile memory. In recent years, in order to meet the growing demand for mass data storage, the manufacturing technology of flash memories has shifted from planar two-dimensional integration to three-dimensional integration. However, flash memory has the disadvantages of high operating voltage (typically greater than 10V, even 15V) and slow access speed (1 ms), making it difficult to meet the development of future information technology. Thus, a new high-density nonvolatile memory having high speed, low power consumption, and high reliability has been receiving attention and research.

The ferroelectric field effect transistor (FeFET) is a ferroelectric thin film material replacing a gate dielectric layer in a field effect transistor (MOSFET), and the ferroelectric thin film material is changed in polarization direction to control the on and off of channel current, thereby realizing the storage of information. The FeFET memory has the advantages of nonvolatility, low power consumption, high read-write speed and the like, and the unit structure is simple and the theoretical storage density is high. In particular, fefets enable three-dimensional integration and are considered one of the most promising new high-density memories.

At present, the defects of the existing three-dimensional FeFET memory are researched as follows: the uniformity and electrical performance of the memory are poor; secondly, in the preparation process, the interface defects between the ferroelectric thin film layer and the channel layer are more, so that the fatigue performance of the device is poor, the difference between the threshold voltage and the sub-threshold swing amplitude of the device is larger, and the reliability of the memory is poor.

Disclosure of Invention

Objects of the invention

The invention aims to provide a three-dimensional ferroelectric field effect transistor storage unit, a three-dimensional ferroelectric field effect transistor storage device and a preparation method of the three-dimensional ferroelectric field effect transistor storage unit. In the storage unit, the first dielectric layer and the second dielectric layer are arranged, so that the ferroelectric thin film layer is not in direct contact with the gate electrode and the channel layer, element diffusion in the ferroelectric thin film and interface reaction between the ferroelectric thin film layer and the gate electrode and the channel layer are avoided, generation of a ferroelectric phase in the ferroelectric thin film layer is promoted, quality and performance of the ferroelectric thin film layer and the storage unit are further guaranteed, difference between the storage units is reduced, reliability of the storage is improved, in addition, leakage current can be reduced by adding the first dielectric layer and the second dielectric layer, and reliability of the storage is further improved.

(II) technical scheme

To solve the above problems, a first aspect of the present invention provides a three-dimensional ferroelectric field effect transistor memory cell comprising: a gate electrode layer; a first through hole penetrating through the gate electrode layer is formed in the thickness direction of the gate electrode layer; a first dielectric layer, a ferroelectric film layer, a second dielectric layer and a channel layer are sequentially covered from the inner wall of the first through hole to the direction close to the axis; the first dielectric layer and the second dielectric layer are made of insulating materials and are used for preventing the ferroelectric thin film layer from contacting the gate electrode layer and the channel layer, the first dielectric layer and the second dielectric layer are used as seed layers or stress control layers for growth of the ferroelectric thin film layer, generation of ferroelectric phases in the ferroelectric thin film layer is promoted, the ferroelectric thin film layer is guaranteed to have excellent ferroelectric performance, and the storage function of the three-dimensional ferroelectric field effect transistor storage unit is achieved.

In the memory cell, the polarization direction of the ferroelectric thin film layer is changed through the direction of voltage applied to the gate electrode layer, so that the conduction and the cut-off of the channel layer are realized, and the memory function of the three-dimensional ferroelectric field effect transistor memory cell is further realized.

According to the memory unit provided by the invention, the ferroelectric thin film layer is isolated through the first dielectric layer and the second dielectric layer, and the direct contact between the ferroelectric thin film layer and the gate electrode and the channel layer is avoided, so that the element diffusion in the ferroelectric thin film and the interface reaction between the element diffusion and the gate electrode and the channel layer are avoided, the quality and the performance of the ferroelectric thin film layer and the memory unit are further ensured, the difference between the memory units is reduced, the reliability of the memory is improved, in addition, the leakage current can be reduced by adding the first dielectric layer and the second dielectric layer, and the reliability of the memory is further improved.

Preferably, the storage unit further includes: and the filling layer is arranged on the inner wall of the channel layer and is used for filling the first through hole.

In the memory cell provided by the invention, the filling layer is arranged in the channel layer, and the first through hole is filled by the filling layer, so that compared with the prior art, the volume of the polycrystalline channel layer in the device is reduced, the defects in the channel layer can be reduced, the fatigue performance of the device is promoted, and the difference between the devices is improved.

Further preferably, the thickness of the channel layer is not greater than the thickness of a depletion layer of the channel layer.

Preferably, the first dielectric layer is silicon oxide (SiO)₂) Silicon nitride (Si)₃N₄) Silicon oxynitride (SiON), aluminum oxide (Al)₂O₃) Hafnium oxide (HfO)₂) Zirconium oxide (ZrO)₂) Titanium oxide (TiO)₂) Lanthanum oxide (La)₂O₃) Hafnium silicon oxynitride (HfSiON), germanium oxide (GeO)₂) One or more of; the second dielectric layer is silicon oxide (SiO)₂) Silicon nitride (Si)₃N₄) Silicon oxynitride (SiON), aluminum oxide (Al)₂O₃) Hafnium oxide (HfO)₂) Zirconium oxide (ZrO)₂) Titanium oxide (TiO)₂) Lanthanum oxide (La)₂O₃) Hafnium silicon oxynitride (HfSiON), germanium oxide (GeO)₂) And the like.

Preferably, the ferroelectric thin film layer is hafnium oxide (HfO)₂) Doped HfO₂Zirconium oxide (ZrO)₂) Or doped ZrO₂One of (1); wherein the doped HfO₂The element to be doped in (b) includes one or more of silicon (Si), aluminum (Al), zirconium (Zr), lanthanum (La), cerium (Ce), strontium (Sr), lutetium (Lu), gadolinium (Gd), scandium (Sc), neodymium (Nd), germanium (Ge), nitrogen (N), and the like.

In still another aspect of the present invention, there is provided a three-dimensional ferroelectric field effect transistor memory comprising: the memory cell array comprises a substrate, a common source electrode, a plurality of selection transistors and a plurality of groups of memory cell strings vertical to the substrate; wherein the memory cell string is composed of a plurality of the three-dimensional ferroelectric field effect transistor memory cells of the first aspect connected in series; the common source electrode is arranged on the substrate; one end of each selection transistor is arranged on the common source electrode, and the surface of the other end of each selection transistor is provided with the storage unit string.

In another aspect of the present invention, a method for manufacturing a three-dimensional ferroelectric field effect transistor memory is provided, including: s1, forming a common source electrode on the substrate; s2, forming a plurality of selection transistors on the common source electrode; s3, depositing an isolation layer and a preset number of gate electrode layers on the surface of the selection transistor in an overlapped mode to form a stacked layer; s4, forming a first through hole with a preset size above the plurality of selection transistors, wherein the first through hole penetrates through the stacked layers; s5, depositing a first dielectric layer, a ferroelectric film layer and a second dielectric layer in sequence on the inner wall of the first through hole in the direction close to the axis; s6, removing the second dielectric layer, the ferroelectric film layer and the first dielectric layer deposited at the bottom of the first through hole in sequence by adopting an etching method so as to enable the first through hole to penetrate to the top of the selection transistor; s7, depositing a channel layer with a preset thickness on the inner wall of the second medium layer; s8, depositing a filling layer on the inner wall of the channel layer to fill the first via hole.

(III) advantageous effects

The technical scheme of the invention has the following beneficial technical effects:

in the memory unit provided by the invention, the first dielectric layer and the second dielectric layer are arranged, so that the ferroelectric thin film layer is not in direct contact with the gate electrode and the channel layer, element diffusion in the ferroelectric thin film and interface reaction between the ferroelectric thin film and the gate electrode and the channel layer are avoided, the quality and performance of the ferroelectric thin film layer and the memory unit are further ensured, the difference between the memory units is reduced, the reliability of the memory is improved, in addition, the leakage current can be reduced by adding the first dielectric layer and the second dielectric layer, and the reliability of the memory is further improved.

Drawings

FIG. 1 is a schematic structural diagram of a memory cell according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a memory according to an embodiment of the present invention;

FIG. 3 is a flow chart illustrating a method for manufacturing a memory according to an embodiment of the invention;

FIG. 4a is a schematic diagram of a common source formed on a substrate according to an embodiment of the present invention;

FIG. 4b is a schematic diagram of a select transistor fabricated on a common source according to one embodiment of the present invention;

FIG. 4c is a schematic diagram of forming gate electrodes of a plurality of memory cells on a select transistor according to one embodiment of the present invention;

FIG. 4d is a schematic diagram of a first via formed over a gate electrode of a memory cell according to an embodiment of the present invention;

FIG. 4e is a schematic diagram of the formation of a first dielectric layer, a ferroelectric thin film layer and a second dielectric layer according to one embodiment of the present invention;

fig. 4f is a schematic diagram of forming a memory cell string according to an embodiment of the present invention.

Reference numerals:

1: a substrate; 2: a common source electrode; 3: an isolation layer; 4: a gate electrode layer; 5: storing the cell string; 6: a selection transistor; 7: selecting a gate dielectric layer; 8: selecting a channel layer; 9: a first dielectric layer; 10: a ferroelectric thin film layer; 11: a second dielectric layer; 12: a channel layer; 13: a filling layer; 14: a first via.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings in conjunction with the following detailed description. It should be understood that the description is intended to be exemplary only, and is not intended to limit the scope of the present invention. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present invention.

In the drawings a schematic view of a layer structure according to an embodiment of the invention is shown. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.

It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it should be noted that the terms "first", "second", and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.

Before explaining the present invention in detail, the inventor of the present invention found in the research process that the gate electrode and the ferroelectric thin film layer are easy to generate an interface layer in the preparation process of the existing memory, and the quality of the interface layer is difficult to control, thereby affecting the uniformity and the electrical performance of the ferroelectric thin film layer and the memory.

Fig. 1 is a schematic structural diagram of a memory cell according to an embodiment of the present invention.

As shown in fig. 1, the memory cell includes: a gate electrode layer 4; the gate electrode layer 4 is provided with a first through hole 14 penetrating in the thickness direction.

The first medium layer 9, the ferroelectric thin film layer 10, the second medium layer 11 and the channel layer 12 are sequentially covered from the inner wall of the first through hole 14 to the direction close to the axis.

The first dielectric layer 9 and the second dielectric layer 11 are both made of insulating materials, and are used for preventing the ferroelectric thin film layer 10 from contacting the gate electrode layer 4 and the channel layer 12, and the first dielectric layer 9 and the second dielectric layer 11 are both used as seed layers or stress control layers for growth of the ferroelectric thin film layer 10, so that generation of ferroelectric phases in the ferroelectric thin film layer 10 is promoted, the ferroelectric thin film layer 10 has excellent ferroelectric properties, and the storage function of a storage unit is ensured.

The ferroelectric thin film layer 10 serves as a storage medium.

The principle of the memory cell is that the polarization direction of the ferroelectric thin film layer 10 is changed by the direction of a voltage applied to the gate electrode layer 4, thereby turning on and off the channel layer 12 to realize a memory function.

In one embodiment, the memory cell is further provided with a filling layer 13 disposed on the inner wall of the channel layer 12 for filling the first via 14.

In the embodiment, the filling layer 13 is added to the channel layer 12, which is equivalent to reducing the volume of the channel layer 12 in the device, so that defects in the channel layer 12 can be reduced, which is helpful to improve the fatigue performance of the device and improve the variability between devices.

Preferably, the thickness of the channel layer 12 is not greater than the thickness of the depletion layer of the channel layer 12.

The depletion layer is a high-resistance region of a semiconductor material in which the number of carriers is very small. In this embodiment, carriers in the channel layer are depleted by repulsion of polarization of the ferroelectric thin film layer, so that the entire channel layer becomes a high resistance region, i.e., a depletion layer. The width of the depletion layer is related to the material properties, temperature and the magnitude of the bias voltage.

Preferably, the first dielectric layer 9 is silicon oxide (SiO)₂) Silicon nitride (Si)₃N₄) Silicon oxynitride (SiON), aluminum oxide (Al)₂O₃) Hafnium oxide (HfO)₂) Zirconium oxide (ZrO)₂) Titanium oxide (TiO)₂) Lanthanum oxide (La)₂O₃) Hafnium silicon oxynitride (HfSiON), germanium oxide (GeO)₂) One or more of (a).

The second dielectric layer 11 is silicon oxide (SiO)₂) Silicon nitride (Si)₃N₄) Silicon oxynitride (SiON), aluminum oxide (Al)₂O₃) Hafnium oxide (HfO)₂) Zirconium oxide (ZrO)₂) Titanium oxide (TiO)₂) Lanthanum oxide (La)₂O₃) Hafnium silicon oxynitride (HfSiON), germanium oxide (GeO)₂) And the like.

Preferably, the ferroelectric thin film layer 10 is hafnium oxide (HfO)₂) Doped HfO₂Zirconium oxide (ZrO)₂) Or doped ZrO₂One of (1); wherein the doped HfO₂The element to be doped in (b) includes one or more of silicon (Si), aluminum (Al), zirconium (Zr), lanthanum (La), cerium (Ce), strontium (Sr), lutetium (Lu), gadolinium (Gd), scandium (Sc), neodymium (Nd), germanium (Ge), nitrogen (N), and the like.

Preferably, the channel layer 12 is polysilicon (Si), poly-germanium (Ge), poly-silicon germanium (SiGe), or doped polysilicon (Si), doped poly-germanium (Ge), doped poly-silicon germanium (SiGe), and the doping element is one or more of boron (B), phosphorus (P), and arsenic (As).

The filler layer 13 includes, but is not limited to, SiO₂SiON and Si₃N₄。

In the memory unit provided by the embodiment of the invention, the first dielectric layer 9 is arranged between the ferroelectric thin film layer 10 and the control gate electrode layer 4, so that direct contact, element diffusion and chemical reaction between the ferroelectric thin film layer 10 and the control gate electrode layer 4 can be avoided; on the other hand, the second medium layer 11 is arranged between the ferroelectric thin film layer 10 and the polycrystalline channel layer 12, so that direct contact, element diffusion and chemical reaction between the ferroelectric thin film layer 10 and the polycrystalline channel layer 12 can be avoided; thereby ensuring the quality and performance of the ferroelectric film layer and the memory thereof; in addition, the first dielectric layer 9 and the second dielectric layer 11 can be used as seed layers or stress control layers for the growth of the ferroelectric thin film layer, so that the performance of the ferroelectric thin film layer 10 is improved, the leakage current can be effectively reduced, and the retention performance of the memory is improved.

Figure 2 is a schematic diagram of a three-dimensional ferroelectric field effect transistor memory structure according to one embodiment of the present invention,

as shown in fig. 2, the memory includes: a substrate 1, a common source 2, a plurality of select transistors 6 and a plurality of groups of memory cell strings 5 perpendicular to the substrate 1.

The memory cell string 5 is formed by connecting a plurality of three-dimensional ferroelectric field effect transistor memory cells in series, and the isolating layers 3 are arranged between the gate electrode layers 4 of the adjacent three-dimensional ferroelectric field effect transistor memory cells.

The common source electrode 2 is arranged on the substrate 1; each of the selection transistors 6 has one end disposed on the common source 2 and the other end having a memory cell string 5 disposed on a surface thereof.

It can be understood that the first through holes of the memory cells on the memory cell string 5 are all coaxially arranged, and the first dielectric layer 9, the ferroelectric thin film layer 10, the second dielectric layer 11, the channel layer 12 and the filling layer 13 of the previous memory cell are connected with the first dielectric layer 9, the ferroelectric thin film layer 10, the second dielectric layer 11, the channel layer 12 and the filling layer 13 of the next memory cell in a one-to-one correspondence.

In one embodiment, the selection transistor 6 comprises a gate electrode layer 4.

The gate electrode layer 4 of the selection transistor 6 is provided with a second via hole in the thickness direction, which communicates with the first via hole 14.

And a selection gate dielectric layer 7 and a selection channel layer 8 are sequentially covered from the inner wall of the second through hole to the direction close to the axis.

The top end of the selection channel layer 8 is closely connected to the bottom end of the channel layer 12 in the first via 14.

Preferably, the first through hole and the second through hole are coaxially arranged.

The diameter of the first through hole and the diameter of the second through hole may be the same or different.

Preferably, the diameter of the second through hole is larger than the diameter of the first through hole.

Preferably, an isolation layer 3 is further provided between the gate electrode layer 4 of the selection transistor 6 and the common source 2.

An isolation layer 3 is arranged between the gate electrode layers 4 of the adjacent three-dimensional ferroelectric field effect memory units.

In one embodiment, the isolation layer 3 is SiO₂Or from SiO, which has a dielectric constant ratio₂The insulating material having a small dielectric constant of (2).

In one embodiment, the gate electrode layer 4 is any one of heavily doped polysilicon, a nitride metal electrode, and tungsten W.

The common source 2 is a conductive layer formed on the substrate 1, including but not limited to forming a pn junction with the substrate 1, for example, if the substrate 1 is a p-type semiconductor, the common source 2 is a heavily doped n-type semiconductor.

The selection gate dielectric layer 7 is silicon oxide (SiO)₂) Silicon nitride (Si)₃N₄) Silicon oxynitride (SiON), aluminum oxide (Al)₂O₃) Hafnium oxide (HfO)₂) Zirconium oxide (ZrO)₂) Titanium oxide (TiO)₂) Lanthanum oxide (La)₂O₃) Hafnium silicon oxynitride (HfSiON), germanium oxide (GeO)₂) And the like.

Fig. 3 is a schematic flow chart of a method for manufacturing a memory according to an embodiment of the invention.

As shown in fig. 3, the method for manufacturing the memory includes: S1-S8.

S1, a common source 2 is formed on the substrate 1.

As shown in fig. 4a, ions may be implanted into the surface of the substrate 1 using an ion implantation process so that the common source 2 and the substrate 1 form a pn junction, the implanted ions being determined according to the substrate 1.

S2, a plurality of selection transistors 6 are formed on the common source 2.

In one embodiment, step S2 includes: S21-S28.

As shown in fig. 4b, in S21, an isolation layer 3 is first deposited on the surface of the common source 2.

Preferably, the isolating layer deposited in step S21 is SiO₂Or dielectric constant ratio SiO₂And a smaller insulating material, wherein the deposition method is any one of Chemical Vapor Deposition (CVD), sputtering, and Atomic Layer Deposition (ALD).

S22: a second via is formed through the isolation layer 3 of the select transistor 6.

Preferably, the second through hole is formed by using photolithography and dry etching processes.

S23: and depositing a selective gate dielectric layer 7 on the inner wall of the second through hole, and removing the selective gate dielectric layer 7 at the bottom of the second through hole to enable the second through hole to reach the upper surface of the common source electrode 2.

Preferably, the deposited selection gate dielectric layer 7 is silicon oxide (SiO)₂) Silicon nitride (Si)₃N₄) Silicon oxynitride(SiON) and aluminum oxide (Al)₂O₃)、HfO₂、ZrO₂Titanium oxide (TiO)₂) Lanthanum oxide (La)₂O₃) Hafnium silicon oxynitride (HfSiON), germanium oxide (GeO)₂) And the like, the deposition method being a chemical vapor deposition method (CVD) or an atomic layer deposition method (ALD).

S24: a selection channel layer 8 is deposited in the second via to fill the second via.

Preferably, the selection channel layer 8 filled in step S24 is polysilicon (Si), poly-germanium (Ge), poly-silicon-germanium (SiGe), or doped polysilicon (Si), doped poly-germanium (Ge), doped poly-silicon-germanium (SiGe), and the doping element is one or more of boron (B), phosphorus (P), and arsenic (As); the deposition method is a chemical vapor deposition method (CVD) or an atomic layer deposition method (ALD).

S25: a gate electrode layer 4 is deposited on the surface of the spacer 3 of the select transistor.

Preferably, the gate electrode layer 4 deposited in step S25 is any one of heavily doped polysilicon, a nitride metal electrode and tungsten (W), and the deposition method is any one of Chemical Vapor Deposition (CVD), sputtering (sputtering), Atomic Layer Deposition (ALD) and Metal Organic Chemical Vapor Deposition (MOCVD);

s26: and removing the upper surface of the second through hole in the gate electrode layer 4, which is positioned in the isolation layer 3, so as to prolong the second through hole. Preferably, the gate electrode layer 4 on the surface of the second via hole is removed by photolithography and dry etching.

S27: and depositing a selection gate dielectric layer 7 on the inner wall of the extended second through hole, and removing the selection gate dielectric material 7 at the bottom in the second through hole.

The deposited selection gate dielectric layer 7 is silicon oxide (SiO)₂) Silicon nitride (Si)₃N₄) Silicon oxynitride (SiON), aluminum oxide (Al)₂O₃)、HfO₂、ZrO₂Titanium oxide (TiO)₂) Lanthanum oxide (La)₂O₃) Hafnium silicon oxynitride (HfSiON), germanium oxide (GeO)₂) Etc. by one or more of the following deposition methodsChemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD).

S28: a selection channel layer 8 is deposited in the elongated second via to fill the second via.

Preferably, the selection channel layer 8 filled in step S28 is polysilicon (Si), poly-germanium (Ge), poly-silicon-germanium (SiGe), or doped polysilicon (Si), doped poly-germanium (Ge), doped poly-silicon-germanium (SiGe), and the doping element is one or more of boron (B), phosphorus (P), and arsenic (As); the deposition method is a chemical vapor deposition method (CVD) or an atomic layer deposition method (ALD).

S3, depositing an isolation layer 3 and a predetermined number of gate electrode layers 4 on the surface of the selection transistor 6 in an overlapping manner to form a stack.

As shown in fig. 4c, in the embodiment shown in fig. 4c, 6 gate electrode layers 4 are stacked, i.e. each memory cell string 5 of the memory to be prepared comprises 6 memory cells. The present invention takes 6 memory cells as an example, but not limited thereto.

S4, forming a first via 14 of a predetermined size above the plurality of selection transistors 6, wherein the first via 14 penetrates through the stacked layers.

As shown in fig. 4d, the first via 14 is located directly above the second via of the select transistor.

And S5, sequentially depositing a first dielectric layer 9, a ferroelectric thin film layer 10 and a second dielectric layer 11 on the inner wall of the first through hole 14 in the direction close to the axis.

Referring to fig. 4e, the ferroelectric thin film layer 10 deposited in step S5 is hafnium oxide (HfO)₂) Doped HfO₂Zirconium oxide (ZrO)₂) Or doped ZrO₂One of (1); wherein the doped HfO₂The element doped in the silicon-doped lanthanum-doped silicon (La), one or more of silicon (Si), aluminum (Al), zirconium (Zr), lanthanum (La), cerium (Ce), strontium (Sr), lutetium (Lu), gadolinium (Gd), scandium (Sc), neodymium (Nd), germanium (Ge), nitrogen (N) and the like; the deposition method is Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD).

The first dielectric layer 9 deposited in step S5 is silicon oxide (SiO)₂) Silicon nitride (Si)₃N₄) Silicon oxynitride (SiON), aluminum oxide (Al)₂O₃) Hafnium oxide (HfO)₂) Zirconium oxide (ZrO)₂) Titanium oxide (TiO)₂) Lanthanum oxide (La)₂O₃) Hafnium silicon oxynitride (HfSiON), germanium oxide (GeO)₂) And the like, the deposition method being a chemical vapor deposition method (CVD) or an atomic layer deposition method (ALD).

The second dielectric layer 11 deposited in step S5 is silicon oxide (SiO)₂) Silicon nitride (Si)₃N₄) Silicon oxynitride (SiON), aluminum oxide (Al)₂O₃) Hafnium oxide (HfO)₂) Zirconium oxide (ZrO)₂) Titanium oxide (TiO)₂) Lanthanum oxide (La)₂O₃) Hafnium silicon oxynitride (HfSiON), germanium oxide (GeO)₂) And the like, the deposition method being a chemical vapor deposition method (CVD) or an atomic layer deposition method (ALD).

S6, removing the second dielectric layer 11, the ferroelectric thin film layer 10 and the first dielectric layer 9 deposited at the bottom of the first via 14 in sequence by etching, so that the first via 14 penetrates through to the top of the selection transistor 6.

And S7, depositing the channel layer 12 with a preset thickness on the inner wall of the second medium layer 11.

Referring to fig. 4f, the channel layer 12 deposited in step S7 is polysilicon (Si), poly-germanium (Ge), poly-silicon-germanium (SiGe), or doped polysilicon (Si), doped poly-germanium (Ge), doped poly-silicon-germanium (SiGe), the doping element is one or more of boron (B), phosphorus (P), and arsenic (As), and the deposition method is Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD);

s8, a filling layer 13 is deposited on the inner wall of the channel layer 12 to fill the first via hole 14.

The filling layer 13 deposited in step S8 includes, but is not limited to, silicon oxide (SiO)₂) Silicon nitride (Si)₃N₄) Silicon oxynitride (SiON) deposited by Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD).

The preparation method of the three-dimensional ferroelectric field effect transistor memory provided by the embodiment of the invention is simple and easy to use, and the prepared memory has excellent performance and strong reliability.

It is to be understood that the above-described embodiments of the present invention are merely illustrative of or explaining the principles of the invention and are not to be construed as limiting the invention. Therefore, any modification, equivalent replacement, improvement and the like made without departing from the spirit and scope of the present invention should be included in the protection scope of the present invention. Further, it is intended that the appended claims cover all such variations and modifications as fall within the scope and boundaries of the appended claims or the equivalents of such scope and boundaries.