阅读说明：本技术 一种电路长期时序可靠性分析方法及系统 (Method and system for analyzing long-term timing sequence reliability of circuit ) 是由 吴玉平 陈岚 于 2020-06-23 设计创作，主要内容包括：本公开提供了一种电路长期时序可靠性分析方法及系统,方法包括：S1,建立电路单元的特征化时序数据与有效受压工作时间的对应关系；S2,建立有效受压工作时间与上层电路工作时间之间的对应关系；S3,建立以上层电路工作时间为变量的电路时序可靠性关系式；S4,根据电路时序可靠性关系式获取上层电路工作时间的最大值。在对电路进行长期时序可靠性分析过程中,考虑了电路中各电路单元的老化状态,使得电路单元特征化数据更加精确丰富,更加精准的表征老化过程中电路单元的特征,使得电路长期时序可靠性分析更加准确。(The invention provides a method and a system for analyzing long-term time sequence reliability of a circuit, wherein the method comprises the following steps: s1, establishing the corresponding relation between the characteristic time sequence data of the circuit unit and the effective pressed working time; s2, establishing a corresponding relation between the effective pressed working time and the working time of the upper circuit; s3, establishing a circuit time sequence reliability relational expression with the upper layer circuit working time as a variable; and S4, acquiring the maximum value of the working time of the upper layer circuit according to the circuit time sequence reliability relational expression. In the process of analyzing the long-term time sequence reliability of the circuit, the aging state of each circuit unit in the circuit is considered, so that the characteristic data of the circuit units is more accurate and abundant, the characteristics of the circuit units in the aging process are more accurately represented, and the long-term time sequence reliability of the circuit is more accurate.)

1. A method for analyzing long-term timing reliability of a circuit comprises the following steps:

s1, establishing the corresponding relation between the characteristic time sequence data of the circuit unit and the effective pressed working time;

s2, establishing the corresponding relation between the effective pressed working time and the working time of the upper circuit;

s3, establishing a circuit time sequence reliability relational expression taking the working time of the upper layer circuit as a variable;

and S4, acquiring the maximum value of the working time of the upper layer circuit according to the circuit time sequence reliability relational expression.

2. The circuit long term timing reliability analysis method of claim 1, further comprising:

s5, comparing the maximum value of the working time of the upper circuit with the working time required by design, if the maximum value of the working time of the upper circuit is greater than or equal to the working time required by design, the detected circuit path meets the long-term timing sequence reliability requirement of the circuit; otherwise, the detected circuit path does not meet the long-term timing reliability requirements of the circuit.

3. The method for analyzing long-term timing reliability of a circuit according to claim 1, wherein the step S2 of establishing a corresponding relationship between the effective pressed operation time and the operation time of the upper layer circuit comprises:

s21, carrying out logic simulation on the upper layer circuit to obtain a simulation result;

s22, obtaining the effective pressed working time of each device in the upper circuit within the preset time according to the simulation result;

and S23, obtaining the working time of the upper layer circuit and the effective pressed working time of each device.

4. The method of claim 1, further comprising thermally analyzing the circuit to determine a temperature at each location of the circuit.

5. The method of circuit long term timing reliability analysis of claim 4, the thermally analyzing the circuit comprising:

performing logic simulation on the circuit to obtain a simulation result;

obtaining a heat source of the circuit according to the simulation result;

setting a heat source at a corresponding position in the circuit according to the heat source position obtained by logic simulation;

and carrying out thermal simulation analysis on the circuit to obtain the temperature of each circuit unit and device position in the circuit.

6. The method of claim 4 or 5, wherein the characterization timing data of the circuit cells is a function of temperature.

7. The method of claim 1, further comprising analyzing voltage drops caused by parasitic resistances on power and ground lines of the circuit to determine actual operating voltages of the unit circuits in the circuit.

8. The method of claim 7, wherein the characterization timing data for the circuit cell is a function of actual operating voltage.

9. The method for analyzing long-term timing reliability of a circuit according to any one of claims 1 to 8, further comprising: the size of the device which is aged faster in the circuit unit is optimized to prolong the maximum value of the working time of the upper layer circuit.

10. A circuit long term timing reliability analysis system, comprising:

the first establishing module is used for establishing the corresponding relation between the characteristic time sequence data of the circuit unit and the effective pressed working time;

the second establishing module is used for establishing the corresponding relation between the effective pressed working time and the working time of the upper layer circuit;

the third establishing module is used for establishing a circuit time sequence reliability relational expression taking the working time of the upper layer circuit as a variable;

and the acquisition module is used for acquiring the maximum value of the working time of the upper layer circuit according to the circuit time sequence reliability relational expression.

11. The circuit long term timing reliability analysis system of claim 10, further comprising:

the comparison module is used for comparing the maximum value of the working time of the upper layer circuit with the working time required by design, and if the maximum value of the working time of the upper layer circuit is greater than or equal to the working time required by design, the detected circuit path meets the long-term timing sequence reliability requirement of the circuit; otherwise, the detected circuit path does not meet the long-term timing reliability requirements of the circuit.

12. The circuit long term timing reliability analysis system of claim 10, the second building block comprising:

the simulation module is used for carrying out logic simulation on the upper layer circuit to obtain a simulation result;

the first obtaining module is used for obtaining the effective pressed working time of each device in the upper layer circuit within the preset time according to the simulation result;

and the second obtaining module is used for obtaining the working time of the upper layer circuit and the effective pressed working time of each device.

Technical Field

The present disclosure relates to the field of circuit long-term timing reliability analysis technologies, and in particular, to a method and a system for analyzing circuit long-term timing reliability.

Background

Circuit timing analysis is an important step in the design flow of integrated circuits, and the circuit unit characterization data on which the current circuit timing analysis depends is fixed data and is irrelevant to the aging state of devices. For a circuit working for a long time, threshold voltages and carrier mobilities of related devices of a semiconductor device are obviously shifted due to accumulation of hot carrier injection (HCl) and gate Bias Temperature Instability (BTI) effects, so that the performance of the device is degraded, the performance of a circuit unit is degraded, and fixed data for characterizing the circuit unit in principle naturally cannot accurately characterize the characteristics of the circuit unit in an aging process. Therefore, current circuit cell characterization fixed data does not support accurate circuit long-term timing reliability analysis. The method is characterized in that different aging states of a circuit unit are characterized, time sequence analysis of the different aging states is carried out, time cost is high, when the method is used for carrying out long-term time sequence reliability analysis on an integrated circuit design of a system on a chip, the path number is large in scale, and long time is spent in the analysis.

Disclosure of Invention

Technical problem to be solved

The invention provides a method and a system for analyzing long-term time sequence reliability of a circuit, which at least solve the problem of analyzing the long-term time sequence reliability in the design process of an integrated circuit.

(II) technical scheme

The present disclosure provides a method for analyzing long-term timing reliability of a circuit, including: s1, establishing the corresponding relation between the characteristic time sequence data of the circuit unit and the effective pressed working time; s2, establishing a corresponding relation between the effective pressed working time and the working time of the upper circuit; s3, establishing a circuit time sequence reliability relational expression with the upper layer circuit working time as a variable; and S4, acquiring the maximum value of the working time of the upper layer circuit according to the circuit time sequence reliability relational expression.

Optionally, the method for analyzing long-term timing reliability of a circuit further includes:

s5, comparing the maximum value of the working time of the upper circuit with the working time required by the design, if the maximum value of the working time of the upper circuit is greater than or equal to the working time required by the design, the detected circuit path meets the long-term timing sequence reliability requirement of the circuit; otherwise, the detected circuit path does not meet the long-term timing reliability requirements of the circuit.

Optionally, the step S2 of establishing a corresponding relationship between the effective pressed operating time and the operating time of the upper layer circuit includes: s21, carrying out logic simulation on the upper layer circuit to obtain a simulation result; s22, obtaining the effective pressed working time of each device in the upper circuit within the preset time according to the simulation result; and S23, obtaining the working time of the upper layer circuit and the effective pressed working time of each device.

Optionally, the method for analyzing long-term timing reliability of a circuit further includes performing thermal analysis on the circuit to determine the temperature of each position of the circuit.

Optionally, the performing thermal analysis on the circuit includes: performing logic simulation on the circuit to obtain a simulation result; obtaining a heat source of the circuit according to a simulation result; setting a heat source at a corresponding position in the circuit according to the heat source position obtained by logic simulation; and carrying out thermal simulation analysis on the circuit to obtain the temperature of each circuit unit and device position in the circuit.

Optionally, the characterized timing data of the circuit cell is a function of temperature.

Optionally, the method for analyzing long-term timing reliability of the circuit further includes analyzing voltage drops caused by parasitic resistances on a power line and a ground line of the circuit to determine actual operating voltages of the unit circuits in the circuit.

Optionally, the characterized timing data of the circuit cell is a function of the actual operating voltage.

Optionally, the method for analyzing long-term timing reliability of a circuit further includes: the size of the device which is aged faster in the circuit unit is optimized to prolong the maximum value of the working time of the upper layer circuit.

In addition, the present disclosure also provides a circuit long-term timing reliability analysis system, including: the first establishing module is used for establishing the corresponding relation between the characteristic time sequence data of the circuit unit and the effective pressed working time; the second establishing module is used for establishing the corresponding relation between the effective pressed working time and the working time of the upper layer circuit; the third establishing module is used for establishing a circuit time sequence reliability relational expression taking the working time of the upper-layer circuit as a variable; and the acquisition module is used for acquiring the maximum value of the working time of the upper-layer circuit according to the circuit time sequence reliability relational expression.

Optionally, the system for analyzing long-term timing reliability of a circuit further includes: the comparison module is used for comparing the maximum value of the working time of the upper circuit with the working time required by design, and if the maximum value of the working time of the upper circuit is greater than or equal to the working time required by design, the detected circuit path meets the long-term time sequence reliability requirement of the circuit; otherwise, the detected circuit path does not meet the long-term timing reliability requirements of the circuit.

Optionally, the second establishing module includes: the simulation module is used for carrying out logic simulation on the upper layer circuit to obtain a simulation result; the first obtaining module is used for obtaining the effective pressed working time of each device in the upper layer circuit within the preset time according to the simulation result; and the second obtaining module is used for obtaining the working time of the upper layer circuit and the effective pressed working time of each device.

(III) advantageous effects

The invention provides a method and a system for analyzing long-term time sequence reliability of a circuit, wherein in the process of analyzing the long-term time sequence reliability of the circuit, the aging state of each circuit unit in the circuit is considered, so that the characteristic data of the circuit units is more accurate and abundant, the characteristics of the circuit units in the aging process are more accurately represented, and the analysis of the long-term time sequence reliability of the circuit is more accurate.

Drawings

FIG. 1 schematically illustrates a step diagram of a method of long term timing reliability analysis of a circuit according to an embodiment of the disclosure;

FIG. 2 schematically illustrates a schematic diagram of a data setup process in a circuit according to an embodiment of the disclosure;

FIG. 3 schematically illustrates a schematic diagram of a data retention process in a circuit according to an embodiment of the disclosure;

FIG. 4 schematically illustrates a block diagram of a circuit long term timing reliability analysis system according to an embodiment of the disclosure.

Detailed Description

The present disclosure provides a method for analyzing long-term timing reliability of a circuit, including: s1, establishing the corresponding relation between the characteristic time sequence data of the circuit unit and the effective pressed working time; s2, establishing a corresponding relation between the effective pressed working time and the working time of the upper circuit; s3, establishing a circuit time sequence reliability relational expression with the upper layer circuit working time as a variable; and S5, acquiring the maximum value of the working time of the upper layer circuit according to the circuit time sequence reliability relational expression.

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings.

The existing long-term time sequence reliability detection method needs to respectively detect whether the path time sequence meets the requirements under all possible aging states, firstly, the analysis time is long, and secondly, the method is not feasible for a large-scale circuit.

The circuit in the embodiment of the present disclosure includes REG1, REG2, and Comb Logic, where REG1 and REG2 are a source register and a target register, respectively, and Comb Logic is a combinational Logic circuit for data communication between REG1 and REG2, and generally consists of several basic circuit units.

In the circuit design process, data establishment time and data storage time need to be met, so that a circuit timing reliability relational expression needs to be met in the data establishment process, and the circuit timing reliability relational expression also needs to be met in the data storage process.

And S1, establishing the corresponding relation between the characteristic time sequence data of the circuit unit and the effective pressed working time. The characteristic time sequence data of the circuit unit in the embodiment of the present disclosure is a function expression with effective pressed working time as a variable, such as Tcell, i, TCO, TSU, TH, etc. in the embodiment of the present disclosure, which may be a one-time term function, a multi-time term function, or a polygonal line function, etc. The characteristic time sequence data of the circuit unit can also be a function expression with temperature as a variable, such as a first-order term function, a multiple-order term function or a broken line function, and when an inequality with a circuit path meeting a long-term time sequence reliability condition is established, the circuit unit characteristic function with temperature as the variable is substituted into a path time sequence inequality.

S2, establishing a corresponding relation between the effective pressed working time and the working time of the upper circuit; s3, establishing a circuit time sequence reliability relational expression with the upper layer circuit working time as a variable;

specifically, in the data establishment process, as shown in fig. 2:

TCLK1 is the delay time from the rising edge of the clock signal CLK to the clock input CLK (reg1.CLK) of register REG 1;

TCO is the delay time from the rising edge of the clock input end CLK (REG1.CLK) signal of the register REG1 to the transmission of data to the output end Q (REG1.Q) of the register REG1, and comprises the internal logic delay of the register and the data output buffering delay;

tdata is the delay time for data to be transmitted from output terminal Q (reg1.q) of register REG1 to data input terminal D (reg2.d) of register REG 2;

TCK2 is the delay time from the rising edge of the clock signal CLK to the clock input CLK (reg2.CLK) of register REG 2;

TSU is the minimum time that the data signal at data signal input D (reg2.D) of register REG2 must remain stable before the rising edge of the clock signal at clock signal input CLK (reg2.CLK) of register REG 2;

tsetup _ slack is a margin of setup time, which is a distance from a time point when data arrives at a data input end D (reg2.D) of the register REG2 to a time point corresponding to the minimum setup time Tsetup, and indicates that the timing requirement is satisfied when the value is positive (the data arrival time point is on the left side of the time point corresponding to Tsetup), and indicates that the timing requirement is not satisfied when the value is negative (the data arrival time point is on the right side of the time point corresponding to Tsetup);

TCLK2-TCLK1 is defined as the clock deviation TSKEW between reg2.clk and reg1. clk;

TLaunch _ Edge is a point in time when data is transmitted from the source register REG1 on the Edge of the clock signal;

TLatch _ Edge is a time point when the target register REG2 latches data on the clock signal Edge;

TLatch _ Edge-TLaunch _ Edge ═ T is the clock signal period.

Tsetup_slack＝T+TSKEW-TSU-TCO-Tdata

Therefore, the following relationship of circuit timing reliability must be satisfied when the timing requirement is satisfied in the data establishing process:

T+TSKEW-TSU-TCO-Tdata≥0 (1)

during data retention, as shown in fig. 3:

TH is the minimum time that data must remain stable after the arrival of a valid edge of the clock;

thold — — — -ck is a retention time margin, which is a distance from a data retention minimum time point to a data change time point of the data input terminal D (reg2.D) of the register REG2, Thold — — -ck ═ TSKEW + TCO + Tdata-TH. A positive value (TH on the left side of the data change time point) indicates that the timing requirement is satisfied, and a negative value (TH on the right side of the data change time point) indicates that the timing requirement is not satisfied. Therefore, when the timing requirement is satisfied, the circuit timing reliability relation must be satisfied:

TSKEW+TCO+Tdata-TH≥0 (2)

tdata is the sum of the delays of the elementary cell circuits experienced by the data signal on the path from reg1.q to reg2. d:

Tdata＝∑Tcell，i i＝1，2，…，N

tcell, i is the characteristic delay data of the basic unit i at the moment when the effective working time under pressure is t, and a function expression with the effective working time under pressure as a variable can be expressed as follows:

Tcell，i＝Tcell，i，0*Fcell，i(t)

wherein Tcell, i, 0 is the characterized delay data when the effective pressed working time is 0, Fcell, i (t) is the degradation degree of the performance index of the circuit unit when the effective pressed working time is t, and Fcell, i (0) is 1.

The characteristic delay data TCO expression of the register along with the change of the working voltage is as follows:

TCO＝TCO，0*Ftco(t)

the TCO, 0 is TCO-characterized delay data with effective pressed working time of 0, Ftco (t) is the decline degree of TCO performance index of the register with effective pressed working time of t, and Ftco (0) is 1.

The TSU expression of the characteristic data of the register along with the change of the working voltage is as follows:

TSU＝TSU，0*Ftsu(t)

the TSU, 0 is delay data characterized by the TSU whose effective pressed operating time is 0, Ftsu (t) is a degradation degree of the TSU performance index of the register whose effective pressed operating time is t, and Ftsu (0) is 1.

The characteristic data TH expression of the register along with the change of the working voltage is as follows:

TH＝TH，0*Fth(t)

where, TH, 0 is the delay data characterized by TH when the effective pressed operating time is 0, Fth (t) is the decline degree of the performance index of the register TH when the effective pressed operating time is t, and Fth (0) is 1.

And S4, acquiring the maximum value of the working time of the upper layer circuit according to the circuit time sequence reliability relational expression.

Specifically, a characterization data expression with the effective stressed operating time t as a variable is substituted into a circuit timing reliability relational expression (1) to obtain:

T+TSKEW-TSU，0*Ftsu(t)-TCO，0*Ftco(t)

-∑[Tcell，i，0*Fcell，i(t)]≥0

and solving the maximum value by using a numerical solution to obtain the maximum value t1max of the effective pressed working time meeting the inequality condition, which corresponds to the extreme aging state of the path capable of working normally.

t≤t1max (3)

Substituting a characterization data expression with the effective stressed operating time t as a variable into a circuit timing reliability relational expression (2):

TSKEW+TCO，0*Ftco(t)

+∑[Tcell，i，0*Ftcell，i(t)]-TH，0*Fth(t)≥0

solving the maximum value by using a numerical solution to obtain the maximum value t2max of the effective pressed working time meeting the inequality condition, wherein the relation formula of the extreme aging state of the corresponding path capable of working normally is as follows:

t≤t2max (4)

determining the maximum value of the working time of the upper layer circuit with the path capable of working normally according to the inequality (3) and the inequality (4):

tmax＝min(t1max，t2max)

comparing the maximum working time of the upper circuit with the required working time tspecmax of the design, wherein the maximum working time of the upper circuit is greater than or equal to the required working time of the design, and the detected circuit path meets the long-term timing sequence reliability requirement of the circuit; otherwise, the detected circuit path does not meet the long-term timing reliability requirements of the circuit.

In step S2, the corresponding relationship between the effective pressed operating time and the operating time of the upper layer circuit is established, and the following steps may be adopted:

s21, carrying out logic simulation on the upper layer circuit to obtain a simulation result;

s22, obtaining the effective pressed working time of each device in the upper circuit within the preset time according to the simulation result; the logic simulation analysis can be carried out on the circuit, and the effective compression time of the devices in each unit on the path in a certain preset time is analyzed based on the logic simulation result.

And S23, obtaining the working time of the upper layer circuit and the effective pressed working time of each device. And establishing a functional relation between the working time of the upper layer circuit and the effective pressed working time of each device according to the logic simulation time and the effective pressed time of the devices in each unit on the path.

The method for analyzing the long-term timing sequence reliability of the circuit in the embodiment of the disclosure further comprises the following steps of carrying out thermal analysis on the circuit to determine the temperature of each position of the circuit, specifically:

step 1: performing logic simulation on the circuit to obtain a simulation result;

step 2: obtaining a heat source of the circuit according to the simulation result;

and step 3: setting a heat source at a corresponding position in the circuit according to the heat source position obtained by logic simulation;

and 4, step 4: and carrying out thermal simulation analysis on the circuit to obtain the temperature of each circuit unit and device position in the circuit.

When the circuit time sequence reliability relational expression is established, the temperature is taken as the characteristic time sequence data of the variable and is substituted into the circuit time sequence reliability relational expression, so that the time sequence analysis is more accurate due to the fact that the temperature of a specific position is considered.

The method for analyzing the long-term timing sequence reliability of the circuit further comprises the step of analyzing voltage drop caused by parasitic resistance on a power line and a ground line of the circuit so as to determine the actual working voltage of each unit circuit in the circuit.

When the circuit time sequence reliability relational expression is established, the characteristic time sequence data taking the actual working voltage of the circuit unit as a variable is substituted into the circuit time sequence reliability relational expression, so that the time sequence analysis is more accurate due to the fact that the actual working voltage of the circuit unit at a specific position is considered.

Further, the size of the device which is aged faster in the circuit unit can be optimized to prolong the maximum working time of the upper circuit.

In another aspect, the present disclosure provides a circuit long-term timing reliability analysis system, as shown in fig. 4, including:

the first establishing module 410 can, for example, execute step S1 shown in fig. 1 for establishing a corresponding relationship between the characterization timing data of the circuit unit and the effective pressed operating time;

the second establishing module 420 may, for example, execute step S2 shown in fig. 1 for establishing a corresponding relationship between the effective pressed operating time and the operating time of the upper layer circuit;

the third establishing module 430, for example, can know to execute step S3 shown in fig. 1 for establishing a circuit timing reliability relation with the upper layer circuit operating time as a variable;

the obtaining module 440, for example, can know to execute step S4 shown in fig. 1, for obtaining the maximum value of the upper layer circuit operating time according to the circuit timing reliability relation.

The circuit long-term timing reliability analysis system further comprises: the comparison module is used for comparing the maximum value of the working time of the upper circuit with the working time required by design, and if the maximum value of the working time of the upper circuit is greater than or equal to the working time required by design, the detected circuit path meets the long-term time sequence reliability requirement of the circuit; otherwise, the detected circuit path does not meet the long-term timing reliability requirements of the circuit.

The second establishing module includes:

the simulation module is used for carrying out logic simulation on the upper layer circuit to obtain a simulation result;

the first obtaining module is used for obtaining the effective pressed working time of each device in the upper layer circuit within the preset time according to the simulation result;

and the second obtaining module is used for obtaining the working time of the upper layer circuit and the effective pressed working time of each device.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.