Semiconductor chip
阅读说明:本技术 半导体芯片 (Semiconductor chip ) 是由 崔善明 朴珉秀 于 2019-10-18 设计创作,主要内容包括:一种半导体芯片包括第一半导体器件和第二半导体器件。第一半导体器件包括错误检测电路。第二半导体器件与第一半导体器件层叠并且经由第一穿通电极和第二穿通电极电连接到第一半导体器件。第一半导体器件和第二半导体器件被配置为根据操作模式而经由第二穿通电极来接收或输出第一数据和第二数据,并且被配置为使用错误检测电路来检测第一数据的错误和第二数据的错误。(A semiconductor chip includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes an error detection circuit. The second semiconductor device is stacked with the first semiconductor device and electrically connected to the first semiconductor device via the first through electrode and the second through electrode. The first and second semiconductor devices are configured to receive or output first and second data via the second through electrode according to an operation mode, and configured to detect an error of the first data and an error of the second data using an error detection circuit.)
1. A semiconductor chip, comprising:
a first semiconductor device including an error detection circuit; and
a second semiconductor device stacked with the first semiconductor device and electrically connected with the first semiconductor device via a first through electrode and a second through electrode,
wherein the first and second semiconductor devices are configured to receive or output first and second data via the second through electrode according to an operation mode, and configured to detect an error of the first data and an error of the second data using an error detection circuit.
2. The semiconductor chip of claim 1, wherein:
the operating mode comprises one of a first write operation, a first read operation, a second write operation, and a second read operation;
performing the first write operation to store the first data output by the first semiconductor device into the second semiconductor device;
performing the first read operation to output the second data output by the second semiconductor device to an external apparatus;
performing the second write operation to store external data provided by the external device into the first semiconductor device; and
performing the second read operation to output the internal data stored in the first semiconductor device to the external device.
3. The semiconductor chip of claim 1, wherein during a first write operation:
the first semiconductor device is configured to generate first data from first external data provided by an external apparatus, and to detect an error of the first data using the error detection circuit; and
the second semiconductor device is configured to store first internal data generated from the first data.
4. The semiconductor chip of claim 1, wherein during a first read operation:
the second semiconductor device is configured to output second internal data stored in the second semiconductor device as the second data via the second through electrode; and
the first semiconductor device is configured to detect an error of the second data using the error detection circuit, and to output the second data as second external data.
5. The semiconductor chip of claim 1, wherein during a second write operation, the first semiconductor device is configured to:
generating the first data from third external data provided by an external device;
detecting an error of the first data using the error detection circuit; and
third internal data generated from the third external data is stored.
6. The semiconductor chip of claim 1, wherein during a second read operation, the first semiconductor device is configured to:
generating the first data from fourth internal data stored in the first semiconductor device;
detecting an error of the first data using the error detection circuit; and
outputting fourth external data generated from the fourth internal data to an external device.
7. The semiconductor chip of claim 1, wherein the first semiconductor device further comprises:
a control circuit configured to:
generating an enable signal, first and second write control signals, first and second read control signals, and a select signal, one of the signals being selectively enabled according to the operation mode; and
outputting the enable signal, the first and second write control signals, the first and second read control signals, and the select signal to the second semiconductor device via the first through electrode;
a first input/output (I/O) circuit configured to:
electrically connecting the second pass electrode to a first pass I/O line and a second pass I/O line; and
receiving or outputting the first data and the second data through the second through electrode; and a first path control circuit configured to:
generating the first data from first external data provided from an external device to output the first data to the first transfer I/O line based on the enable signal, the first and second write control signals, the first and second read control signals, and the select signal during a first write operation;
generating second external data from the second data loaded on the first transmission I/O line to output the second external data to the external device based on the enable signal, the first and second write control signals, the first and second read control signals, and the select signal during a first read operation;
generating the first data from third external data provided by the external device to output the first data to the first transfer I/O line and generate first internal data from the third external data, based on the enable signal, the first and second write control signals, the first and second read control signals, and the select signal, during a second write operation;
generating the first data from second internal data to output the first data to the first transfer I/O line and fourth external data from the second internal data to output the fourth external data to the external device based on the enable signal, the first and second write control signals, the first and second read control signals, and the select signal during a second read operation,
wherein the error detection circuit is configured to detect an error of the first data and an error of the second data loaded on the first transmission I/O line, generate a detection signal, and output the detection signal to the external device.
8. The semiconductor chip of claim 7, wherein the control circuit comprises:
a register configured to generate a mode enable signal, a first write mode signal, a second write mode signal, a third write mode signal, a first read mode signal, a second read mode signal, and a third read mode signal, and a reset signal, the mode enable signal including information on the operation mode; and
a control signal generation circuit configured to generate the enable signal, the first and second write control signals, the first and second read control signals, and the selection signal, one of which is selectively enabled according to a logic level combination of the mode enable signal, the first write mode signal, the second write mode signal, the third write mode signal, the first read mode signal, the second and third read mode signals, and the reset signal.
9. The semiconductor chip of claim 8, wherein the control signal generation circuit comprises:
an enable signal generation circuit configured to delay the mode enable signal to generate the enable signal;
a transfer control signal generation circuit configured to generate a transfer control signal that is enabled when the first read mode signal is input to the transfer control signal generation circuit and disabled when the first write mode signal is input to the transfer control signal generation circuit;
a write control signal generation circuit configured to generate the first write control signal and the second write control signal, one of the first write control signal and the second write control signal being selectively enabled according to a logic level combination of the enable signal, the second write mode signal, and the third write mode signal when the transfer control signal is disabled; and
a read control signal generation circuit configured to generate the first read control signal or the second read control signal, the first read control signal or the second read control signal being selectively enabled according to a logic level combination of the mode enable signal, the second read mode signal, and the third read mode signal, and configured to generate the selection signal, the selection signal being enabled when the mode enable signal is disabled and the transfer control signal is enabled.
10. The semiconductor chip of claim 7, wherein the first path control circuit comprises:
a first write path control circuit configured to:
generating the first data from the first external data to output the first data to the first transfer I/O line or generating the first data from the third external data to output the first data to the first transfer I/O line according to the enable signal and the first and second write control signals; and
inversely buffering the third external data to generate the first internal data; and
a first read path control signal configured to: inverting and buffering the second data loaded on the first transmission I/O line according to the selection signal and the first and second read control signals to output the inverted and buffered data of the second data as the second external data or output the second internal data as the fourth external data.
11. The semiconductor chip of claim 1, wherein the second semiconductor device comprises:
a second I/O circuit configured to:
electrically connecting the second pass electrode to a third transmit I/O line and a fourth transmit I/O line; and
receiving or outputting the first data and the second data through the second through electrode; and
a second path control circuit configured to:
generating third internal data from the first data input through the third transfer I/O line during a first write operation; and
outputting fourth internal data as the second data through the third transfer I/O line during a first read operation according to an enable signal, first and second write control signals, first and second read control signals, and a select signal.
12. The semiconductor chip of claim 11, wherein the second path control circuit comprises:
a second write path control circuit configured to output the first data loaded on the third transfer I/O line as the third internal data according to the enable signal and the first and second write control signals; and
a second read path control signal configured to output the fourth internal data to the third transmission I/O line to generate the second data according to the selection signal and the first and second read control signals.
13. A semiconductor chip, comprising:
a first semiconductor device including a first error detection circuit; and
a second semiconductor device including a second error detection circuit, wherein the second semiconductor device is stacked with the first semiconductor device and electrically connected with the first semiconductor device via a first through electrode and a second through electrode;
wherein the first and second semiconductor devices are configured to receive or output first and second data via the second through electrode during a first write operation and a first read operation, and configured to detect an error of the first data and an error of the second data using the first and second error detection circuits.
14. The semiconductor chip of claim 13, wherein during the first write operation:
the first semiconductor device is configured to generate first data from first external data provided by an external apparatus, and to detect an error of the first data using the first error detection circuit; and
the second semiconductor device is configured to store first internal data generated from the first data, and is configured to detect an error of the first data using the second error detection circuit.
15. The semiconductor chip of claim 13, wherein during the first read operation:
the second semiconductor device is configured to output second internal data stored in the second semiconductor device as the second data via the second through electrode, and to detect an error of the second data using the second error detection circuit; and
the first semiconductor device is configured to detect an error of the second data using the first error detection circuit, and to output the second data as second external data.
16. The semiconductor chip of claim 13, wherein during a second write operation, the first semiconductor device is configured to:
generating the first data from third external data provided by an external device;
detecting an error of the first data using the first error detection circuit; and
third internal data generated from the third external data is stored.
17. The semiconductor chip of claim 13, wherein during a second read operation, the first semiconductor device is configured to:
generating the first data from fourth internal data stored in the first semiconductor device;
detecting an error of the first data using the first error detection circuit; and
outputting fourth external data generated from the fourth internal data to an external device.
18. The semiconductor chip of claim 13, wherein said first semiconductor device further comprises:
a control circuit configured to:
generating an enable signal, first and second write control signals, first and second read control signals, and a select signal, one of the signals being selectively enabled according to the first write operation, the first read operation, the second write operation, and the second read operation; and
outputting the enable signal, the first and second write control signals, the first and second read control signals, and the select signal to the second semiconductor device via the first through electrode;
a first input/output (I/O) circuit configured to:
electrically connecting the second pass electrode to a first pass I/O line and a second pass I/O line; and
receiving or outputting the first data and the second data through the second through electrode; and
a first path control circuit configured to:
generating the first data from first external data provided from an external device to output the first data to the first transfer I/O line based on the enable signal, the first and second write control signals, the first and second read control signals, and the select signal during the first write operation;
generating second external data from the second data loaded on the first transmission I/O line to output the second external data to the external device based on the enable signal, the first and second write control signals, the first and second read control signals, and the select signal during the first read operation;
generating the first data from third external data provided by the external device to output the first data to the first transfer I/O line and generate first internal data from the third external data, based on the enable signal, the first and second write control signals, the first and second read control signals, and the select signal, during the second write operation;
generating the first data from second internal data to output the first data to the first transfer I/O line and fourth external data from the second internal data to output the fourth external data to the external device based on the enable signal, the first and second write control signals, the first and second read control signals, and the select signal during the second read operation,
wherein the first error detection circuit is configured to detect an error of the first data and an error of the second data loaded on the first transmission I/O line to generate a first detection signal, and to output the first detection signal to the external device.
19. The semiconductor chip of claim 18, wherein the control circuit comprises:
a register configured to generate a mode enable signal, a first write mode signal, a second write mode signal, a third write mode signal, a first read mode signal, a second read mode signal, and a third read mode signal, and a reset signal, the mode enable signal including information on the first write operation, the first read operation, the second write operation, and the second read operation; and
a control signal generation circuit configured to generate the enable signal, the first and second write control signals, the first and second read control signals, and the selection signal, one of which is selectively enabled according to a logic level combination of the mode enable signal, the first write mode signal, the second write mode signal, the third write mode signal, the first read mode signal, the second and third read mode signals, and the reset signal.
20. The semiconductor chip of claim 19, wherein the control signal generation circuit comprises:
an enable signal generation circuit configured to delay the mode enable signal to generate the enable signal;
a transfer control signal generation circuit configured to generate a transfer control signal that is enabled when the first read mode signal is input to the transfer control signal generation circuit and disabled when the first write mode signal is input to the transfer control signal generation circuit;
a write control signal generation circuit configured to generate the first write control signal and the second write control signal, one of the first write control signal and the second write control signal being selectively enabled according to a logic level combination of the enable signal, the second write mode signal, and the third write mode signal when the transfer control signal is disabled; and
a read control signal generation circuit configured to generate the first read control signal or the second read control signal, the first read control signal or the second read control signal being selectively enabled according to a logic level combination of the mode enable signal, the second read mode signal, and the third read mode signal, and configured to generate the selection signal, the selection signal being enabled when the mode enable signal is disabled and the transfer control signal is enabled.
21. The semiconductor chip of claim 18, wherein the first path control circuit comprises:
a first write path control circuit configured to:
generating the first data from the first external data to output the first data to the first transfer I/O line or generating the first data from the third external data to output the first data to the first transfer I/O line according to the enable signal and the first and second write control signals; and
inversely buffering the third external data to generate the first internal data; and
a first read path control signal configured to: inverting and buffering the second data loaded on the first transmission I/O line according to the selection signal and the first and second read control signals to output the inverted and buffered data of the second data as the second external data or output the second internal data as the fourth external data.
22. The semiconductor chip of claim 13, wherein said second semiconductor device further comprises:
a second I/O circuit configured to:
electrically connecting the second pass electrode to a third transmit I/O line and a fourth transmit I/O line; and
receiving or outputting the first data and the second data through the second through electrode; and
a second path control circuit configured to:
outputting the first data to the third transmit I/O line during the first write operation; and
outputting the second data loaded on the third transfer I/O line through the second through electrode during the first read operation according to an enable signal, first and second write control signals, first and second read control signals, and a select signal input through the first through electrode,
wherein the second error detection circuit is configured to detect an error of the first data and an error of the second data loaded on the third transfer I/O line to generate a second detection signal, and to output the second detection signal to an external device.
23. The semiconductor chip of claim 22, wherein the second path control circuit comprises:
a second write path control circuit configured to output the first data loaded on the second transfer I/O line as third internal data according to the enable signal and the first and second write control signals; and
a second read path control signal configured to output fourth internal data to the third transmission I/O line to generate the second data according to the selection signal and the first and second read control signals.
Technical Field
Embodiments of the present disclosure relate to a semiconductor chip that detects an error of data received or output via a through electrode.
Background
Recently, various designs for receiving or outputting multi-bit data during each clock cycle have been used to increase the operating speed of semiconductor devices. If the data transfer speed of the semiconductor device becomes faster, the possibility of an error occurring when transferring data in the semiconductor device increases. This can cause reliability problems during data transmission.
An error code capable of detecting the occurrence of an error may be generated and transmitted together with data whenever the data is transmitted in the semiconductor device to improve the reliability of data transmission. The error codes may include cyclic redundancy check and Error Detection Codes (EDCs) capable of detecting errors and Error Correction Codes (ECCs) capable of correcting errors.
Recently, three-dimensional semiconductor chips have been developed to increase the integration density of memories. Each of the three-dimensional semiconductor chips may be implemented by vertically stacking a plurality of semiconductor devices to achieve maximum integration density over a limited area.
Each three-dimensional semiconductor chip may be implemented using a through-silicon via (TSV) technology that electrically connects all stacked semiconductor devices to each other using a TSV that vertically penetrates the semiconductor devices. Therefore, the three-dimensional semiconductor chip manufactured using the TSV can reduce a package area compared to the three-dimensional semiconductor chip manufactured using the bonding wire.
Disclosure of Invention
According to one embodiment, a semiconductor chip includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes an error detection circuit. The second semiconductor device is stacked with the first semiconductor device and electrically connected with the first semiconductor device via the first through electrode and the second through electrode. The first and second semiconductor devices are configured to receive or output first and second data via the second through electrode according to an operation mode, and configured to detect an error of the first data and an error of the second data using an error detection circuit.
According to another embodiment, a semiconductor chip includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first error detection circuit. The second semiconductor device includes a second error detection circuit. The second semiconductor device is stacked with the first semiconductor device and electrically connected with the first semiconductor device via the first through electrode and the second through electrode. The first and second semiconductor devices are configured to receive or output first and second data via the second through electrode during a first write operation and a first read operation, and configured to detect an error of the first data and an error of the second data using the first and second error detection circuits.
Drawings
Fig. 1 is a block diagram illustrating a configuration of a semiconductor chip according to one embodiment of the present disclosure.
Fig. 2 is a block diagram showing a configuration of a control circuit included in the semiconductor chip of fig. 1.
Fig. 3 is a circuit diagram showing a configuration of a control signal generation circuit included in the control circuit of fig. 2.
Fig. 4 is a graph showing logic levels of signals generated by a register and a control signal generation circuit included in the control circuit of fig. 2 according to an operation mode of the semiconductor chip of fig. 1.
Fig. 5 is a circuit diagram showing a configuration of a first path control circuit included in the semiconductor chip of fig. 1.
Fig. 6 is a circuit diagram showing a configuration of a second path control circuit included in the semiconductor chip of fig. 1.
Fig. 7 illustrates a first write operation path of a semiconductor chip according to one embodiment of the present disclosure.
Fig. 8 illustrates a first read operation path of a semiconductor chip according to one embodiment of the present disclosure.
Fig. 9 illustrates a second write operation path of a semiconductor chip according to one embodiment of the present disclosure.
Fig. 10 illustrates a second read operation path of a semiconductor chip according to one embodiment of the present disclosure.
Detailed Description
A limited number of possible embodiments of the present disclosure are described herein with reference to the figures. These described embodiments are for illustrative purposes and are not intended to limit the scope of the present disclosure.
As shown in fig. 1, a
The
The
The operation modes may include a first write operation, a first read operation, a second write operation, and a second read operation. The first write operation may be an operation performed to store the first data D1 output from the
The first I/
More specifically, the first I/
Based on the enable signal EN, the first write control signal WT _ CON <1>, the second write control signal WT _ CON <2>, the first read control signal RD _ CON <1>, the second read control signal RD _ CON <2>, and the select signal SEL, the first
During the second write operation, the
The first
The
The second I/
More specifically, the second I/
The second
During the first write operation, the
The second
Meanwhile, although the first and
Referring to fig. 2, the
The
The control
Referring to fig. 3, the control
The enable
The transmission control
The write control
The read control
More specifically, the logic levels of signals generated by the
Referring to fig. 4, during the first write operation, the
During the first write operation, the control
During the first read operation, the
During the first read operation, the control
During the second write operation, the
During the second write operation, the control
During the second read operation, the
During the second read operation, the control
Referring to fig. 5, the first
The first write path control circuit 131 may be implemented using a first buffer IV51, a first transfer gate T51, and a second transfer gate T52.
The first buffer IV51 may be turned on when the first write control signal WT _ CON <1> has a logic "high" level and the first inverted write control signal WT _ CONB <1> has a logic "low" level. Accordingly, when the first write control signal WT _ CON <1> has a logic "high" level and the first inverted write control signal WT _ CONB <1> has a logic "low" level, the first buffer IV51 may inversely buffer the signal loaded on the second transfer I/O line TIO2 to generate the first
The first read path control circuit 132 may be implemented using the second buffer IV52, the third transmission gate T53, the fourth transmission gate T54, and the fifth transmission gate T55.
The second buffer IV52 may be turned on when the first read control signal RD _ CON <1> has a logic "high" level and the first inverted read control signal RD _ CONB <1> has a logic "low" level. Accordingly, when the first read control signal RD _ CON <1> has a logic "high" level and the first inverted read control signal RD _ CONB <1> has a logic "low" level, the second buffer IV52 may inversely buffer the signal loaded on the first transmission I/O line TIO1 to generate the external data ED. When the second read control signal RD _ CON <2> has a logic "high" level and the second inverted read control signal RD _ CONB <2> has a logic "low" level, the third transfer gate T53 may be turned on to output the first internal data ID1 through the second transfer I/
Referring to fig. 6, the second
The second write path control circuit 421 may be implemented using a third buffer IV61, a sixth transfer gate T61, and a seventh transfer gate T62.
The third buffer IV61 may be turned on when the first write control signal WT _ CON <1> has a logic "high" level and the first inverted write control signal WT _ CONB <1> has a logic "low" level. Accordingly, when the first write control signal WT _ CON <1> has a logic "high" level and the first inverted write control signal WT _ CONB <1> has a logic "low" level, the third buffer IV61 may inversely buffer the signal loaded on the third transfer I/O line TIO3 to generate the second
The second read path control circuit 422 may be implemented using a fourth buffer IV62, an eighth transmission gate T63, a ninth transmission gate T64, and a tenth transmission gate T65.
The fourth buffer IV62 may be turned on when the first read control signal RD _ CON <1> has a logic "high" level and the first inverted read control signal RD _ CONB <1> has a logic "low" level. When the second read control signal RD _ CON <2> has a logic "high" level and the second inverted read control signal RD _ CONB <2> has a logic "low" level, the eighth transfer gate T63 may be turned on to output the second internal data ID2 through the third transfer I/O line TIO 3. When the enable signal EN has a logic "low" level and the inverted enable signal ENB has a logic "high" level, the ninth transmission gate T64 may be turned on. When the selection signal SEL has a logic "high" level and the inverted selection signal SELB has a logic "low" level, the tenth transmission gate T65 may be turned on to output the second internal data ID2 through the fourth transmission I/O line TIO 4.
An operation of generating the first data D1 through the first write operation path of the
Referring to fig. 7, during the first write operation, the
During the first write operation, the first
The first I/
The first
The second I/
The second
During the first write operation, the
As described above, during the first write operation, the
An operation of generating the second data D2 through the first read operation path of the
Referring to fig. 8, during the first read operation, the
During the first read operation, the
The second
The second I/
The first I/
The first
During the first read operation, the first
As described above, during the first read operation, the
An operation of generating the first data D1 through the second write operation path of the
Referring to fig. 9, during the second write operation, the
During the second write operation, the first
The first
During the second write operation, the
As described above, during the second write operation, the
An operation of generating the first data D1 through the second read operation path of the
Referring to fig. 10, during the second read operation, the
During the second read operation, the
During the second read operation, the first
The first
As described above, during the second read operation, the
According to the above-described embodiments, the semiconductor chip may have improved efficiency of detecting data errors by detecting errors of data input or output using a single error detection circuit during a write operation or a read operation with respect to a plurality of semiconductor devices sequentially stacked in the semiconductor chip.
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