阅读说明：本技术 故障冗余电路 (Fault redundant circuit ) 是由 崔谨镐 朴民奎 于 2019-08-08 设计创作，主要内容包括：本发明公开了一种故障冗余电路。一种冗余电路包括选择控制信号发生电路和列控制电路。当锁存地址信号的逻辑电平与熔丝信号的逻辑电平不同时,选择控制信号发生电路驱动被初始化的内部节点以产生选择控制信号。列控制电路基于选择控制信号来缓冲预列选择信号,以产生用于执行单元的列操作的列选择信号或者产生用于执行冗余单元的列操作的冗余列选择信号。(The invention discloses a fault redundancy circuit. A redundancy circuit includes a selection control signal generation circuit and a column control circuit. When the logic level of the latch address signal is different from the logic level of the fuse signal, the selection control signal generation circuit drives the initialized internal node to generate the selection control signal. The column control circuit buffers the pre-column selection signal based on the selection control signal to generate a column selection signal for performing a column operation of the cell or to generate a redundant column selection signal for performing a column operation of the redundant cell.)

1. A redundancy circuit, comprising:

a selection control signal generation circuit configured to: driving the initialized internal node to generate a selection control signal when a logic level of the latch address signal is different from a logic level of the fuse signal; and

a column control circuit configured to: buffering pre-selection signals based on the selection control signal to:

generating a column selection signal for performing a column operation of the cell; or

A redundancy column selection signal for performing a column operation of the redundancy cells is generated.

2. The redundancy circuit of claim 1, wherein the internal node is driven to have a predetermined logic level when a precharge signal is generated.

3. The redundancy circuit of claim 2, wherein the pre-charge signal is generated at:

when a predetermined delay period elapses from a time when a pre-column selection signal is generated to select a column path during the column operation; or

When a reset signal for performing an initialization operation is generated.

4. The redundancy circuit of claim 1, wherein the redundancy circuit,

wherein the select control signal is driven by the internal node to a first logic level; and

wherein the selection control signal is driven to a second logic level when a logic level of the latch address signal is different from a logic level of the fuse signal.

5. The redundancy circuit of claim 1, wherein the selection control signal generation circuit comprises:

a comparison circuit configured to: comparing the latch address signal and the fuse signal based on an enable pulse and a precharge signal to generate a comparison signal; and

an internal node driving circuit configured to drive the internal node based on the comparison signal.

6. The redundancy circuit of claim 5, wherein the enable pulse is generated based on an address latch pulse created to receive an address signal for accessing a cell on which the column operation is performed.

7. The redundancy circuit of claim 5, wherein the comparison circuit generates the comparison signal driven to a first logic level based on the precharge signal, and drives the comparison signal to a second logic level when a logic level of the latch address signal is different from a logic level of the fuse signal.

8. The redundancy circuit of claim 5, wherein the internal node driving circuit drives the internal node when the comparison signal has a second logic level.

9. The redundancy circuit of claim 5, wherein the comparison circuit comprises:

a comparison/drive circuit configured to: driving a first node when a logic level of the latch address signal is different from a logic level of the fuse signal;

an enable drive circuit configured to: driving a second node through the first node when the enable pulse is generated, the comparison signal being output via the second node; and

a precharge drive circuit configured to: driving the second node based on the pre-charge signal and the comparison signal.

10. The redundancy circuit of claim 9, wherein the compare/drive circuit:

driving the first node using the fuse signal based on the latch address signal; or

Driving the first node using the latch address signal based on the fuse signal.

11. The redundancy circuit of claim 9, wherein the precharge drive circuit drives the comparison signal to the first logic level when the precharge signal has the first logic level or the comparison signal has the first logic level.

12. The redundancy circuit of claim 5, wherein the selection control signal generation circuit further comprises a precharge circuit that initializes the internal node based on the precharge signal.

13. The redundancy circuit of claim 5, wherein the selection control signal generation circuit further comprises a selection control signal output circuit that buffers a signal of the internal node to generate the selection control signal and drives the internal node based on the selection control signal.

14. The redundancy circuit of claim 1, wherein the redundancy circuit,

wherein the column control circuit buffers the pre-column selection signal according to the selection control signal to generate the column selection signal, the selection control signal being driven to a first logic level when the latch address signal and the fuse signal have the same logic level; and

wherein the column control circuit buffers the pre-column selection signal according to the selection control signal to generate the redundancy column selection signal, the selection control signal being driven to a second logic level when the latch address signal and the fuse signal have different logic levels.

15. A redundancy circuit, comprising:

a comparison circuit configured to: comparing the latch address signal with a fuse signal based on the enable pulse and the precharge signal to generate a comparison signal;

an internal node drive circuit configured to: driving an internal node based on the comparison signal;

a selection control signal output circuit configured to: buffering the signal of the internal node to output a buffered signal of the internal node as a selection control signal; and

a column control circuit configured to: buffering pre-selection signals based on the selection control signal to:

generating a column selection signal for performing a column operation of the cell; or

A redundancy column selection signal for performing a column operation of the redundancy cells is generated.

16. The redundancy circuit of claim 15, wherein the enable pulse is generated based on an address latch pulse created to receive an address signal for accessing a cell on which the column operation is performed.

17. The redundancy circuit of claim 15, wherein the pre-charge signal is generated at:

when a predetermined delay period elapses from a time when a pre-column selection signal is generated to select a column path during the column operation; or

When a reset signal for performing an initialization operation is generated.

18. The redundancy circuit of claim 15, wherein the comparison circuit comprises:

a comparison/drive circuit configured to: driving a first node when a logic level of the latch address signal is different from a logic level of the fuse signal;

an enable drive circuit configured to: driving a second node through the first node when the enable pulse is generated, the comparison signal being output via the second node; and

a precharge drive circuit configured to: driving the second node based on the pre-charge signal and the comparison signal.

19. The redundancy circuit of claim 18, wherein the compare/drive circuit:

driving the first node using the fuse signal based on the latch address signal; or

Driving the first node using the latch address signal based on the fuse signal.

20. The redundancy circuit of claim 18, wherein the selection control signal output circuit buffers the signal of the internal node to generate the selection control signal, and drives the internal node based on the selection control signal.

Technical Field

Embodiments of the present disclosure relate to a fail-redundant circuit using fuse signals.

Background

The semiconductor device may store address information for accessing the defective cell into the fuse set, and may repair the defective cell by replacing the defective cell with the redundant cell when the defective cell is selected.

Disclosure of Invention

According to one embodiment, a redundancy circuit includes a selection control signal generation circuit and a column control circuit. When the logic level of the latch address signal is different from the logic level of the fuse signal, the selection control signal generation circuit drives the initialized internal node to generate the selection control signal. The column control circuit buffers the pre-column selection signal based on the selection control signal to generate a column selection signal for performing a column operation of the cell or to generate a redundant column selection signal for performing a column operation of the redundant cell.

According to another embodiment, a redundancy circuit includes: a comparison circuit configured to compare the latch address signal with the fuse signal based on the enable pulse and the precharge signal to generate a comparison signal; an internal node driving circuit configured to drive an internal node based on the comparison signal; a selection control signal output circuit configured to buffer the signal of the internal node to output a buffered signal of the internal node as a selection control signal; and a column control circuit configured to buffer the pre-column selection signal based on the selection control signal to generate a column selection signal for performing a column operation of the cell or to generate a redundant column selection signal for performing a column operation of the redundant cell.

Drawings

Fig. 1 is a block diagram illustrating a configuration of a redundancy circuit according to one embodiment of the present disclosure.

Fig. 2 is a circuit diagram showing an example of an address latch circuit included in the redundancy circuit of fig. 1.

Fig. 3 is a circuit diagram showing an example of a precharge signal generation circuit included in the redundancy circuit of fig. 1.

Fig. 4 is a circuit diagram showing an example of a selection control signal generation circuit included in the redundancy circuit of fig. 1.

Fig. 5 is a circuit diagram showing an example of a first comparator included in the selection control signal generation circuit of fig. 4.

Fig. 6 is a circuit diagram showing an example of a column control circuit included in the redundancy circuit of fig. 1.

Fig. 7 is a block diagram showing a configuration of an electronic system employing the redundancy circuit shown in fig. 1.

Detailed Description

Various embodiments of the present disclosure are described below with reference to the accompanying drawings. However, the described embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure.

As shown in fig. 1, a redundancy circuit 1 according to one embodiment may include an address latch circuit 11, a fuse signal generation circuit 12, a precharge signal generation circuit 13, a selection control signal generation circuit 14, a column control circuit 15, and a column operation circuit 16.

The address latch circuit 11 may latch the first to eighth address signals ADD <1:8> based on the address latch pulse ALATP, and may output latch signals of the first to eighth address signals ADD <1:8> as the first to eighth latch address signals LA <1:8 >. When a column operation is performed, the address latch pulse ALATP for the address latch circuit 11 may be generated to receive the first to eighth address signals ADD <1:8> for accessing the cells activated by the column operation. Column operations may be performed to select a data path for receiving or outputting data. The address latch circuit 11 is implemented to latch an address signal whose number of bits may be set to be different according to the embodiment. The configuration and operation of the address latch circuit 11 are described in detail below with reference to fig. 2.

The fuse signal generation circuit 12 may include a fuse set 121 having a plurality of fuses, and may store the first to eighth fuse signals F <1:8> into the fuse set 121. When the cells 161 selected by the first to eighth address signals ADD <1:8> are defective cells and are replaced with the redundancy cells 162, the logic level combinations of the first to eighth fuse signals F <1:8> may correspond to the logic level combinations of the first to eighth address signals ADD <1:8> input to the address latch circuit 11. The fuse set 121 may include fuses corresponding to respective ones of the first to eighth fuse signals F <1:8 >. The fuses of the fuse set 121 may include information on logic levels of the first to eighth fuse signals F <1:8> determined according to electrical open/short states of the fuses. In different embodiments, the logic level combinations of the first to eighth fuse signals F <1:8> and the logic level combinations of the first to eighth address signals ADD <1:8> may be set differently. In different embodiments, the number of bits included in the fuse signal stored in the fuse signal generation circuit 12 may be set differently.

The precharge signal generation circuit 13 may generate the precharge signal PCGPB based on the precharge selection signal PRE _ YI and the reset signal RST. The PRE-column selection signal PRE _ YI may be generated to select a column path during a column operation. The reset signal RST may be generated to perform an initialization operation. The precharge signal generation circuit 13 may generate the precharge signal PCGPB when a predetermined delay period has elapsed from the time when the precharge column selection signal PRE _ YI for performing the column operation is generated. The precharge signal generation circuit 13 may generate the precharge signal PCGPB when the reset signal RST is generated. The configuration and operation of the precharge signal generation circuit 13 are described more fully below with reference to fig. 3.

The term "predetermined" (such as a predetermined delay period) as used herein with respect to a parameter means that the value of the parameter is determined before the parameter is used in a process or algorithm. For some embodiments, the values of the parameters are determined before the process or algorithm begins. In other embodiments, the values of the parameters are determined during the process or algorithm but before the parameters are used in the process or algorithm.

The selection control signal generation circuit 14 may generate the selection control signal SYEB from the first to eighth latch address signals LA <1:8> and the first to eighth fuse signals F <1:8> based on the address latch pulse ALATP and the precharge signal PCGPB. When the precharge signal PCGPB is generated, the selection control signal generation circuit 14 may initialize the selection control signal SYEB to a first logic level. When the address latch pulse ALATP is generated, the selection control signal generation circuit 14 may hold the selection control signal SYEB having the first logic level corresponding to the initialization state if the logic level combination of the first to eighth latch address signals LA <1:8> is the same as the logic level combination of the first to eighth fuse signals F <1:8 >. When the address latch pulse ALATP is generated, the selection control signal generation circuit 14 may generate the selection control signal SYEB having a second logic level if a logic level combination of the first to eighth latch address signals LA <1:8> is different from a logic level combination of the first to eighth fuse signals F <1:8 >. In one embodiment, the first logic level may be a logic "low" level and the second logic level may be a logic "high" level. The configuration and operation of the selection control signal generation circuit 14 are described more fully below with reference to fig. 4 and 5.

The column control circuit 15 may generate the column selection signal YI or the redundant column selection signal SYI from the PRE-column selection signal PRE _ YI based on the selection control signal SYEB. When the selection control signal SYEB has the first logic level, the column control circuit 15 may buffer the PRE-column selection signal PRE _ YI to output the buffered signal of the PRE-column selection signal PRE _ YI as the redundancy column selection signal SYI. When the selection control signal SYEB has the second logic level, the column control circuit 15 may buffer the PRE-column selection signal PRE _ YI to output the buffered signal of the PRE-column selection signal PRE _ YI as the column selection signal YI. The column selection signal YI may be generated to perform a column operation of the cell 161. When the cell 161 is a fail cell, the redundancy column selection signal SYI may be generated to perform a column operation for replacing the redundancy cell 162 of the cell 161. The configuration and operation of the column control circuit 15 is described more fully below with reference to fig. 6.

The column operation circuit 16 may perform a column operation of the cell 161 or the redundancy cell 162 based on the column selection signal YI and the redundancy column selection signal SYI. When the column selection signal YI is enabled, the column operation circuit 16 may perform a column operation of the cell 161. When the redundancy column selection signal SYI is enabled, the column operation circuit 16 may perform a column operation of the redundancy unit 162.

Referring to fig. 2, the address latch circuit 11 may be implemented using a flip-flop FF 21. When the address latch pulse ALATP is generated, the flip-flop FF21 may latch the first to eighth address signals ADD <1:8>, and the flip-flop FF21 may output the latch signals of the first to eighth address signals ADD <1:8> as the first to eighth latch address signals LA <1:8 >.

Referring to fig. 3, the precharge signal generation circuit 13 may include a delay selection signal generation circuit 21 and a NOR gate NOR 21. The delay selection signal generation circuit 21 may include inverters IV21, IV22, IV23, and IV24 coupled in series. The delay selection signal generation circuit 21 may delay the PRE-column selection signal PRE _ YI by a delay period set by the inverters IV21, IV22, IV23, and IV24 to generate the delay selection signal PREd. The NOR gate NOR21 may perform a logical NOR operation of delaying the selection signal PREd and the reset signal RST to generate the precharge signal PCGPB. The NOR gate NOR21 may generate the precharge signal PCGPB having a logic "low" level when at least one of the delay selection signal PREd and the reset signal RST has a logic "high" level. The precharge signal generation circuit 13 may generate the precharge signal PCGPB having a logic "low" level when a delay period set by the inverters IV21, IV22, IV23, and IV24 elapses from the time when the precharge column selection signal PRE _ YI for performing the column operation is generated to have a logic "high" level. The precharge signal generation circuit 13 may generate the precharge signal PCGPB having a logic "low" level when the reset signal RST is generated to have a logic "high" level.

Referring to fig. 4, the selection control signal generation circuit 14 may include an enable pulse generation circuit 31, a comparison circuit 32, an internal node drive circuit 33, a precharge circuit 34, and a selection control signal output circuit 35.

The enable pulse generating circuit 31 may include inverters IV31, IV32, and IV 33. The enable pulse generating circuit 31 may generate the enable pulse ENP having a logic "low" level when a period set by the inverters IV31, IV32, and IV33 elapses from the time when the address latch pulse ALATP is generated to have a logic "high" level.

The comparison circuit 32 may include a first comparator 321, a second comparator 322, a third comparator 323, a fourth comparator 324, a fifth comparator 325, a sixth comparator 326, a seventh comparator 327, and an eighth comparator 328.

The first comparator 321 may receive the precharge signal PCGPB, the enable pulse ENP, the first latch address signal LA <1>, and the first fuse signal F <1> to generate a first comparison signal COM <1 >. When the precharge signal PCGPB is generated, the first comparator 321 may initialize the first comparison signal COM <1> to a logic "low" level. When the enable pulse ENP is generated, the first comparator 321 may compare the first latch address signal LA <1> with the first fuse signal F <1> to generate a first comparison signal COM <1 >. When the enable pulse ENP is generated, the first comparator 321 may hold the first comparison signal COM <1> having a logic "low" level if the first latch address signal LA <1> has the same logic level as the first fuse signal F <1 >. When the enable pulse ENP is generated, the first comparator 321 may generate the first comparison signal COM <1> having a logic "high" level if a logic level of the first latch address signal LA <1> is different from a logic level of the first fuse signal F <1 >. The configuration and operation of the first comparator 321 is described more fully below with reference to fig. 5.

Each of the second to eighth comparators 322, 323, 324, 325, 326, 327, and 328 may be designed to have substantially the same configuration and operation as the first comparator 321. Therefore, a detailed description of the second to eighth comparators 322, 323, 324, 325, 326, 327 and 328 is omitted for the sake of brevity.

The internal node driving circuit 33 may include NMOS transistors N31, N32, N33, N34, N35, N36, N37, and N38. When the first comparison signal COM <1> has a logic "high" level, the NMOS transistor N31 may drive the node nd31 to the ground voltage VSS. When the second comparison signal COM <2> has a logic "high" level, the NMOS transistor N32 may drive the node nd31 to the ground voltage VSS. When the third comparison signal COM <3> has a logic "high" level, the NMOS transistor N33 may drive the node nd31 to the ground voltage VSS. When the fourth comparison signal COM <4> has a logic "high" level, the NMOS transistor N34 may drive the node nd31 to the ground voltage VSS. When the fifth comparison signal COM <5> has a logic "high" level, the NMOS transistor N35 may drive the node nd31 to the ground voltage VSS. When the sixth comparison signal COM <6> has a logic "high" level, the NMOS transistor N36 may drive the node nd31 to the ground voltage VSS. When the seventh comparison signal COM <7> has a logic "high" level, the NMOS transistor N37 may drive the node nd31 to the ground voltage VSS. When the eighth comparison signal COM <8> has a logic "high" level, the NMOS transistor N38 may drive the node nd31 to the ground voltage VSS.

The precharge circuit 34 may include a PMOS transistor P31. When the precharge signal PCGPB has a logic "low" level, the PMOS transistor P31 may drive the node nd31 to the power supply voltage VDD. The precharge circuit 34 may drive the node nd31 to the power supply voltage VDD in response to a precharge signal PCGPB generated to have a logic "low" level when a predetermined delay period elapses from the time when the PRE-column selection signal PRE _ YI is generated to perform a column operation for receiving or outputting data or when the reset signal RST is generated to perform an initialization operation.

The selection control signal output circuit 35 may include an inverter IV34 and a PMOS transistor P32. The inverter IV34 may inversely buffer the signal of the node nd31 to output an inverted buffered signal of the node nd31 as the selection control signal SYEB. When the selection control signal SYEB has a logic "low" level, the PMOS transistor P32 may be turned on to drive the node nd31 to the power supply voltage VDD. When the node nd31 has a logic "low" level, the selection control signal output circuit 35 may generate the selection control signal SYEB driven to a logic "high" level. When the node nd31 has a logic "high" level, the selection control signal output circuit 35 may generate the selection control signal SYEB driven to a logic "low" level, and may drive the node nd31 to the power supply voltage VDD.

When the precharge signal PCGPB is generated, the selection control signal generation circuit 14 may drive the node nd31 to a logic "high" level and may drive the selection control signal SYEB to a logic "low" level to initialize the selection control signal SYEB. Since all of the first to eighth comparison signals COM <1:8> are generated to have a logic "low" level if the logic level combination of the first to eighth latch address signals LA <1:8> is the same as the logic level combination of the first to eighth fuse signals F <1:8> in the case where the address latch pulse ALATP is generated to have a logic "high" level, the selection control signal generation circuit 14 may hold the node nd31 having a logic "high" level and may hold the selection control signal SYEB having a logic "low" level. Since at least one of the first to eighth comparison signals COM <1:8> is generated to have a logic "high" level if the logic level combination of the first to eighth latch address signals LA <1:8> is different from the logic level combination of the first to eighth fuse signals F <1:8> in the case where the address latch pulse ALATP is generated to have the logic "high" level, the selection control signal generation circuit 14 may drive the node nd31 to a logic "low" level and may drive the selection control signal SYEB having a logic "high" level. For one embodiment, the selection control signal generation circuit 14 may be implemented to drive the node nd31 only in the case where the logic level combination of the first to eighth latch address signals LA <1:8> is different from the logic level combination of the first to eighth fuse signals F <1:8 >. Therefore, the number of logical operations performed in the selection control signal generation circuit 14 can be reduced to reduce the power consumption of the redundancy circuit 1 and to improve the operation speed of the redundancy circuit 1.

Referring to fig. 5, the first comparator 321 may include a comparison/driving circuit 51, an enable driving circuit 52, and a precharge driving circuit 53.

The comparison/drive circuit 51 may include PMOS transistors P51 and P52. When the first fuse signal F <1> has a logic "low" level, the PMOS transistor P51 may drive the node nd51 according to the first latch address signal LA <1 >. When the first latch address signal LA <1> has a logic "low" level, the PMOS transistor P52 may drive the node nd51 according to the first fuse signal F <1 >. When the logic level of the first latch address signal LA <1> is different from the logic level of the first fuse signal F <1>, the comparison/drive circuit 51 may drive the node nd51 to a logic "high" level. When the first fuse signal F <1> has a logic "low" level and the first latch address signal LA <1> has a logic "high" level, the comparison/drive circuit 51 may drive the node nd51 to a logic "high" level using the PMOS transistor P51 that is turned on. When the first fuse signal F <1> has a logic "high" level and the first latch address signal LA <1> has a logic "low" level, the comparison/drive circuit 51 may drive the node nd51 to a logic "high" level using the PMOS transistor P52 that is turned on. When the first latch address signal LA <1> and the first fuse signal F <1> have the same logic level, the comparison/driving circuit 51 may terminate to drive the node nd 51.

The enable driver circuit 52 may include a PMOS transistor P53. When the enable pulse ENP is generated to have a logic "low" level, the PMOS transistor P53 may drive the node nd52 according to the level of the node nd 51. When the enable pulse ENP is generated to have a logic "low" level by the address latch pulse ALATP having a logic "high" level for the column operation and the logic level of the first latch address signal LA <1> is different from that of the first fuse signal F <1>, the enable driving circuit 52 may drive the node nd52 to a logic "high" level using the node nd51 having a logic "high" level. The first comparison signal COM <1> may be output via the node nd 52.

The precharge driving circuit 53 may include a NAND gate NAND51 and an NMOS transistor N51. The NAND gate NAND51 may perform a logical NAND operation of the first comparison signal COM <1> and the precharge signal PCGPB. The NMOS transistor N51 may be turned on by the output signal of the NAND gate NAND51 to drive the node nd52 to the ground voltage VSS. The precharge driving circuit 53 may drive the first comparison signal COM <1> to a logic "low" level, the first comparison signal COM <1> being output through the node nd52 through the NMOS transistor N51 turned on when the precharge signal PCGPB is generated to have a logic "low" level. The precharge driving circuit 53 may drive the first comparison signal COM <1> to a logic "low" level, the first comparison signal COM <1> being output via the node nd52 through the NMOS transistor N51 turned on when the first comparison signal COM <1> is generated to have a logic "low" level.

When the precharge signal PCGPB is generated to have a logic "low" level, the first comparator 321 may initialize the first comparison signal COM <1> to a logic "low" level. When the enable pulse ENP is generated to have a logic "low" level and the first latch address signal LA <1> has the same logic level as the first fuse signal F <1>, the first comparator 321 may hold the first comparison signal COM <1> having a logic "low" level. When the enable pulse ENP is generated to have a logic "low" level and the logic level of the first latch address signal LA <1> is different from the logic level of the first fuse signal F <1>, the first comparator 321 may generate the first comparison signal COM <1> having a logic "high" level.

For one embodiment, when comparing the first latch address signal LA <1> with the first fuse signal F <1> to generate the first comparison signal COM <1>, the first comparator 321 may be implemented to drive the nodes nd51 and nd52 only in case that the logic level of the first latch address signal LA <1> is different from the logic level of the first fuse signal F <1 >. Therefore, the number of logical operations can be reduced to reduce the power consumption of the redundancy circuit 1 and to improve the operation speed of the redundancy circuit 1.

Referring to fig. 6, the column control circuit 15 may include inverters IV61, IV62, and IV63, and NAND gates NAND61 and NAND 62. The inverter IV61 may inversely buffer the selection control signal SYEB to output an inverted buffered signal of the selection control signal SYEB. The NAND gate NAND61 may perform a logical NAND operation of the selection control signal SYEB and the PRE-column selection signal PRE _ YI. The NAND gate NAND62 may perform a logical NAND operation of the PRE-column selection signal PRE _ YI and the output signal of the inverter IV 61. The inverter IV62 may inversely buffer the output signal of the NAND gate NAND61 to generate the column selection signal YI. The inverter IV63 may inversely buffer the output signal of the NAND gate NAND62 to generate the redundancy column selection signal SYI.

When the selection control signal SYEB has a logic "high" level, the column control circuit 15 may buffer the PRE-column selection signal PRE _ YI to output a buffered signal of the PRE-column signal PRE _ YI as the column selection signal YI. The column selection signal YI may be generated to perform a column operation of the cell 161. When the selection control signal SYEB has a logic "low" level, the column control circuit 15 may buffer the PRE-column selection signal PRE _ YI to output the buffered signal of the PRE-column selection signal PRE _ YI as the redundancy column selection signal SYI. When the cell 161 is a defective cell corresponding to a defective cell, the redundancy column selection signal SYI may be generated to perform a column operation of the redundancy cell 162 used to replace the cell 161.

As described above, when the first to eighth latch address signals LA <1:8> and the first to eighth fuse signals F <1:8> are compared to generate the first to eighth comparison signals COM <1:8>, the redundancy circuit 1 according to one embodiment may be implemented to drive the internal nodes only in the case where the logic level combination of the first to eighth latch address signals LA <1:8> and the logic level combination of the first to eighth fuse signals F <1:8> are different. Therefore, the number of logical operations performed in the redundancy circuit 1 can be reduced to reduce the power consumption of the redundancy circuit 1 and to improve the operation speed of the redundancy circuit 1.

The redundancy circuit 1 described with reference to fig. 1 to 6 may be applied to an electronic system including a memory system, a graphic system, a computing system, a mobile system, and the like. For example, as shown in fig. 7, an electronic system 1000 according to an embodiment may include a data storage circuit 1001, a memory controller 1002, a buffer memory 1003, and an input/output (I/O) interface 1004.

The data storage circuit 1001 may store data output from the memory controller 1002 or may read and output the stored data to the memory controller 1002 according to a control signal output from the memory controller 1002. The data storage circuit 1001 may include the redundancy circuit 1 shown in fig. 1. Meanwhile, the data storage circuit 1001 may include a nonvolatile memory capable of retaining its stored data even when its power supply is interrupted. The nonvolatile memory may be a flash memory such as a NOR type flash memory or a NAND type flash memory, a phase change random access memory (PRAM), a Resistive Random Access Memory (RRAM), a Spin Transfer Torque Random Access Memory (STTRAM), a Magnetic Random Access Memory (MRAM), or the like.

The memory controller 1002 may receive a command output from an external device (e.g., a host device) via the I/O interface 1004 and may decode the command output from the host device to control an operation for inputting data into the data storage circuit 1001 or the buffer memory 1003 or an operation for outputting data stored in the data storage circuit 1001 or the buffer memory 1003. Although fig. 7 shows the memory controller 1002 as a single block, the memory controller 1002 may include one controller for controlling the data storage circuit 1001 and another controller for controlling the buffer memory 1003 representing a volatile memory.

The buffer memory 1003 may temporarily store data to be processed by the memory controller 1002. That is, the buffer memory 1003 can temporarily store data output from the data storage circuit 1001 or data to be input to the data storage circuit 1001. The buffer memory 1003 may store data output from the memory controller 1002 according to a control signal. The buffer memory 1003 can read out data stored therein and output the data to the memory controller 1002. The buffer memory 1003 may include a volatile memory such as a Dynamic Random Access Memory (DRAM), a mobile DRAM, or a Static Random Access Memory (SRAM). The buffer memory 1003 may include the redundancy circuit 1 shown in fig. 1.

The I/O interface 1004 may physically and electrically connect the memory controller 1002 to an external device (i.e., a host). Accordingly, the memory controller 1002 may receive control signals and data provided from an external device (i.e., a host) via the I/O interface 1004 and may output data output from the memory controller 1002 to the external device (i.e., the host) via the I/O interface 1004. That is, electronic system 1000 may communicate with a host via I/O interfaces 1004. The I/O interface 1004 may include any of a variety of interface protocols, such as Universal Serial Bus (USB), multimedia card (MMC), peripheral component interconnect express (PCI-E), serial attached SCSI (sas), serial AT attachment (SATA), parallel AT attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Device Interface (ESDI), and Integrated Drive Electronics (IDE).

Electronic system 1000 may be used as a secondary storage device or an external storage device for a host. The electronic system 1000 may include a Solid State Disk (SSD), a USB memory, a Secure Digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a Secure Digital High Capacity (SDHC) card, a memory stick card, a Smart Media (SM) card, a multimedia card (MMC), an embedded multimedia card (eMMC), or a Compact Flash (CF) card, etc.