阅读说明：本技术 一种二维互补型存储器及其制备方法 (Two-dimensional complementary memory and preparation method thereof ) 是由 王天宇 孟佳琳 何振宇 陈琳 孙清清 张卫 于 2021-03-08 设计创作，主要内容包括：本发明属于半导体技术领域,具体为一种二维互补型存储器及其制备方法。本发明二维互补型存储器包括：衬底；底电极阵列,包括多条沿第一方向延伸,沿第二方向排列的线状底电极；在底电极阵列上依次形成的第一BN二维材料层、石墨烯二维材料层、第二BN二维材料层；以及顶电极阵列,包括多条沿第二方向延伸,沿第一方向排列的线状顶电极,其中,所述第一方向与所述第二方向垂直。本发明采用独立的互补型存储器解决交叉阵列中的“潜行电流”问题,提高了材料的选择范围,同时全二维材料构建的范德瓦尔斯异质结作为互补型存储器的功能层,可缩减至原子级别的厚度,有效提高二维存储器的高密度集成能力。(The invention belongs to the technical field of semiconductors, and particularly relates to a two-dimensional complementary memory and a preparation method thereof. The two-dimensional complementary memory of the present invention includes: a substrate; a bottom electrode array including a plurality of linear bottom electrodes extending in a first direction and arranged in a second direction; the first BN two-dimensional material layer, the graphene two-dimensional material layer and the second BN two-dimensional material layer are sequentially formed on the bottom electrode array; and the top electrode array comprises a plurality of linear top electrodes which extend along a second direction and are arranged along a first direction, wherein the first direction is vertical to the second direction. The invention adopts the independent complementary memory to solve the problem of 'sneak current' in the cross array, improves the selection range of materials, and simultaneously, the Van der Waals heterojunction constructed by the full two-dimensional material is used as the functional layer of the complementary memory, thus reducing the thickness to the atomic level and effectively improving the high-density integration capability of the two-dimensional memory.)

1. A two-dimensional complementary memory, comprising:

a substrate;

a bottom electrode array formed on the substrate and including a plurality of linear bottom electrodes extending in a first direction and arranged in a second direction;

a first BN two-dimensional material layer formed on the bottom electrode array;

a graphene two-dimensional material layer formed on the first BN two-dimensional material layer;

a second BN two-dimensional material layer formed on the graphene two-dimensional material layer;

a top electrode array including a plurality of linear top electrodes extending in the second direction and arranged in the first direction,

wherein the first direction is perpendicular to the second direction.

2. A two-dimensional complementary memory according to claim 1, wherein the linear bottom electrode and the linear top electrode are made of Ag or Cu, have a width of 2 μm to 50 μm, and have a thickness of 20nm to 100 nm.

3. A two-dimensional complementary memory according to claim 1, wherein the thickness of the first BN two-dimensional material layer is 5nm to 50 nm.

4. A two-dimensional complementary memory according to claim 1, wherein the thickness of the graphene two-dimensional material layer is 10nm to 50 nm.

5. A two-dimensional complementary memory according to claim 1, wherein the thickness of the second BN two-dimensional material layer is 5nm to 50 nm.

6. A preparation method of a two-dimensional complementary memory is characterized by comprising the following steps:

providing a substrate;

forming a bottom electrode array on the substrate, wherein the bottom electrode array comprises a plurality of linear bottom electrodes which extend along a first direction and are arranged along a second direction;

transferring a first BN two-dimensional material layer onto the bottom electrode array;

transferring a graphene two-dimensional material layer onto the first BN two-dimensional material layer;

transferring a second BN two-dimensional material layer onto the graphene two-dimensional material layer;

forming a top electrode array on the second BN two-dimensional material layer, wherein the top electrode array comprises a plurality of linear top electrodes which extend along the second direction and are arranged along the first direction,

wherein the first direction is perpendicular to the second direction.

7. The method of claim 6, wherein the bottom and top linear electrodes are made of Ag or Cu, have a width of 2-50 μm and a thickness of 20-100 nm.

8. The method according to claim 6, wherein the first BN two-dimensional material layer has a thickness of 5nm to 50 nm.

9. The method according to claim 6, wherein the graphene two-dimensional material layer has a thickness of 10nm to 50 nm.

10. The method according to claim 6, wherein the second BN two-dimensional material layer has a thickness of 5nm to 50 nm.

Technical Field

The invention belongs to the technical field of semiconductors, and particularly relates to a two-dimensional complementary memory and a preparation method thereof.

Background

At present, two-dimensional materials are widely studied due to their characteristics such as atomic-scale thickness, excellent flexibility, unique photoelectric properties, and the like. In particular, a huge application potential is demonstrated in terms of two-terminal memories. However, the high density integration capability of two-dimensional memories is still plagued by the problem of "sneak current" in crossbar arrays.

To solve the "sneak current problem" of the crossbar array, a 1S1R (i.e., 1 gate device +1 memory device), 1T1R (i.e., 1 transistor +1 memory device) structure is proposed. However, the 1S1R structure and the 1T1R structure involve the integration of two devices, and the factors of process compatibility, current matching, and the like need to be considered, which greatly limits the application of device material selection and high-density storage. In addition, 1T1R has poor integration capability and cannot reach crossbar array 4F²Density.

In order to easily solve the "sneak current" problem in high-density crossbar arrays, complementary memories have been proposed. The complementary memory is used as an independent memory device, and the effect of 1S1R or 1T1R is realized without considering the problems of process compatibility and current or voltage matching. In addition, the device structure can greatly reduce the characteristic size of the device, and is beneficial to the increase of the selection range of the device material and the improvement of the integration capability.

Disclosure of Invention

In order to solve the above problems, an object of the present invention is to provide a two-dimensional complementary memory and a method for manufacturing the same.

The invention provides a two-dimensional complementary memory, comprising:

a substrate;

a bottom electrode array including a plurality of linear bottom electrodes extending in a first direction and arranged in a second direction;

a first BN two-dimensional material layer formed on the bottom electrode array;

a graphene two-dimensional material layer formed on the first BN two-dimensional material layer;

the second BN two-dimensional material layer is formed on the graphene two-dimensional material layer;

the top electrode array comprises a plurality of linear top electrodes which extend along a second direction and are arranged along a first direction, wherein the first direction is perpendicular to the second direction.

In the two-dimensional complementary memory of the present invention, preferably, the material of the linear bottom electrode and the linear top electrode is Ag or Cu, the width is 2 μm to 50 μm, and the thickness is 20nm to 100 nm.

In the two-dimensional complementary memory of the invention, preferably, the thickness of the first BN two-dimensional material layer is 5nm to 50 nm.

In the two-dimensional complementary memory, the thickness of the graphene two-dimensional material layer is preferably 10 nm-50 nm.

In the two-dimensional complementary memory of the invention, preferably, the thickness of the second BN two-dimensional material layer is 5nm to 50 nm.

The invention also provides a preparation method of the two-dimensional complementary memory, which comprises the following steps:

providing a substrate;

forming a bottom electrode array on the substrate, wherein the bottom electrode array comprises a plurality of linear bottom electrodes which extend along a first direction and are arranged along a second direction;

transferring a first BN two-dimensional material layer onto the bottom electrode array;

transferring a graphene two-dimensional material layer onto the first BN two-dimensional material layer;

transferring a second BN two-dimensional material layer onto the graphene two-dimensional material layer;

and forming a top electrode array on the second BN two-dimensional material layer, wherein the top electrode array comprises a plurality of linear top electrodes which extend along a second direction and are arranged along a first direction, and the first direction is perpendicular to the second direction.

In the preparation method of the present invention, preferably, the material of the linear bottom electrode and the linear top electrode is Ag or Cu, the width is 2 μm to 50 μm, and the thickness is 20nm to 100 nm.

In the preparation method, preferably, the thickness of the first BN two-dimensional material layer is 5nm to 50 nm.

In the preparation method, preferably, the thickness of the graphene two-dimensional material layer is 10 nm-50 nm.

In the preparation method, preferably, the thickness of the second BN two-dimensional material layer is 5nm to 50 nm.

The invention adopts the independent complementary memory to solve the problem of 'sneak current' in the cross array, not only improves the selection range of materials, but also has excellent size reduction capability and has 4F²Potential for storage density. The Van der Waals heterojunction constructed by adopting a full two-dimensional material is used as a functional layer of a complementary memory, the thickness can be reduced to an atomic level, and the Van der Waals heterojunction is compatible with a new two-dimensional system in the semiconductor development route planning. In addition, the excellent flexibility of the two-dimensional material provides a new choice for the further development of flexible high-density memory devices.

Drawings

FIG. 1 is a flow chart of a two-dimensional complementary memory fabrication method.

Fig. 2 is a schematic diagram of the device structure after forming marks on the substrate.

Fig. 3 is a schematic diagram of the structure of the device after the bottom electrode array is formed.

Fig. 4 is a schematic view of the device structure after the first BN two-dimensional material layer is formed.

Fig. 5 is a schematic structural diagram of the device after the graphene two-dimensional material layer is formed.

Fig. 6 is a schematic view of the device structure after the second BN two-dimensional material layer is formed.

Fig. 7 is a structural diagram of a two-dimensional complementary memory.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more clearly and completely understood, the technical solutions in the embodiments of the present invention will be described below with reference to the accompanying drawings in the embodiments of the present invention, and it should be understood that the specific embodiments described herein are only for explaining the present invention and are not intended to limit the present invention. The described embodiments are only some embodiments of the invention, not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it should be noted that the terms "upper", "lower", "vertical", "horizontal", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

Furthermore, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described below in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details. Unless otherwise specified below, each part in the device may be formed of a material known to those skilled in the art, or a material having a similar function developed in the future may be used.

FIG. 1 is a flow chart of a two-dimensional complementary memory fabrication method. As shown in fig. 1, in step S1, a silicon oxide wafer is prepared as the substrate 200, spin-coated with photoresist, and uv-exposed to obtain the mark region. Preferably, the spin of the photoresist can be spin at 500r/s for 5s at a low speed and then spin at 4000r/s for 40s at a high speed. Thereafter, Ti having a thickness of 15nm and Au having a thickness of 70nm were sputtered by Physical Vapor Deposition (PVD), and excess metal was removed by ultrasonic treatment with acetone to obtain a substrate 200 having a mark 201, and the resulting structure is shown in FIG. 2.

In step S2, a bottom electrode array is formed by defining the shape of the bottom electrode array on the substrate 200 by e-beam lithography, and then depositing Ag metal to form the bottom electrode array, and the resulting structure is shown in fig. 3. The bottom electrode array includes a plurality of line-shaped bottom electrodes 202 extending in a first direction and arranged in a second direction. The linear bottom electrode may be made of Cu or the like, and preferably has a width of 2 to 50 μm and a thickness of 20 to 100 nm.

In step S3, a first BN two-dimensional material layer 203 with a thickness of 10nm is transferred onto the bottom electrode array by using a mechanical lift-off method, and the resulting structure is shown in fig. 4. Preferably, the thickness of the first BN two-dimensional material layer is 5 nm-50 nm.

In step S4, a 20nm thick graphene 204 is transferred onto the first BN two-dimensional material layer 203 by using a mechanical lift-off method, and the resulting structure is shown in fig. 5. The thickness of the graphene is preferably 10 nm-50 nm.

In step S5, a second BN two-dimensional material layer 205 with a thickness of 10nm is transferred onto the graphene 204 by using a mechanical lift-off method, and the resulting structure is shown in fig. 6. The thickness of the second BN two-dimensional material layer 205 is preferably 5nm to 50 nm.

In step S6, the top electrode array is formed by defining the shape of the top electrode array by e-beam lithography and then growing Ag metal by physical vapor deposition, and the resulting structure is shown in fig. 7. The top electrode array includes a plurality of top electrodes 206 extending along a second direction and arranged along a first direction, wherein the first direction is perpendicular to the second direction. In the present embodiment, the width of the line-shaped top electrode 206 is 5 μm and the thickness thereof is 50nm, but the present invention is not limited thereto, and the width of the line-shaped top electrode may be 2 μm to 50 μm and the thickness thereof may be 20nm to 100 nm. The linear top electrode may be made of metal such as Cu.

While the specific embodiments of the two-dimensional complementary memory manufacturing method according to the present invention have been described in detail above, the present invention is not limited thereto. The specific embodiment of each step may be different depending on the case. In addition, the order of some steps may be reversed, some steps may be omitted, etc.

FIG. 7 is a schematic diagram of a two-dimensional complementary memory of the present invention. As shown in fig. 7, the two-dimensional complementary memory includes: a substrate 200; a bottom electrode array including a plurality of linear bottom electrodes 202 extending in a first direction and arranged in a second direction; a first BN two-dimensional material layer 203 formed on the bottom electrode array; a graphene two-dimensional material layer 204 formed on the first BN two-dimensional material layer 203; a second BN two-dimensional material layer 205 formed on the graphene two-dimensional material layer 204; the top electrode array includes a plurality of top electrodes 206 extending along a second direction and arranged along a first direction, wherein the first direction is perpendicular to the second direction.

Preferably, the linear bottom electrode is made of Ag, Cu, etc., and has a width of 2-50 μm and a thickness of 20-100 nm. Preferably, the thickness of the first BN two-dimensional material layer is 5 nm-50 nm. The thickness of the graphene two-dimensional material layer is 10 nm-50 nm. The thickness of the second BN two-dimensional material layer is 5 nm-50 nm.

The invention adopts the independent complementary memory to solve the problem of 'sneak current' in the cross array, not only improves the selection range of materials, but also has excellent size reduction capability and has 4F²Potential for storage density. The Van der Waals heterojunction constructed by adopting a full two-dimensional material is used as a functional layer of a complementary memory, the thickness can be reduced to an atomic level, and the Van der Waals heterojunction is compatible with a new two-dimensional system in the semiconductor development route planning. In addition, the excellent flexibility of the two-dimensional material provides a new choice for the further development of flexible high-density memory devices.

The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.