阅读说明：本技术 存储器阵列及其制造方法 (Memory array and method of manufacturing the same ) 是由 杨柏峰 杨世海 吴昭谊 王圣祯 林佑明 于 2021-03-16 设计创作，主要内容包括：公开了包括伪导电线的3D存储器阵列及其形成方法。在实施例中,一种存储器阵列包括在半导体衬底上方的铁电(FE)材料,该FE材料包括与字线接触的竖直侧壁；在FE材料上的氧化物半导体(OS)层,该OS层接触源极线和位线,该FE材料在OS层与字线之间；晶体管,包括FE材料的一部分、字线的一部分、OS层的一部分、源极线的一部分以及位线的一部分；以及晶体管与半导体衬底之间的第一伪字线,该FE材料还包括与第一伪字线接触的第一锥形侧壁。本发明的实施例还涉及存储器阵列及其制造方法。(3D memory arrays including dummy conductive lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a Ferroelectric (FE) material over a semiconductor substrate, the FE material including vertical sidewalls in contact with word lines; an Oxide Semiconductor (OS) layer on the FE material, the OS layer contacting the source line and the bit line, the FE material between the OS layer and the word line; a transistor including a portion of the FE material, a portion of the word line, a portion of the OS layer, a portion of the source line, and a portion of the bit line; and a first dummy word line between the transistor and the semiconductor substrate, the FE material further including a first tapered sidewall in contact with the first dummy word line. Embodiments of the invention also relate to memory arrays and methods of manufacturing the same.)

1. A memory array, comprising:

a Ferroelectric (FE) material over the semiconductor substrate, the FE material including vertical sidewalls in contact with the word lines;

an Oxide Semiconductor (OS) layer over the FE material, the OS layer contacting a source line and a bit line, wherein the FE material is between the OS layer and the word line;

a transistor comprising a portion of the FE material, a portion of the word line, a portion of the OS layer, a portion of the source line, and a portion of the bit line; and

a first dummy word line between the transistor and the semiconductor substrate, wherein the FE material further includes a first tapered sidewall in contact with the first dummy word line.

2. The memory array of claim 1, further comprising a second dummy word line over the transistor, the transistor being between the second dummy word line and the semiconductor substrate, wherein the FE material further comprises a second tapered sidewall in contact with the second dummy word line.

3. The memory array of claim 2, wherein a distance between opposing sidewalls of the second tapered sidewall of the FE material decreases in a direction toward the semiconductor substrate.

4. The memory array of claim 1, wherein a distance between opposing sidewalls of the first tapered sidewall of the FE material decreases in a direction toward the semiconductor substrate.

5. The memory array of claim 1, further comprising:

a functional memory cell region including the word line and the transistor; and

a first dummy region between the functional memory cell region and the semiconductor substrate, the first dummy region including the first dummy word line, wherein a ratio of a thickness of the first dummy region in a first direction perpendicular to a main surface of the semiconductor substrate to a thickness of the functional memory cell region in the first direction is 0.01 to 0.6.

6. The memory array of claim 1, wherein the word lines have a first length in a second direction parallel to a major surface of the semiconductor substrate, wherein the first dummy word lines have a second length in the second direction, and wherein the second length is greater than the first length.

7. The memory array of claim 6, further comprising a second dummy word line between the first dummy word line and the semiconductor substrate, the second dummy word line having a third length in the second direction equal to the second length.

8. A memory array, comprising:

one or more lower dummy word lines over the semiconductor substrate;

one or more word lines above the lower dummy word line;

one or more upper dummy word lines over the word lines;

a source line extending through the lower dummy word line, the word line, and the upper dummy word line;

bit lines extending through the lower dummy word lines, the word lines, and the upper dummy word lines; and

one or more transistors, each of the transistors including a portion of one of the word lines, a portion of the source line, and a portion of the bit line, wherein a width of the upper dummy word line is less than a width of the word line, and wherein a length of the upper dummy word line is less than a length of the word line.

9. The memory array of claim 8, wherein the width of the word line is less than the width of the lower dummy word line, and wherein the length of the word line is less than the length of the lower dummy word line.

10. A method of fabricating a memory array, comprising:

forming a multilayer stack over a semiconductor substrate, the multilayer stack comprising alternating conductive and dielectric layers;

patterning a first trench extending through the multilayer stack, a first portion of the first trench proximate to the semiconductor substrate having a first tapered sidewall, a second portion of the first trench having a vertical sidewall, a third portion of the first trench distal to the semiconductor substrate having a second tapered sidewall, wherein the vertical sidewall extends from the first tapered sidewall to the second tapered sidewall, wherein patterning the first trench defines a bottom dummy word line adjacent the first portion, a word line adjacent the second portion, and a top dummy word line adjacent the third portion;

depositing a Ferroelectric (FE) material along the first tapered sidewalls, the vertical sidewalls, the second tapered sidewalls, and a bottom surface of the first trench;

depositing an Oxide Semiconductor (OS) layer over the FE material, wherein a first portion of the OS layer, a first portion of the FE material, and a portion of the bottom dummy word line form one or more dummy transistors, and wherein a second portion of the OS layer, a second portion of the FE material, and a portion of the word line form one or more transistors;

patterning the multilayer stack such that the conductive layer and the dielectric layer have a stepped shape in a cross-sectional view; and

forming a conductive line electrically coupled to the one or more transistors.

Technical Field

Embodiments of the invention relate to memory arrays and methods of manufacturing the same.

Background

For example, semiconductor memory is used in integrated circuits for electronic applications including radios, televisions, cell phones, and personal computing devices. Semiconductor memories include two main categories: volatile memory and non-volatile memory. Volatile memory includes Random Access Memory (RAM), which can be further divided into two subcategories: static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM). Both SRAM and DRAM are volatile because they lose stored information when not powered.

On the other hand, the nonvolatile memory may store data thereon when not powered on. One type of non-volatile semiconductor memory is ferroelectric random access memory (FeRAM or FRAM). Advantages of FeRAM include fast read/write speed and small size.

Disclosure of Invention

According to an aspect of an embodiment of the present invention, there is provided a memory array including: a Ferroelectric (FE) material over the semiconductor substrate, the FE material including vertical sidewalls in contact with the word lines; an Oxide Semiconductor (OS) layer over the FE material, the OS layer contacting the source line and the bit line, wherein the FE material is between the OS layer and the word line; a transistor including a portion of the FE material, a portion of the word line, a portion of the OS layer, a portion of the source line, and a portion of the bit line; and a first dummy word line between the transistor and the semiconductor substrate, wherein the FE material further includes a first tapered sidewall in contact with the first dummy word line.

According to another aspect of an embodiment of the present invention, there is provided a memory array including: one or more lower dummy word lines over the semiconductor substrate; one or more word lines above the lower dummy word line; one or more upper dummy word lines over the word lines; a source line extending through the lower dummy word line, the word line, and the upper dummy word line; bit lines extending through the lower dummy word lines, the word lines, and the upper dummy word lines; and one or more transistors, each of the transistors including a portion of one of the word lines, a portion of the source line, and a portion of the bit line, wherein a width of the upper dummy word line is less than a width of the word line, and wherein a length of the upper dummy word line is less than a length of the word line.

According to another aspect of an embodiment of the present invention, there is provided a method of manufacturing a memory array, including: forming a multi-layer stack over a semiconductor substrate, the multi-layer stack comprising alternating conductive and dielectric layers; patterning a first trench extending through the multilayer stack, a first portion of the first trench proximate to the semiconductor substrate having a first tapered sidewall, a second portion of the first trench having a vertical sidewall, and a third portion of the first trench distal to the semiconductor substrate having a second tapered sidewall, wherein the vertical sidewall extends from the first tapered sidewall to the second tapered sidewall, wherein patterning the first trench defines a bottom dummy word line adjacent to the first portion, a word line adjacent to the second portion, and a top dummy word line adjacent to the third portion; depositing a Ferroelectric (FE) material along the first tapered sidewalls, the vertical sidewalls, the second tapered sidewalls, and the bottom surface of the first trench; depositing an Oxide Semiconductor (OS) layer over the FE material, wherein a first portion of the OS layer, a first portion of the FE material, and a portion of the bottom dummy word line form one or more dummy transistors, and wherein a second portion of the OS layer, a second portion of the FE material, and a portion of the word line form one or more transistors; patterning the multilayer stack such that the conductive layer and the dielectric layer have a stepped shape in a cross-sectional view; and forming a conductive line electrically coupled to the one or more transistors.

Drawings

Aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1A and 1B illustrate perspective and circuit diagrams of a memory array according to some embodiments.

Fig. 2, 3, 4, 5, 6, 7, 8, 9, 10A, 10B, 11A, 11B, 12A, 12B, 13A, 13B, 13C, 14A, 14B, 14C, 15, 16, 17, 18, 19, 20, 21, 22, 23A, 23B, 23C, 24, 25A, 25B, 25C, 25D, 26, and 27 are cross-sectional, top, and perspective views of an intermediate stage of fabricating a memory array according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Also, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another (or other) element or component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Various embodiments provide a 3D memory array having a plurality of vertically stacked memory cells. Each memory cell includes a transistor having a word line region serving as a gate electrode, a bit line region serving as a first source/drain electrode, and a source line region serving as a second source/drain electrode. Each transistor further includes a Ferroelectric (FE) gate dielectric layer and an Oxide Semiconductor (OS) channel region. The FE gate dielectric layer, the OS channel region, the bit line region, and the source line region may be formed in a groove formed in the word line region. The upper and lower regions of the recess may have tapered sidewalls whose widths narrow in a direction toward a substrate over which the 3D memory array is formed, while the middle region of the recess has sidewalls whose widths are substantially constant. Dummy memory layers may be formed in the top and bottom layers of the 3D memory array adjacent to the tapered sidewalls, which reduces non-uniformities in the 3D memory array, reduces device defects, and improves device performance. The word line regions in the middle region may be connected to the conductive contacts such that functional memory devices are formed, while the word line regions (e.g., dummy memory layers) in the upper and lower regions are not connected to the conductive contacts and thus do not include functional memory devices.

Fig. 1A and 1B illustrate an example of a memory array 200 according to some embodiments. FIG. 1A shows an example of a portion of a memory array 200 in a three-dimensional view, while FIG. 1B shows a circuit diagram of the memory array 200. The memory array 200 includes a plurality of memory cells 202, which may be arranged in a grid of rows and columns. Memory cells 202 may further be vertically stacked to provide a three-dimensional memory array, thereby increasing device density. The memory array 200 may be arranged in a back end of line (BEOL) of a semiconductor die. For example, the memory array 200 may be arranged in an interconnect layer of a semiconductor die, such as over one or more active devices (e.g., transistors) formed on a semiconductor substrate.

In some embodiments, memory array 200 is a flash memory array, such as a NOR flash memory array or the like. Each memory cell 202 may include a transistor 204 having a Ferroelectric (FE) material 90. FE material 90 may be used as a gate dielectric. In some embodiments, the gate of each of the transistors 204 is electrically coupled to a respective word line (e.g., conductive line 72), the first source/drain region of each of the transistors 204 is electrically coupled to a respective bit line (e.g., conductive line 106), and the second source/drain region of each of the transistors 204 is electrically coupled to a respective source line (e.g., conductive line 108). A respective source line may electrically couple each of the second source/drain regions to ground. Memory cells 202 in the same horizontal row of memory array 200 may share a common word line, while memory cells 202 in the same vertical column of memory array 200 may share a common source line and a common bit line.

The memory array 200 includes a plurality of vertically stacked conductive lines 72 (e.g., word lines), with the dielectric layer 52 disposed between adjacent conductive lines 72. The conductive lines 72 extend in a direction parallel to a major surface of an underlying substrate (not separately shown in fig. 1A and 1B). The conductive lines 72 may have a stair-step configuration such that the lower conductive lines 72 are longer than the ends of the upper conductive lines 72 and extend laterally beyond the ends of the upper conductive lines 72. For example, in fig. 1A, a plurality of stacked layers of conductive lines 72 are shown, with the topmost conductive line 72 being the shortest and the bottommost conductive line 72 being the longest. The respective lengths of the conductive lines 72 may increase in a direction toward the underlying substrate. In this manner, a portion of each conductive line 72 may be accessed from above the memory array 200, and conductive contact may be made to the exposed portion of each conductive line 72.

The memory array 200 also includes a plurality of conductive lines 106 (e.g., bit lines) and a plurality of conductive lines 108 (e.g., source lines). Conductive lines 106 and 108 may each extend in a direction perpendicular to conductive lines 72. The second dielectric material 102 is disposed and isolated between adjacent ones of the conductive lines 106 and 108. The conductive lines 106, adjacent conductive lines 108, and intersecting conductive lines 72 define boundaries of each of the memory cells 202, and the first dielectric material 98 is disposed between and isolates adjacent memory cells 202. In some embodiments, the conductive line 108 is electrically coupled to ground. Although fig. 1A shows a particular placement of the conductive lines 106 relative to the conductive lines 108, it should be appreciated that the placement of the conductive lines 106 and 108 may be reversed.

Memory array 200 may also include an oxide halfA conductor (OS) layer 92. OS layer 92 may provide a channel region for transistor 204 of memory cell 202. For example, when an appropriate voltage (e.g., greater than the threshold voltage (V) of transistor 204) is applied through the corresponding conductive line 72_th) Voltage of) may be applied to the transistor 204, the region of the corresponding OS layer 92 adjacent to the conductive line 72 may allow current to flow from the corresponding conductive line 106 to the corresponding conductive line 108 (e.g., in the direction shown by arrow 206).

FE material 90 is disposed between conductive line 72 and OS layer 92. FE material 90 may provide a gate dielectric for transistor 204. Thus, memory array 200 may also be referred to as a ferroelectric random access memory (FERAM) array. The FE material 90 may be polarized in one of two different directions. The polarization direction of the FE material 90 can be changed by applying an appropriate voltage difference across the FE material 90 and generating an appropriate electric field. The polarization may be relatively local (e.g., typically contained within the boundaries of each of the memory cells 202), and the FE material 90 may extend continuously across multiple memory cells 202. The threshold voltage of a particular transistor 204 varies according to the polarization direction of the corresponding region of FE material 90. As such, a digital value (e.g., 0 or 1) may be stored in the transistor 204 according to the polarization direction of the corresponding region of the FE material 90. For example, when a region of FE material 90 has a first electrical polarization direction, the corresponding transistor 204 may have a relatively lower threshold voltage and when a region of FE material 90 has a second electrical polarization direction, the corresponding transistor 204 may have a relatively higher threshold voltage. The difference between the two threshold voltages may be referred to as a threshold voltage shift. A larger threshold voltage shift makes it easier (e.g., less prone to error) to read the digital value stored in the corresponding memory cell 202.

To perform a write operation on memory cell 202, a write voltage is applied across a region of FE material 90 corresponding to memory cell 202. The write voltage may be applied, for example, by applying appropriate voltages to the corresponding conductive line 72 (e.g., the corresponding word line), the corresponding conductive line 106 (e.g., the corresponding bit line), and the corresponding conductive line 108 (e.g., the corresponding source line). The polarization direction of a region of FE material 90 can be changed by applying a write voltage across the region of FE material 90. As a result, the threshold voltage of the corresponding transistor 204 switches from a low threshold voltage to a high threshold voltage, or from a high threshold voltage to a low threshold voltage, and a digital value may be stored in the memory cell 202. Because the conductive lines 72 extend in a direction perpendicular to the conductive lines 106 and 108, individual memory cells 202 may be selected for write operations.

To perform a read operation on memory cell 202, a read voltage (e.g., a voltage between a low threshold voltage and a high threshold voltage) is applied to a corresponding conductive line 72 (e.g., a corresponding word line). Depending on the polarization direction of the corresponding region of FE material 90, transistor 204 of memory cell 202 may be turned on or off. As a result, the conductive line 106 may or may not discharge through the conductive line 108 (e.g., a source line that may be coupled to ground) and a digital value stored in the memory cell 202 may be determined. Because the conductive lines 72 extend in a direction perpendicular to the conductive lines 106 and 108, individual memory cells 202 may be selected for read operations.

FIG. 1A further illustrates a reference cross section of a memory array 200 used in subsequent figures. The cross-section a-a' is along the longitudinal axis of the conductive line 72 and in a direction, for example, parallel to the direction of current flow through the OS layer 92 of the transistor 204. Section B-B 'is perpendicular to section a-a', the longitudinal axis of conductive line 72, and the longitudinal axes of conductive line 106 and conductive line 106. Section B-B' extends through first dielectric material 98 and second dielectric material 102. Section C-C 'is parallel to section B-B' and extends through conductive line 106. For clarity, the subsequent figures refer to these reference sections.

Fig. 2-27 are views of intermediate stages in the manufacture of a memory array 200 according to some embodiments. Fig. 15 to 22, 23A, 24, 25A, 26 and 27 are shown along the reference section a-a' shown in fig. 1. Fig. 2 to 9, 10B, 11B, 12B, 13B, 14B, 23B and 25B are shown along a reference section B-B' shown in fig. 1. Fig. 13C, 14C and 23C and 25C are shown along the reference section C-C' shown in fig. 1. Fig. 10A, 11A, 12A, 13A, and 14A show plan views. Fig. 25D shows a perspective view.

In fig. 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with p-type or n-type dopants) or undoped. Substrate 50 may be a wafer, such as a silicon wafer. Typically, SOI substrates include a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a Buried Oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of substrate 50 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium phosphide and/or gallium indium arsenide phosphide; or a combination thereof.

Fig. 2 further illustrates circuitry that may be formed over substrate 50. The circuit includes transistors at the top surface of the substrate 50. The transistor may include a gate dielectric layer 302 over the top surface of the substrate 50 and a gate electrode 304 over the gate dielectric layer 302. Source/drain regions 306 are disposed in substrate 50 on opposite sides of gate dielectric layer 302 and gate electrode 304. Gate spacers 308 are formed along sidewalls of gate dielectric layer 302 and separate source/drain regions 306 from gate electrode 304 by an appropriate lateral distance. The transistors may include fin field effect transistors (finfets), nano (e.g., nanosheets, nanowires, omni-directional gates, etc.) FETs (nanofets), planar FETs, etc., or combinations thereof, and may be formed by a gate-first process or a gate-last process.

The first ILD 310 surrounds and isolates the source/drain regions 306, the gate dielectric layer 302, and the gate electrode 304, and the second ILD 312 is above the first ILD 310. A source/drain contact 314 extends through the second ILD 312 and the first ILD 310 and is electrically coupled to the source/drain region 306, and a gate contact 316 extends through the second ILD 312 and is electrically coupled to the gate electrode 304. An interconnect structure 320, including over the second ILD 312, the source/drain contacts 314, and the gate contact 316, the interconnect structure 320 including one or more stacked dielectric layers 324 and conductive features 322 formed in the one or more dielectric layers 324. The interconnect structure 320 may be electrically connected to the gate contact 316 and the source/drain contact 314 to form a functional circuit. In some embodiments, the functional circuitry formed by interconnect structure 320 may include logic circuitry, memory circuitry, sense amplifiers, controllers, input/output circuitry, image sensor circuitry, and the like, or combinations thereof. Although fig. 2 discusses transistors formed over substrate 50, other active devices (e.g., diodes, etc.) and/or passive devices (e.g., capacitors, resistors, etc.) may also be formed as part of the functional circuitry.

In fig. 3, a multi-layer stack 58 is formed over the structure of fig. 2. The substrate 50, transistors, ILD, and interconnect structure 320 may be omitted from subsequent figures for simplicity and clarity. Although the multi-layer stack 58 is shown contacting the dielectric layer 324 of the interconnect structure 320, any number of intervening layers may be disposed between the substrate 50 and the multi-layer stack 58. For example, one or more interconnect layers including conductive features in insulating layers (e.g., low-k dielectric layers) may be disposed between the substrate 50 and the multi-layer stack 58. In some embodiments, the conductive features may be patterned to provide power, ground, and/or signal lines to the substrate 50 and/or active devices on the memory array 200 (see fig. 1A and 1B).

Multilayer stack 58 includes alternating layers of dielectric layers 52A-52K (collectively, dielectric layers 52) and conductive layers 54A-54K (collectively, conductive layers 54). The conductive layer 54 may be patterned in a subsequent step to define conductive lines 72 (e.g., word lines). Conductive layer 54 may comprise a conductive material such as copper, titanium nitride, tantalum nitride, tungsten, ruthenium, aluminum, combinations thereof, and the like, and dielectric layer 52 may comprise an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, and the like. Conductive layer 54 and dielectric layer 52 may each be formed using, for example, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), plasma enhanced CVD (pecvd), or the like. Although fig. 3 shows a particular number of conductive layers 54 and dielectric layers 52, other embodiments may include a different number of conductive layers 54 and dielectric layers 52.

In fig. 4, a hard mask 80 is deposited over the multi-layer stack 58, and a first patterned mask 82, such as a patterned photoresist, is formed on the hard mask 80. The hard mask 80 may comprise, for example, silicon nitride, silicon oxynitride, etc., which may be deposited by CVD, PVD, ALD, PECVD, etc. The first patterned mask 82 may be formed by depositing a photosensitive layer over the hard mask 80 using spin coating or the like. The photosensitive layer can then be patterned by exposing the photosensitive layer to a patterned energy source (e.g., a patterned light source) and developing the photosensitive layer to remove exposed or unexposed portions of the second photosensitive layer, thereby forming a first patterned mask 82.

In fig. 5, a first opening 86 is formed in the hard mask 80. The pattern of the first patterned mask 82 may be transferred to the hard mask 80 using a suitable etching process such as wet or dry etching, Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), or a combination thereof. Suitable etching processes may be anisotropic. After forming the first opening 86 in the hard mask 80, the first patterned mask 82 may be removed by a suitable process such as an ashing process, a stripping process, or the like, or a combination thereof.

In fig. 6, a first opening 86 extends through the multi-layer stack 58. The pattern of hard mask 80 may be transferred to multilayer stack 58 using one or more suitable etching processes, such as wet or dry etching, RIE, NBE, or combinations thereof. Suitable etching processes may be anisotropic. The first openings 86 divide the conductive layers 54A-54K into conductive lines 72A-72K (e.g., word lines, collectively conductive lines 72). For example, adjacent conductive lines 72 may be separated from each other by etching first openings 86 through conductive layer 54.

As shown in fig. 6, the etching process used to form the first opening 86 may form a portion of the first opening 86 with tapered sidewalls. For example, the portions of the first opening 86 adjacent to the conductive lines 72A, 72J, and 72K and the dielectric layers 52A, 52B, 52J, and 52K may have tapered sidewalls, while the portions of the first opening 86 adjacent to the conductive lines 72B-72I and the dielectric layers 52C-52I may have substantially vertical sidewalls. Forming the channel region in the portion of the first opening 86 having tapered sidewalls may cause the characteristics (e.g., threshold voltage, etc.) of the channel region to vary and reliability to be reduced, which may cause device defects in subsequently formed transistors and memory cells. As such, dummy transistors (e.g., non-functional devices) may be subsequently formed in the portions of the first openings 86 having tapered sidewalls to reduce device defects in the resulting devices, while forming functional transistors in the portions of the first openings 86 having vertical sidewalls.

Fig. 7-10B illustrate the formation and patterning of a channel region for the transistor 204 (see fig. 1A) in the first opening 86. Fig. 7 to 9 and 10B illustrate a reference section B-B' shown in fig. 1A. Fig. 10A shows a top view.

In fig. 7, the hard mask 80 is removed and the FE material 90, OS layer 92 and first dielectric layer 98A are deposited in the first opening 86. The hard mask 80 may be removed by a suitable process such as a wet etch process, a dry etch process, a planarization process, combinations thereof, and the like.

FE material 90 may be conformally deposited in first opening 86 along the sidewalls of conductive line 72 and dielectric layer 52 and along conductive line 72K and the top surface of substrate 50. The FE material 90 can comprise a material that is capable of switching between two different polarization directions by applying an appropriate voltage difference across the FE material 90. For example, the FE material 90 may be a high-k dielectric material, such as a hafnium-based (Hf) dielectric material. In some embodiments, FE material 90 comprises hafnium oxide, hafnium zirconium oxide, hafnium silicon-doped oxide, and the like. In some embodiments, the FE material 90 may be included in two SiO_xSiN between layers_xA multi-layer structure of layers (e.g., an ONO structure). In some embodiments, FE material 90 may comprise a different ferroelectric material or a different type of memory material. The FE material 90 may be deposited by CVD, PVD, ALD, PECVD, etc.

An OS layer 92 is conformally deposited in the first opening 86 over the FE material 90. OS layer 92 comprises a material suitable for providing a channel region for transistor 204 (see fig. 1A). For example, the OS layer 92 may include zinc oxide (ZnO), indium tungsten oxide (InWO), indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), Indium Tin Oxide (ITO), combinations thereof, and the like. OS layer 92 may be deposited by CVD, PVD, ALD, PECVD, and the like. The OS layer 92 may extend over the FE material 90 along the sidewalls and bottom surface of the first opening 86.

A first dielectric layer 98A is deposited in the first opening 86 over the OS layer 92. The first dielectric layer 98A may comprise, for example, silicon oxide, silicon nitride, silicon oxynitride, etc., which may be deposited by CVD, PVD, ALD, PECVD, etc. A first dielectric layer 98A may extend over the OS layer 92 along sidewalls and a bottom surface of the first opening 86.

In fig. 8, the bottom portions of the first dielectric layer 98A and the OS layer 92 in the first opening 86 are removed. In some embodiments, a bottom portion of the first dielectric layer 98A may be removed using a suitable photolithography and etching process. The etch may be any suitable etch process, such as wet or dry etch, RIE, NBE, or the like, or combinations thereof. Suitable etching processes may be anisotropic.

The first dielectric layer 98A may then be used as a mask to etch the bottom portion of the OS layer 92 in the first opening 86. The bottom portion of OS layer 92 may be etched by any suitable etching process, such as wet or dry etching, RIE, NBE, or the like, or combinations thereof. Suitable etching processes may be anisotropic. Etching the OS layer 92 may expose portions of the FE material 90 on the bottom surface of the first opening 86. Accordingly, the portions of the OS layer 92 on opposite sidewalls of the first opening 86 may be separated from each other, which improves isolation between the memory cells 202 of the memory array 200 (see fig. 1A).

In fig. 9, an additional dielectric material 98B is deposited over the first dielectric layer 98A and fills the remaining portion of the first opening 86. The additional dielectric material 98B may be formed from the same or similar materials and processes as the first dielectric layer 98A. The additional dielectric material 98B and the first dielectric layer 98A may be collectively referred to as a first dielectric material 98.

In fig. 10A and 10B, the top surfaces of the first dielectric material 98, the OS layer 92, the FE material 90, and the conductive line 72K are planarized by a suitable planarization process. Suitable planarization processes may be Chemical Mechanical Polishing (CMP), etch back processes, combinations thereof, and the like. As shown in fig. 10B, a suitable planarization process exposes the multi-layer stack 58 such that the top surface of the multi-layer stack 58 (e.g., the top surface of the conductive line 72K), the first dielectric material 98, the OS layer 92FE material 90 are horizontal after the appropriate planarization process is complete.

Fig. 11A-14C illustrate intermediate steps in fabricating conductive lines 106 and 108 (e.g., source lines and bit lines) in the memory array 200. The conductive lines 106 and 108 may extend in a direction perpendicular to the conductive line 72 so that individual cells of the memory array 200 may be selected for read and write operations. Fig. 11A, 12A, 13A, and 14A show plan views. Fig. 11B, 12B, 13B, and 14B illustrate a reference section B-B' shown in fig. 1A. Fig. 13C and 14C illustrate a reference section C-C' shown in fig. 1A.

In fig. 11A and 11B, the second opening 100 is patterned by the first dielectric material 98 and the OS layer 92. The second opening 100 may be patterned in the first dielectric material 98 and the OS layer 92 using suitable photolithography and etching processes. The etching process may be any acceptable etching process, such as by wet or dry etching, RIE, NBE, or the like, or combinations thereof. The etching process may be anisotropic. The second opening 100 may be disposed between opposing sidewalls of the FE material 90 and may expose sidewalls and a bottom surface of the FE material 90. The second opening 100 may physically separate adjacent stacks of memory cells 202 in the memory array 200 (see fig. 1A).

In fig. 12A and 12B, a second dielectric material 102 is deposited in the second opening 100 and fills the second opening 100. The second dielectric material 102 may comprise, for example, silicon oxide, silicon nitride, silicon oxynitride, etc., which may be deposited by CVD, PVD, ALD, PECVD, etc. The second dielectric material 102 may extend along the sidewalls and bottom surface of the second opening 100 over the FE material 90. After depositing the second dielectric material 102, a suitable planarization process (e.g., CMP, etchback, etc.) may be performed to remove excess portions of the second dielectric material 102. As shown in fig. 12B, after the planarization process, the top surface of the multi-layer stack 58, the FE material 90, the OS layer 92, the first dielectric material 98, and the second dielectric material 102 may be substantially horizontal (e.g., within process variations).

In some embodiments, the materials of the first and second dielectric materials 98, 102 may be selected such that the first and second dielectric materials 98, 102 may be selectively etched with respect to each other. For example, in some embodiments, the first dielectric material 98 is an oxide and the second dielectric material 102 is a nitride. In some embodiments, the first dielectric material 98 is a nitride and the second dielectric material 102 is an oxide. Other materials are also possible.

In fig. 13A-13C, the third opening 104 is patterned through the first dielectric material 98. The third opening 104 may be patterned through the first dielectric material 98 using a suitable photolithography and etching process. The etching process may be any acceptable etching process, such as by wet or dry etching, RIE, NBE, or the like, or combinations thereof. The etching process may be anisotropic. The etching process may use an etchant that etches the first dielectric material 98 without significantly etching the second dielectric material 102, the OS layer 92, and the FE material 90. The pattern of the third opening 104 may correspond to a pattern of subsequently formed conductive lines (such as the conductive lines 106 and 108 discussed below with reference to fig. 14A-14C). In some embodiments, a portion of the first dielectric material 98 may remain between each pair of third openings 104, and the second dielectric material 102 may be disposed between adjacent pairs of the third openings 104.

In fig. 14A to 14C, the third opening 104 is filled with a conductive material to form a conductive line 106 and a conductive line 108. The conductive lines 106 and 108 may comprise a conductive material such as copper, titanium nitride, tantalum nitride, tungsten, ruthenium, aluminum, combinations thereof, and the like, which may be formed using, for example, CVD, ALD, PVD, PECVD, and the like. After depositing the conductive material, a suitable planarization process (e.g., CMP, etchback, etc.) may be performed to remove excess portions of the conductive material, thereby forming conductive lines 106 and 108. As shown in fig. 14B and 14C, the top surface of the multi-layer stack 58, the FE material 90, the OS layer 92, the first dielectric material 98, the second dielectric material 102, the conductive line 106, the conductive line 108 may be substantially horizontal (e.g., within process variations) after the planarization process.

The conductive line 106 may correspond to a bit line in the memory array 200, while the conductive line 108 may correspond to a source line in the memory array 200. Further, the conductive lines 106 and 108 may provide source/drain electrodes for the transistors 204 in the memory array 200. Although fig. 14C is a cross-sectional view showing only the conductive line 106, the cross-sectional view of the conductive line 108 may be similar.

Fig. 15-22 are views of intermediate stages in the fabrication of a staircase structure of memory array 200, according to some embodiments. Fig. 15 to 22 show a reference section a-a' shown in fig. 1A. Although the stair-step structure is discussed as being formed after forming the channel regions for the transistor 204, the conductive line 106, and the conductive line 108, in some embodiments the stair-step structure may be formed before forming the channel regions for the transistor 204, the conductive line 106, and the conductive line 108. For example, the step structure may be patterned prior to the fabrication steps described in fig. 4-14C. The same or similar process may be used for the pre-stair step and the post-stair step embodiments.

In fig. 15, a second patterned mask 56, such as a patterned photoresist, is formed over the multi-layer stack 58 and the portions of the multi-layer stack 58 exposed by the second patterned mask 56 are etched. The second patterned mask 56 may be formed by depositing a photosensitive layer over the multi-layer stack 58 using spin coating or the like. The photosensitive layer can then be patterned by exposing the photosensitive layer to a patterned energy source (e.g., a patterned light source) and developing the photosensitive layer to remove exposed or unexposed portions of the second photosensitive layer, thereby forming a second patterned mask 56. The second patterned mask 56 may be patterned to cover portions of the multi-layer stack 58, wherein portions of the FE material 90, the OS layer 92, the first dielectric material 98, the second dielectric material 102, the conductive line 106, and the conductive line 108 are formed such that these portions are protected during the fabrication of the stair step structure.

The exposed portions of the multi-layer stack 58 may then be etched using the second patterned mask 56 as a mask. The etch may be any suitable etch process, such as wet or dry etch, RIE, NBE, or the like, or combinations thereof. The etching process may be anisotropic. The etching process may remove portions of the conductive lines 72K, 72J, and 72I and the dielectric layers 52K, 52J, and 52I in the region 60 to define the fourth opening 61. Because the conductive lines 72 and the dielectric layer 52 have different material compositions, the etchant used to remove the exposed portions of these layers may be different. In some embodiments, the dielectric layer 52 serves as an etch stop while the conductive line 72 is etched, and the conductive line 72 serves as an etch stop while the dielectric layer 52 is etched. As a result, portions of the conductive lines 72 and the dielectric layer 52 may be selectively removed without removing the remaining layers of the multi-layer stack 58, and the fourth opening 61 may extend to a desired depth. Alternatively, after the fourth opening 61 reaches a desired depth, a timed etch process may be used to stop etching the fourth opening 61. In the resulting structure, conductive line 72H is exposed in region 60.

In fig. 16, second patterned mask 56 is trimmed to expose other portions of multilayer stack 58. Second patterned mask 56 may be trimmed using acceptable photolithographic techniques. As a result of trimming, the width of second patterned mask 56 is reduced and portions of multi-layer stack 58 in regions 60 and 62 are exposed. For example, the top surfaces of conductive lines 72K in region 62 and the top surfaces of conductive lines 72H in region 60 may be exposed.

The exposed portions of the multi-layer stack 58 may then be etched using the second patterned mask 56 as a mask. The etch may be any suitable etch process, such as wet or dry etch, RIE, NBE, or the like, or combinations thereof. The etching process may be anisotropic. The etching may extend the fourth opening 61 further into the multi-layer stack 58. Because the conductive lines 72 and the dielectric layer 52 have different material compositions, the etchant used to remove the exposed portions of these layers may be different. In some embodiments, the dielectric layer 52 serves as an etch stop while the conductive line 72 is etched, and the conductive line 72 serves as an etch stop while the dielectric layer 52 is etched. As a result, portions of the conductive lines 72 and the dielectric layer 52 may be selectively removed without removing the remaining layers of the multi-layer stack 58, and the fourth opening 61 may extend to a desired depth. Alternatively, after the fourth opening 61 reaches a desired depth, a timed etch process may be used to stop etching the fourth opening 61. Further, during the etching process, the unetched portions of the conductive lines 72 and the dielectric layers 52 serve as a mask for the underlying layers, and as a result, the previous patterns of the conductive lines 72K, 72J, and 72I and the dielectric layers 52K, 52J, and 52I (see fig. 15) can be transferred to the underlying conductive lines 72H and the underlying dielectric layers 52H. In the resulting structure, conductive line 72J is exposed in region 62, while conductive line 72G is exposed in region 60.

In fig. 17, second patterned mask 56 is trimmed to expose other portions of multilayer stack 58. Second patterned mask 56 may be trimmed using acceptable photolithographic techniques. As a result of the trimming, the width of second patterned mask 56 is reduced and portions of multi-layer stack 58 in regions 60, 62, and 63 are exposed. For example, the top surfaces of conductive line 72K in region 63, the top surfaces of conductive line 72J in region 62, and the top surfaces of conductive line 72G in region 60 may be exposed.

The exposed portions of the multi-layer stack 58 may then be etched using the second patterned mask 56 as a mask. The etch may be any suitable etch process, such as wet or dry etch, RIE, NBE, or the like, or combinations thereof. The etching process may be anisotropic. The etching may extend the fourth opening 61 further into the multi-layer stack 58. Because the conductive lines 72 and the dielectric layer 52 have different material compositions, the etchant used to remove the exposed portions of these layers may be different. In some embodiments, the dielectric layer 52 serves as an etch stop while the conductive line 72 is etched, and the conductive line 72 serves as an etch stop while the dielectric layer 52 is etched. As a result, portions of the conductive lines 72 and the dielectric layer 52 may be selectively removed without removing the remaining layers of the multi-layer stack 58, and the fourth opening 61 may extend to a desired depth. Alternatively, after the fourth opening 61 reaches a desired depth, a timed etch process may be used to stop etching the fourth opening 61. Further, during the etching process, the unetched portions of the conductive lines 72 and the dielectric layers 52 serve as a mask for the underlying layers, and as a result, the previous patterns of the conductive lines 72K-72H and the dielectric layers 52K-52H (see fig. 16) may be transferred to the underlying conductive lines 72J and 72G and the underlying dielectric layers 52J and 52G. In the resulting structure, conductive line 72J is exposed in region 63, conductive line 72I is exposed in region 62, and conductive line 72F is exposed in region 60.

In fig. 18, second patterned mask 56 is trimmed to expose other portions of multilayer stack 58. Second patterned mask 56 may be trimmed using acceptable photolithographic techniques. As a result of the trimming, the width of second patterned mask 56 is reduced and portions of multi-layer stack 58 in regions 60, 62, 63, and 64 are exposed. For example, the top surfaces of conductive line 72K in region 64, conductive line 72J in region 63, conductive line 72I in region 62, and conductive line 72F in region 60 may be exposed.

The exposed portions of the multi-layer stack 58 may then be etched using the second patterned mask 56 as a mask. The etch may be any suitable etch process, such as wet or dry etch, RIE, NBE, or the like, or combinations thereof. The etching process may be anisotropic. The etching may extend the fourth opening 61 further into the multi-layer stack 58. Because the conductive lines 72 and the dielectric layer 52 have different material compositions, the etchant used to remove the exposed portions of these layers may be different. In some embodiments, the dielectric layer 52 serves as an etch stop while the conductive line 72 is etched, and the conductive line 72 serves as an etch stop while the dielectric layer 52 is etched. As a result, portions of the conductive lines 72 and the dielectric layer 52 may be selectively removed without removing the remaining layers of the multi-layer stack 58, and the fourth opening 61 may extend to a desired depth. Alternatively, after the fourth opening 61 reaches a desired depth, a timed etch process may be used to stop etching the fourth opening 61. Further, during the etching process, the unetched portions of the conductive lines 72 and the dielectric layers 52 serve as a mask for the underlying layers, and as a result, the previous patterns of the conductive lines 72K-72G and the dielectric layers 52K-52G (see fig. 17) may be transferred to the underlying conductive lines 72J, 72I, and 72F and the underlying dielectric layers 52J, 52I, and 52F. In the resulting structure, conductive line 72J is exposed in region 64, conductive line 72I is exposed in region 63, conductive line 72H is exposed in region 62, and conductive line 72E is exposed in region 60.

In fig. 19, second patterned mask 56 is trimmed to expose other portions of multilayer stack 58. Second patterned mask 56 may be trimmed using acceptable photolithographic techniques. As a result of the trimming, the width of second patterned mask 56 is reduced and portions of multi-layer stack 58 in regions 60, 62, 63, 64, and 65 are exposed. For example, the top surfaces of conductive line 72K in region 65, the top surfaces of conductive line 72J in region 64, the top surfaces of conductive line 72I in region 63, the top surfaces of conductive line 72H in region 62, and the top surfaces of conductive line 72E in region 60 may be exposed.

The exposed portions of the multi-layer stack 58 may then be etched using the second patterned mask 56 as a mask. The etch may be any suitable etch process, such as wet or dry etch, RIE, NBE, or the like, or combinations thereof. The etching process may be anisotropic. The etching may extend the fourth opening 61 further into the multi-layer stack 58. Because the conductive lines 72 and the dielectric layer 52 have different material compositions, the etchant used to remove the exposed portions of these layers may be different. In some embodiments, the dielectric layer 52 serves as an etch stop while the conductive line 72 is etched, and the conductive line 72 serves as an etch stop while the dielectric layer 52 is etched. As a result, portions of the conductive lines 72 and the dielectric layer 52 may be selectively removed without removing the remaining layers of the multi-layer stack 58, and the fourth opening 61 may extend to a desired depth. Alternatively, after the fourth opening 61 reaches a desired depth, a timed etch process may be used to stop etching the fourth opening 61. Further, during the etching process, the unetched portions of the conductive lines 72 and the dielectric layers 52 serve as a mask for the underlying layers, and as a result, the previous patterns of the conductive lines 72K-72F and the dielectric layers 52K-52F (see fig. 18) may be transferred to the underlying conductive lines 72J, 72I, 72H, and 72E and the underlying dielectric layers 52J, 52I, 52H, and 52E. In the resulting structure, conductive line 72J is exposed in region 65, conductive line 72I is exposed in region 64, conductive line 72H is exposed in region 63, conductive line 72G is exposed in region 62, and conductive line 72D is exposed in region 60.

In fig. 20, second patterned mask 56 is trimmed to expose other portions of multilayer stack 58. Second patterned mask 56 may be trimmed using acceptable photolithographic techniques. As a result of the trimming, the width of second patterned mask 56 is reduced and portions of multi-layer stack 58 in regions 60, 62, 63, 64, 65, and 66 are exposed. For example, the top surfaces of conductive line 72K in region 66, the top surfaces of conductive line 72J in region 65, the top surfaces of conductive line 72I in region 64, the top surfaces of conductive line 72H in region 63, the top surfaces of conductive line 72G in region 62, and the top surfaces of conductive line 72D in region 60 may be exposed.

The exposed portions of the multi-layer stack 58 may then be etched using the second patterned mask 56 as a mask. The etch may be any suitable etch process, such as wet or dry etch, RIE, NBE, or the like, or combinations thereof. The etching process may be anisotropic. The etching may extend the fourth opening 61 further into the multi-layer stack 58. Because the conductive lines 72 and the dielectric layer 52 have different material compositions, the etchant used to remove the exposed portions of these layers may be different. In some embodiments, the dielectric layer 52 serves as an etch stop while the conductive line 72 is etched, and the conductive line 72 serves as an etch stop while the dielectric layer 52 is etched. As a result, portions of the conductive lines 72 and the dielectric layer 52 may be selectively removed without removing the remaining layers of the multi-layer stack 58, and the fourth opening 61 may extend to a desired depth. Alternatively, after the fourth opening 61 reaches a desired depth, a timed etch process may be used to stop etching the fourth opening 61. Further, during the etching process, the unetched portions of the conductive lines 72 and the dielectric layers 52 serve as a mask for the underlying layers, and as a result, the previous patterns of the conductive lines 72K-72E and the dielectric layers 52K-52E (see fig. 19) may be transferred to the underlying conductive lines 72J, 72I, 72H, 72G, and 72D and the underlying dielectric layers 52J, 52I, 52H, 52G, and 52D. In the resulting structure, conductive line 72J is exposed in region 66, conductive line 72I is exposed in region 65, conductive line 72H is exposed in region 64, conductive line 72G is exposed in region 63, conductive line 72F is exposed in region 62, and conductive line 72C is exposed in region 60.

In fig. 21, second patterned mask 56 is trimmed to expose other portions of multilayer stack 58. Second patterned mask 56 may be trimmed using acceptable photolithographic techniques. As a result of trimming, the width of second patterned mask 56 is reduced and portions of multi-layer stack 58 in regions 60, 62, 63, 64, 65, 66, and 67 are exposed. For example, the top surfaces of conductive line 72K in region 67, the top surfaces of conductive line 72J in region 66, the top surfaces of conductive line 72I in region 65, the top surfaces of conductive line 72H in region 64, the top surfaces of conductive line 72G in region 63, the top surfaces of conductive line 72F in region 62, and the top surfaces of conductive line 72C in region 60 may be exposed.

The exposed portions of the multi-layer stack 58 may then be etched using the second patterned mask 56 as a mask. The etch may be any suitable etch process, such as wet or dry etch, RIE, NBE, or the like, or combinations thereof. The etching process may be anisotropic. The etching may extend the fourth opening 61 further into the multi-layer stack 58. Because the conductive lines 72 and the dielectric layer 52 have different material compositions, the etchant used to remove the exposed portions of these layers may be different. In some embodiments, the dielectric layer 52 serves as an etch stop while the conductive line 72 is etched, and the conductive line 72 serves as an etch stop while the dielectric layer 52 is etched. As a result, portions of the conductive lines 72 and the dielectric layer 52 may be selectively removed without removing the remaining layers of the multi-layer stack 58, and the fourth opening 61 may extend to a desired depth. Alternatively, after the fourth opening 61 reaches a desired depth, a timed etch process may be used to stop etching the fourth opening 61. Further, during the etching process, the unetched portions of the conductive lines 72 and the dielectric layers 52 serve as a mask for the underlying layers, and as a result, the previous patterns of the conductive lines 72K-72D and the dielectric layers 52K-52D (see fig. 20) may be transferred to the underlying conductive lines 72J, 72I, 72H, 72G, 72F, and 72C and the underlying dielectric layers 52J, 52I, 52H, 52G, 52F, and 52C. In the resulting structure, conductive line 72J is exposed in region 67, conductive line 72I is exposed in region 66, conductive line 72H is exposed in region 65, conductive line 72G is exposed in region 64, conductive line 72F is exposed in region 63, conductive line 72E is exposed in region 62, and conductive line 72B is exposed in region 60.

In fig. 22, second patterned mask 56 is trimmed to expose other portions of multilayer stack 58. Second patterned mask 56 may be trimmed using acceptable photolithographic techniques. As a result of trimming, the width of second patterned mask 56 is reduced and portions of multi-layer stack 58 in regions 60, 62, 63, 64, 65, 66, 67, and 68 are exposed. For example, the top surfaces of conductive line 72K in region 68, the top surfaces of conductive line 72J in region 67, the top surfaces of conductive line 72I in region 66, the top surfaces of conductive line 72H in region 65, the top surfaces of conductive line 72G in region 64, the top surfaces of conductive line 72F in region 63, the top surfaces of conductive line 72E in region 62, and the top surfaces of conductive line 72B in region 60 may be exposed.

The exposed portions of the multi-layer stack 58 may then be etched using the second patterned mask 56 as a mask. The etch may be any suitable etch process, such as wet or dry etch, RIE, NBE, or the like, or combinations thereof. The etching process may be anisotropic. The etching may extend the fourth opening 61 further into the multi-layer stack 58. Because the conductive lines 72 and the dielectric layer 52 have different material compositions, the etchant used to remove the exposed portions of these layers may be different. In some embodiments, the dielectric layer 52 serves as an etch stop while the conductive line 72 is etched, and the conductive line 72 serves as an etch stop while the dielectric layer 52 is etched. As a result, portions of the conductive lines 72 and the dielectric layer 52 may be selectively removed without removing the remaining layers of the multi-layer stack 58, and the fourth opening 61 may extend to a desired depth. Alternatively, after the fourth opening 61 reaches a desired depth, a timed etch process may be used to stop etching the fourth opening 61. Further, during the etching process, the unetched portions of the conductive lines 72 and the dielectric layers 52 serve as a mask for the underlying layers, and as a result, the previous patterns of the conductive lines 72K-72C and the dielectric layers 52K-52C (see fig. 21) may be transferred to the underlying conductive lines 72I, 72H, 72G, 72F, 72E, 72D, 72B, and 72A and the underlying dielectric layers 52I, 52H, 52G, 52F, 52E, 52D, 52B, and 52A. In the resulting structure, conductive line 72I is exposed in region 68, conductive line 72H is exposed in region 67, conductive line 72G is exposed in region 66, conductive line 72F is exposed in region 65, conductive line 72E is exposed in region 64, conductive line 72D is exposed in region 63, conductive line 72C is exposed in region 62, and substrate 50 is exposed in region 60.

In fig. 23A-23C, the second patterned mask 56 may be removed, such as by an acceptable ashing or wet strip process. Thus, the stepped structure 69 is formed. The stair-step structure 69 comprises a stack of alternating layers of dielectric layers 52 and conductive lines 72. The lower conductive line 72 is longer and extends laterally beyond the upper conductive line 72. Specifically, conductive line 72C is longer than conductive line 72D, conductive line 72D is longer than conductive line 72E, conductive line 72E is longer than conductive line 72F, conductive line 72F is longer than conductive line 72G, conductive line 72G is longer than conductive line 72H, conductive line 72H is longer than conductive line 72I, and conductive line 72I is longer than conductive lines 72J and 72K. As a result, in a subsequent processing step, a conductive contact may be made to each conductive line 72 from above the stair-step structure 69.

As shown in fig. 23B and 23C, FE material 90, OS layer 92, first dielectric material 98, second dielectric material 102, conductive line 106, and a first portion of conductive line 108 (not separately shown, but may be similar to conductive line 106) are formed near the sidewalls of conductive lines 72K, 72I, and 72A and dielectric layers 52K, 52I, 52B, and 52A, with a tapered profile. This may result in the FE material 90, the OS layer 92, the first dielectric material 98, the second dielectric material 102, the conductive line 106, and the first portion of the conductive line 108 having tapered sidewalls, and may also result in thickness variations in the first portion of the FE material 90, the OS layer 92, the first dielectric material 98, the second dielectric material 102, the conductive line 106, and the conductive line 108, etc. Forming the transistor 204 in the first portion of the FE material 90, the OS layer 92, the first dielectric material 98, the second dielectric material 102, the conductive line 106, and the conductive line 108 having a tapered profile may cause the transistor 204 to have device characteristics (e.g., threshold voltage, etc.) that vary between transistors 204 disposed at different vertical levels of the memory array 200. As such, the conductive lines 72K, 72J, 72B, and 72A may be dummy conductive lines that are not connected to conductive contacts or active devices on the substrate 50 (see, e.g., fig. 3), and the transistors formed in the conductive lines 72K, 72I, 72B, and 72A and the dielectric layers 52K, 52I, 52B, and 52A may be dummy transistors (e.g., non-functional transistors or devices) that are not connected to conductive contacts or active devices on the substrate 50 (see, e.g., fig. 3). Conductive lines 72K and 72J and dielectric layers 52K and 52J may be collectively referred to as top dummy region 100A, and conductive lines 72B and 72A and dielectric layers 52A and 52B may be collectively referred to as bottom dummy region 100C.

As further shown in fig. 23B and 23C, a second portion of FE material 90, OS layer 92, first dielectric material 98, second dielectric material 102, conductive line 106, and conductive line 108 (not separately shown, but may be similar to conductive line 106) is formed adjacent to conductive lines 72B-72I and dielectric layers 52C-52I, with substantially vertical sidewalls. The FE material 90, the OS layer 92, the first dielectric material 98, the second dielectric material 102, the conductive line 106, and the second portion of the conductive line 108 may have vertical sidewalls and a uniform thickness. This results in devices formed in the second portions of FE material 90, OS layer 92, first dielectric material 98, second dielectric material 102, conductive line 106, and conductive line 108 having reduced device characteristic variations as compared to devices formed in the first portions of FE material 90, OS layer 92, first dielectric material 98, second dielectric material 102, conductive line 106, and conductive line 108. As will be discussed in more detail below, conductive contacts extending to conductive lines 72C-72I may be formed such that functional transistors (e.g., transistor 204) and functional memory cells (e.g., memory cell 202) are formed in conductive lines 72C-72I and FE material 90, OS layer 92, first dielectric material 98, second dielectric material 102, conductive line 106, and a second portion of conductive line 108. This may result in transistor 204 and memory cell 202 having reduced device variation, reduced device defects, and improved performance. The conductive lines 72I-72C and the dielectric layers 52I-52C may be collectively referred to as a functional memory cell region 100B. Furthermore, forming conductive lines 72K and 72J having the same length and forming conductive lines 72B and 72A having the same length as conductive line 72C reduces the patterning step required to form stair-step structure 69, thereby reducing production time and cost.

As shown in fig. 23A, the conductive lines 72K and 72J and the dielectric layers 52K and 52J (e.g., the top dummy region 100A) may have a combined thickness T₁The conductive lines 72I-72C and the dielectric layers 52I-52C (e.g., thus, the functional memory cell region 100B) may have a combined thickness T₂And conductive lines 72B and 72A and dielectric layers 52A and 52B (e.g., bottom dummy region 100C) may have a combined thickness T₃. Thickness T₁May range from about 50nm to about 300nmInner, thickness T₂May be in the range of about 500nm to about 5,000nm, and a thickness T₃May be in the range of about 50nm to about 300 nm. In some embodiments, the thickness T₁May be equal to the thickness T₃(ii) a However, in some embodiments, the thickness T₁May be greater or less than the thickness T₃. Thickness T₁And thickness T₂May be in the range of about 0.01 to about 0.6, and the thickness T₃And thickness T₂The ratio of (a) may be in the range of about 0.01 to about 0.6. Although fig. 23A shows two pairs of conductive lines 72 and dielectric layers 52 in the top dummy region 100A, two pairs of conductive lines 72 and dielectric layers 52 in the bottom dummy region 100C, and seven pairs of conductive lines 72 and dielectric layers 52 in the functional memory cell region 100B, any number of pairs of conductive lines 72 and dielectric layers 52 may be included in each of the top dummy region 100A, functional memory cell region 100B, and bottom dummy region 100C. Keeping the thicknesses of the top dummy region 100A, the functional memory cell region 100B, and the bottom dummy region 100C within the above ranges can ensure formation of the memory cell 202 with reduced variation while maintaining the area where the memory cell 202 is formed.

In fig. 24, an inter-metal dielectric (IMD)70 is deposited over the multi-layer stack 58. IMD 70 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma enhanced CVD (pecvd), or flowable CVD (fcvd). The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), Undoped Silicate Glass (USG), and the like. Other isolation materials formed by any acceptable process may be used. As shown in FIG. 24, IMD 70 extends along sidewalls of conductive lines 72A-72K, sidewalls of dielectric layers 52A-52K, and top surfaces of conductive lines 72C-72K.

After deposition of IMD 70, a planarization process is applied to IMD 70. In some embodiments, the planarization process may include CMP, an etch-back process, combinations thereof, and the like. A planarization process may be used to planarize the top surface of IMD 70. In some embodiments (not separately shown), a planarization process may be used to expose the surface of the multi-layer stack 58. For example, a planarization process may be used to expose the surface of conductive line 72K such that the top surface of conductive line 72K is level with the top surface of IMD 70.

In fig. 25A-25D, contacts 110A-110G (collectively referred to as contacts 110) are formed that extend to and are electrically coupled to conductive line 72. Contacts 110 are electrically coupled to conductive lines 72C-72I in functional memory cell region 100B, while no contacts 110 are electrically coupled to conductive lines 72A, 72B, 72J, and 72K in bottom dummy region 100C and top dummy region 100A. As such, conductive lines 72A, 72B, 72J, and 72K may be dummy conductive lines. Further, devices formed in the bottom dummy region 100C and the top dummy region 100A that are not electrically coupled to the contacts 110 may be non-functional devices.

Although not separately shown, the contacts 110 may be electrically coupled to metal lines extending over the IMD 70. The metal lines may extend in a direction parallel to the top surface of IMD 70. Metal lines may be used to interconnect contacts 110 and may provide connections to underlying interconnect structures 320. The metal wires may be arranged in a different cross section from that shown in fig. 25A to 25C. In some embodiments, metal lines may be disposed in IMD 70. The metal lines may be adjacent to the contacts 110 and may be disposed at any height within the IMD 70.

As shown in fig. 25A and 25D, the stepped shape of the conductive lines 72 provides a surface on each conductive line 72 to receive a contact 110. For example, because the length of the respective conductive line 72 increases in a direction toward the underlying substrate, a portion of each underlying conductive line 72 is not covered by an overlying conductive line 72, and the contacts 110 may extend to each conductive line 72. Because the conductive lines 72A, 72B, 72J, and 72K are dummy conductive lines, the conductive lines 72A, 72B, 72J, and 72K may not be patterned in a stair step structure, which saves patterning steps and space in completing the device, thereby reducing cost and increasing device density.

Forming the contacts 110 may include patterning openings in the IMD 70 to expose portions of the conductive lines 72, for example, using a combination of lithography and etching. A liner (not separately shown) such as a diffusion barrier layer, an adhesion layer, or the like and a conductive material are formed in the opening. The liner may comprise titanium, titanium nitride, tantalum nitride, and the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, may be performed to remove excess material from the surface of IMD 70. The remaining liner and conductive material form contacts 110 in the openings. As shown in fig. 25A, the contact 110A may extend to the conductive line 72C, the contact 110B may extend to the conductive line 72D, the contact 110C may extend to the conductive line 72E, the contact 110D may extend to the conductive line 72F, the contact 110E may extend to the conductive line 72G, the contact 110F may extend to the conductive line 72H, and the contact 110G may extend to the conductive line 72I.

In the embodiment shown in fig. 25A, conductive lines 72K, 72J, 72B, and 72A are dummy conductive lines that are not electrically coupled to contacts 110. As previously discussed, the FE material 90, the OS layer 92, the first dielectric material 98, the second dielectric material 102, the conductive line 106, and a first portion of the conductive line 108 (not separately shown, but may be similar to the conductive line 106) extending through the conductive lines 72K, 72J, 72B, and 72A may have a tapered profile. The devices formed in the conductive lines 72K, 72J, 72B, and 72A and the dielectric layers 52K, 52J, 52B, and 52A may be non-functional devices such that devices with variations and defects are not formed in these layers. Forming the memory cells 202 in the conductive lines 72C-72I and the dielectric layers 52C-52I ensures that the formed memory cells 202 have reduced variation, reduced device defects, and improved device performance.

Further in fig. 25A-25D, contacts 112 may be formed to extend to and electrically couple to conductive lines 106 and 108 (not separately shown, but may be similar to conductive lines 106). As shown in fig. 25B and 25C, the contacts 112 may be formed to extend through the IMD 70. The contacts 112 may be formed using the same or similar processes and materials used to form the contacts 110. Contacts 112 may be electrically coupled to metal lines (not separately shown) that extend over IMD 70 in a direction parallel to the top surface of IMD 70. Metal lines may be used to interconnect the conductive lines 106 and 108 and may provide connections to the underlying interconnect structure 320.

Fig. 26 shows an embodiment in which the top dummy region 100A includes only the conductive line 72J and the dielectric layer 52J and omits the conductive line 72K and the dielectric layer 52K. Contacts 110 are electrically coupled to conductive lines 72C-72I in functional memory cell region 100B, while no contacts 110 are electrically coupled to conductive lines 72A, 72B, and 72J in bottom dummy region 100C and top dummy region 100A. As such, conductive lines 72A, 72B, and 72J may be dummy conductive lines.

As shown in fig. 26, the conductive line 72J and the dielectric layer 52J may have a combined thickness T₄Conductive lines 72I-72C and dielectric layers 52I-52C may have a combined thickness T₅And conductive lines 72B and 72A and dielectric layers 52A and 52B may have a combined thickness T₆. Thickness T₄May be in the range of about 50nm to about 300nm, and has a thickness T₅May be in the range of about 500nm to about 5,000nm, and a thickness T₆May be in the range of about 50nm to about 300 nm. Despite the thickness T of the top dummy region 100A₄Is shown as being greater than the thickness T of the bottom dummy region 100C₆But a thickness T₆May be equal to or greater than the thickness T₄. Thickness T₄And thickness T₅May be in the range of about 0.01 to about 0.6, and the thickness T₆And thickness T₅The ratio of (a) may be in the range of about 0.01 to about 0.6. Although fig. 26 shows one pair of conductive lines 72 and dielectric layers 52 in the top dummy region 100A, two pairs of conductive lines 72 and dielectric layers 52 in the bottom dummy region 100C, and seven pairs of conductive lines 72 and dielectric layers 52 in the functional memory cell region 100B, any number of pairs of conductive lines 72 and dielectric layers 52 may be included in each of the top dummy region 100A, functional memory cell region 100B, and bottom dummy region 100C. For example, in some embodiments, the top dummy region 100A may include more conductive line pairs 72 and dielectric layers 52 than the bottom dummy region 100C.

Keeping the thicknesses of the top dummy region 100A, the functional memory cell region 100B, and the bottom dummy region 100C within the above ranges can ensure formation of the memory cell 202 with reduced variation while maintaining the area where the memory cell 202 is formed. Further, the thicknesses of the top dummy region 100A and the bottom dummy region 100C may be set independently of each other based on the height of the tapered portions of the first opening 86 in which the FE material 90, the OS layer 92, the first dielectric material 98, the second dielectric material 102, the conductive line 106, and the conductive line 108 are formed.

Fig. 27 shows an embodiment in which the staircase profile is continuous in the conductive lines 72 and the dielectric layer 52 of the top dummy region 100A and the bottom dummy region 100C. For example, as shown in fig. 27, the lengths of conductive line 72K and dielectric layer 52K may be shorter than the lengths of conductive line 72J and dielectric layer 52J, and the lengths of conductive line 72A and dielectric layer 52A may be greater than the lengths of conductive line 72B and dielectric layer 52B. Contacts 110 are electrically coupled to conductive lines 72C-72I in functional memory cell region 100B, while no contacts 110 are electrically coupled to conductive lines 72A, 72B, 72J, and 72I in bottom dummy region 100C and top dummy region 100A. As such, conductive lines 72A, 72B, 72J, and 72K may be dummy conductive lines.

The thicknesses of the top dummy region 100A, the functional memory cell region 100B, and the bottom dummy region 100C may be the same as or similar to those described above with respect to fig. 23A. Although fig. 27 shows two pairs of conductive lines 72 and dielectric layers 52 in the top dummy region 100A, two pairs of conductive lines 72 and dielectric layers 52 in the bottom dummy region 100C, and seven pairs of conductive lines 72 and dielectric layers 52 in the functional memory cell region 100B, any number of pairs of conductive lines 72 and dielectric layers 52 may be included in each of the top dummy region 100A, functional memory cell region 100B, and bottom dummy region 100C.

Keeping the thicknesses of the top dummy region 100A, the functional memory cell region 100B, and the bottom dummy region 100C within the above ranges can ensure formation of the memory cell 202 with reduced variation while maintaining the area where the memory cell 202 is formed. Continuing the staircase structure into the top and bottom dummy regions 100A and 100C provides greater isolation for the conductive lines 72 in the top and bottom dummy regions 100A and 100C.

Embodiments may achieve various advantages. For example, forming a memory array (which includes dummy regions) adjacent to portions of the conductive lines, FE material, and OS layer having tapered sidewalls and forming active regions adjacent to portions of the conductive lines, FE material, and OS layer having vertical sidewalls reduces variation between memory cells formed in the various layers above the memory array, reduces device defects, and improves performance.

According to an embodiment, a memory array includes a Ferroelectric (FE) material over a semiconductor substrate, the FE material including vertical sidewalls in contact with word lines; an Oxide Semiconductor (OS) layer on the FE material, the OS layer contacting the source line and the bit line, the FE material between the OS layer and the word line; a transistor including a portion of the FE material, a portion of the word line, a portion of the OS layer, a portion of the source line, and a portion of the bit line; and a first dummy word line between the transistor and the semiconductor substrate, the FE material further including a first tapered sidewall contacting the first dummy word line. In an embodiment, the memory array is a second dummy word line over the transistor, the transistor is between the second dummy word line and the semiconductor substrate, the FE material further comprises a second tapered sidewall in contact with the second dummy word line. In an embodiment, a distance between opposing sidewalls of the second tapered sidewall of the FE material decreases in a direction toward the semiconductor substrate. In an embodiment, a distance between opposing sidewalls of the first tapered sidewall of the FE material decreases in a direction toward the semiconductor substrate. In an embodiment, the memory array further comprises a functional memory cell region comprising the word line and the transistor; and a first dummy region between the functional memory cell region and the semiconductor substrate, the first dummy region including the first dummy word line, a ratio of a thickness of the first dummy region in a first direction perpendicular to a main surface of the semiconductor substrate to a thickness of the functional memory cell region in the first direction being 0.01 to 0.6. In an embodiment, the word line has a first length in a second direction parallel to a main surface of the semiconductor substrate, the first dummy word line has a second length in the second direction, and the second length is greater than the first length. In an embodiment, the memory array further comprises a second dummy word line between the first dummy word line and the semiconductor substrate, the second dummy word line having a third length in the second direction equal to the second length.

According to another embodiment, a memory array comprises: one or more lower dummy word lines over the semiconductor substrate; one or more word lines above the lower dummy word line; one or more upper dummy word lines over the word lines; a source line extending through the lower dummy word line, the word line, and the upper dummy word line; bit lines extending through the lower dummy word lines, the word lines, and the upper dummy word lines; and one or more transistors, each of the transistors including a portion of one of the word lines, a portion of the source line, and a portion of the bit line, a width of the upper dummy word line being smaller than a width of the word line, and a length of the upper dummy word line being smaller than a length of the word line. In an embodiment, a width of the word line is smaller than a width of the lower dummy word line, and a length of the word line is smaller than a length of the lower dummy word line. In an embodiment, portions of the bit lines and the source lines extending through the lower dummy word lines and the upper dummy word lines have tapered sidewalls. In an embodiment, portions of the bit lines and the source lines extending through the word lines have vertical sidewalls. In an embodiment, the memory array further comprises: a lower dummy region, a functional memory cell region above the lower dummy region, and an upper dummy region above the functional memory cell region, the lower dummy word line being arranged in the lower dummy region, the word line and the one or more transistors being arranged in the functional memory cell region, the upper dummy word line being arranged in the upper dummy region, a ratio of a first thickness of the lower dummy region to a second thickness of the functional memory cell region being 0.01 to 0.6, and a ratio of a third thickness of the upper dummy region to the second thickness being 0.01 to 0.6. In an embodiment, the lower dummy word line includes a first dummy word line and a second dummy word line, the second dummy word line being farther from the semiconductor substrate than the first dummy word line, a length of the second dummy word line being equal to a length of the first dummy word line. In an embodiment, the lower dummy word line includes a first dummy word line and a second dummy word line, the second dummy word line being farther from the semiconductor substrate than the first dummy word line, a length of the second dummy word line being smaller than a length of the first dummy word line.

According to yet another embodiment, a method comprises: forming a multilayer stack over a semiconductor substrate, the multilayer stack comprising alternating conductive and dielectric layers; patterning a first trench extending through the multilayer stack, a first portion of the first trench proximate the semiconductor substrate having a first tapered sidewall, a second portion of the first trench having a vertical sidewall, a third portion of the first trench distal the semiconductor substrate having a second tapered sidewall, wherein the vertical sidewall extends from the first tapered sidewall to the second tapered sidewall, wherein patterning the first trench defines a bottom dummy word line adjacent the first portion, a word line adjacent the second portion, and a top dummy word line adjacent the third portion. Depositing a Ferroelectric (FE) material along the first tapered sidewalls, the vertical sidewalls, the second tapered sidewalls, and a bottom surface of the first trench; depositing an Oxide Semiconductor (OS) layer over the FE material, wherein a first portion of the OS layer, a first portion of the FE material, and a portion of the bottom dummy word line form one or more dummy transistors, and wherein a second portion of the OS layer, a second portion of the FE material, and a portion of the word line form one or more transistors; patterning the multilayer stack such that the conductive layer and the dielectric layer have a stepped shape in a cross-sectional view; and forming a conductive line electrically coupled to the one or more transistors. In an embodiment, a width between opposing sidewalls of the first tapered sidewall and the second tapered sidewall narrows in a direction toward the semiconductor substrate. In an embodiment, the bottom dummy word line is patterned with a length equal to a length of a bottommost word line of the word lines. In an embodiment, a bottom most word line of the word lines is patterned to a first length, wherein a top most bottom dummy word line of the bottom dummy word lines is patterned to a second length, and wherein a bottom most dummy word line of the bottom dummy word lines is patterned to a third length, the third length being greater than the second length, and the second length being greater than the first length. In an embodiment, a topmost one of the word lines is patterned to a first length, wherein a bottommost top dummy word line of the top dummy word line is patterned to a second length, and wherein a topmost top dummy word line of the top dummy word line is patterned to a third length, the first length being greater than the second length, and the second length being greater than the third length. In an embodiment, the first portion has a first height, wherein the second portion has a second height, wherein the third portion has a third height, wherein a ratio of the first height to the second height is 0.01 to 0.6, and wherein a ratio of the third height to the second height is 0.01 to 0.6.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.