阅读说明：本技术 存储器件及其形成方法 (Memory device and method of forming the same ) 是由 吴昭谊 贾汉中 林佑明 杨世海 于 2021-03-22 设计创作，主要内容包括：提供了一种存储器件及其形成方法。该存储器件包括位于衬底上的第一层和位于第一层上的第二层。第一层包括第一层堆叠件；穿过第一层堆叠件的第一栅电极；第一层堆叠件和第一栅电极之间的第一沟道层；以及第一沟道层和第一栅电极之间的第一铁电层。第二层包括第二层堆叠件；穿过第二层堆叠件的第二栅电极；第二层堆叠件和第二栅电极之间的第二沟道层；以及第二沟道层和第二栅电极之间的第二铁电层。(A memory device and a method of forming the same are provided. The memory device includes a first layer on a substrate and a second layer on the first layer. The first layer comprises a first layer stack; a first gate electrode passing through the first layer stack; a first channel layer between the first layer stack and the first gate electrode; and a first ferroelectric layer between the first channel layer and the first gate electrode. The second layer comprises a second layer stack; a second gate electrode passing through the second layer stack; a second channel layer between the second layer stack and the second gate electrode; and a second ferroelectric layer between the second channel layer and the second gate electrode.)

1. A memory device, comprising:

a first layer disposed on a substrate, wherein the first layer comprises:

a first layer stack;

a first gate electrode passing through the first layer stack;

a first channel layer disposed between the first layer stack and the first gate electrode; and

a first ferroelectric layer disposed between the first channel layer and the first gate electrode; and

a second layer disposed on the first layer, wherein the second layer comprises:

a second layer stack;

a second gate electrode passing through the second layer stack;

a second channel layer disposed between the second layer stack and the second gate electrode; and

a second ferroelectric layer disposed between the second channel layer and the second gate electrode.

2. The memory device of claim 1, wherein the first layer stack comprises:

a first dielectric layer;

a first conductive layer disposed on the first dielectric layer;

a second dielectric layer disposed on the first conductive layer; and

a second conductive layer disposed on the second dielectric layer, wherein the first channel layer is in contact with the first dielectric layer, the first conductive layer, the second dielectric layer, and the second conductive layer.

3. The memory device of claim 2, wherein the first dielectric layer and the first conductive layer have a first width, the second dielectric layer and the second conductive layer have a second width, and the second width is less than the first width.

4. The memory device of claim 2, wherein the second layer stack comprises:

a third conductive layer disposed over the second conductive layer;

a third dielectric layer disposed on the third conductive layer;

a fourth conductive layer disposed on the third dielectric layer; and

a fourth dielectric layer disposed on the fourth conductive layer, wherein the second channel layer is in contact with the third conductive layer, the third dielectric layer, the fourth conductive layer, and the fourth dielectric layer.

5. The memory device of claim 4, wherein the third conductive layer and the third dielectric layer have a third width, the fourth conductive layer and the fourth dielectric layer have a fourth width, and the fourth width is greater than the third width.

6. The memory device of claim 4, wherein the first and fourth conductive layers are connected to a first connection, and the second and third conductive layers are connected to a second connection different from the first connection.

7. The memory device of claim 4, wherein the first gate electrode and the second gate electrode are connected to a third connection.

8. The memory device of claim 2, wherein the second layer stack comprises:

a third dielectric layer disposed over the second conductive layer;

a third conductive layer disposed on the third dielectric layer;

a fourth dielectric layer disposed on the third conductive layer; and

a fourth conductive layer disposed on the fourth dielectric layer, wherein the second channel layer is in contact with the third dielectric layer, the third conductive layer, the fourth dielectric layer, and the fourth conductive layer.

9. A method of forming a memory device, comprising:

forming a first layer stack on a substrate, wherein the first layer stack comprises a first dielectric layer, a first conductive layer, a second dielectric layer and a second conductive layer which are stacked in sequence;

forming a first opening in the first layer stack to pass through the first layer stack;

forming a first gate structure in the first opening;

removing portions of the second conductive layer and the second dielectric layer to expose portions of the first conductive layer to form a stepped region;

forming a second layer stack on the first layer stack, wherein the second layer stack includes a third conductive layer, a third dielectric layer, a fourth conductive layer, and a fourth dielectric layer, which are sequentially stacked;

forming a first electrical path and a second electrical path in the stepped region between the first layer stack and the second layer stack, respectively, wherein the first electrical path is electrically connected to the first conductive layer and the fourth conductive layer, and the second electrical path is electrically connected to the second conductive layer and the third conductive layer;

forming a second opening in the second layer stack to pass through the second layer stack; and

forming a second gate structure in the second layer stack, wherein the second gate structure and the first gate structure are electrically independent from each other.

10. A memory device, comprising:

a layer stack disposed on a substrate, wherein the layer stack includes a first dielectric layer, a first source/drain (S/D) layer, a second dielectric layer, and a second source/drain layer, which are sequentially stacked;

a first conductive pillar passing through the layer stack;

the first ferroelectric layer wraps the first conductive column; and

a first channel layer disposed between the layer stack and the first ferroelectric layer, wherein the first ferroelectric layer is in contact with the first channel layer and the first conductive pillar.

Technical Field

Implementations of the present application relate to memory devices and methods of forming the same.

Background

The semiconductor Integrated Circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of integrated circuits, each of which is smaller and more complex than the previous generation. In the course of IC development, the functional density (i.e., the number of interconnected devices per chip area) has generally increased, while the geometry (i.e., the smallest component (or line) that can be fabricated using the fabrication process) has decreased. Such a scaling down process generally brings the benefits of increased production efficiency and reduced associated costs.

This scaling down also increases the complexity of handling and manufacturing ICs, and similar developments in IC processing and manufacturing are needed to achieve these advantages. For example, three-dimensional (3D) memory devices, such as 3D NOR (NOR) type memory, have been introduced instead of planar memory devices. However, 3D memory devices are not entirely satisfactory in all respects, and other problems arise that should be solved.

Disclosure of Invention

Some embodiments of the present application provide a memory device comprising: a first layer disposed on a substrate, wherein the first layer comprises: a first layer stack; a first gate electrode passing through the first layer stack; a first channel layer disposed between the first layer stack and the first gate electrode; and a first ferroelectric layer disposed between the first channel layer and the first gate electrode; and a second layer disposed on the first layer, wherein the second layer comprises: a second layer stack; a second gate electrode passing through the second layer stack; a second channel layer disposed between the second layer stack and the second gate electrode; and a second ferroelectric layer disposed between the second channel layer and the second gate electrode.

Other embodiments of the present application provide a method of forming a memory device, comprising: forming a first layer stack on a substrate, wherein the first layer stack comprises a first dielectric layer, a first conductive layer, a second dielectric layer and a second conductive layer which are stacked in sequence; forming a first opening in the first layer stack to pass through the first layer stack; forming a first gate structure in the first opening; removing portions of the second conductive layer and the second dielectric layer to expose portions of the first conductive layer to form a stepped region; forming a second layer stack on the first layer stack, wherein the second layer stack includes a third conductive layer, a third dielectric layer, a fourth conductive layer, and a fourth dielectric layer, which are sequentially stacked; forming a first electrical path and a second electrical path in the stepped region between the first layer stack and the second layer stack, respectively, wherein the first electrical path is electrically connected to the first conductive layer and the fourth conductive layer, and the second electrical path is electrically connected to the second conductive layer and the third conductive layer; forming a second opening in the second layer stack to pass through the second layer stack; and forming a second gate structure in the second layer stack, wherein the second gate structure and the first gate structure are electrically independent from each other.

Still other embodiments of the present application provide a memory device comprising: a layer stack disposed on a substrate, wherein the layer stack includes a first dielectric layer, a first source/drain (S/D) layer, a second dielectric layer, and a second source/drain layer, which are sequentially stacked; a first conductive pillar passing through the layer stack; the first ferroelectric layer wraps the first conductive column; and a first channel layer disposed between the layer stack and the first ferroelectric layer, wherein the first ferroelectric layer is in contact with the first channel layer and the first conductive pillar.

Drawings

Aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1 to 6A are sectional views of a method of forming a three-dimensional (3D) memory device according to a first embodiment.

Fig. 6B is a plan view along the cross section I-I' of fig. 6A.

Fig. 7A is a cross-sectional view of a 3D memory device according to a second embodiment.

Fig. 7B is a plan view along the section II-II' of fig. 7A.

Fig. 8 is a cross-sectional view of a 3D memory device according to a third embodiment.

Fig. 9 is a cross-sectional view of a 3D memory device according to a fourth embodiment.

Fig. 10 to 16 are sectional views of a method of forming a 3D memory device according to a fifth embodiment.

Fig. 17 is a sectional view of a 3D memory device according to a sixth embodiment.

Fig. 18 is a sectional view of a 3D memory device according to a seventh embodiment.

FIG. 19 illustrates a flow diagram of a method of forming a 3D memory device according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Further, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatial relational terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein to describe one element or component's relationship to another element or component as illustrated for ease of description. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used therein interpreted accordingly.

According to some embodiments, a three-dimensional (3D) memory device includes a first layer having a plurality of first memory cells and a second layer having a plurality of second memory cells stacked over the first layer. The second memory cell is stacked on the first memory cell, thereby allowing easy modification to increase the number of memory cells in the memory device, thereby increasing memory cell density. In addition, a dielectric material (e.g., isolation structure) is disposed between the first and second memory cells to reduce or eliminate leakage current between two vertically adjacent memory cells, thereby improving device performance.

Fig. 1 to 6A are sectional views of a method of forming a 3D memory device 100 according to a first embodiment. Fig. 6B is a plan view along the cross section I-I' of fig. 6A. The 3D memory device 100 is a 3D memory device having a ferroelectric material, and may be, but is not limited to, a 3D or NOR type memory device.

Referring to fig. 1, in a front end of line (FEOL) process of semiconductor fabrication, a plurality of electronic components 104, such as transistors, resistors, capacitors, inductors, diodes, etc., are formed in a device region of a semiconductor substrate 102. The semiconductor substrate 102 may be a bulk substrate, such as a doped or undoped silicon substrate, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 102 may comprise other semiconductor materials such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or a combination thereof. Other substrates, such as multilayer or gradient substrates, may also be used. Electronic components 104 may be formed in/on semiconductor substrate 102 using any suitable formation method known or used in semiconductor manufacturing.

After forming the electronic components 104, interconnect structures are formed over the semiconductor substrate 102 to connect the electronic components 104 to form functional circuits. The interconnect structure may include a plurality of dielectric layers (e.g., 106, 108) and conductive features 105 (e.g., vias, metal lines) formed in the dielectric layers. In some embodiments, the interconnect structure is formed in a back end of line (BEOL) process of semiconductor manufacturing. The formation of interconnect structures is known in the art and therefore details are not repeated here. To avoid confusion and ease of discussion, in the following discussion, the semiconductor substrate 102, the electronic component 104, and the interconnect structures on the semiconductor substrate 102 are collectively referred to as the substrate 101, and details of the substrate 101 shown in fig. 1 may be omitted in subsequent figures.

Fig. 2 to 6A show further process steps in the BEOL process of forming the 3D memory device 100 according to the first embodiment. Referring now to fig. 2, a layer stack 110 is formed on a substrate 101. In detail, the layer stack 110 may include a dielectric layer 112, a conductive layer 114, a dielectric layer 116, and a conductive layer 118, which are sequentially formed on the substrate 101.

In some embodiments, dielectric layer 112 and dielectric layer 116 may comprise dielectric materials such as organic dielectric materials or inorganic dielectric materials. The organic dielectric material may be a polymer such as Polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), and the like. The inorganic dielectric material may include: nitrides such as silicon nitride and the like; oxides such as silicon oxide; an oxynitride such as silicon oxynitride; phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), the like, or combinations thereof. The dielectric layer 112 may be formed by spin coating, lamination, Chemical Vapor Deposition (CVD), or the like. In some embodiments, dielectric layer 112 and dielectric layer 116 are of the same dielectric material, such as silicon oxide. However, embodiments of the present invention are not so limited, and in other embodiments, the dielectric layers 112 and 116 have different dielectric materials.

In some embodiments, conductive layer 114 and conductive layer 118 may comprise a conductive material, such as a metal. For example, conductive layer 114 and conductive layer 118 can be formed from the same source/drain (S/D) material, such as W, Ru. In this case, the conductive layers 114 and 118 may also be referred to as a first source/drain metal layer 114 and a second source/drain metal layer 118, respectively.

The first source/drain metal layer 114 and the second source/drain metal layer 118 may be formed of an N-type metal or a P-type metal, depending on the type of device being formed (e.g., N-type or P-type). In some embodiments, Sc, Ti, Cr, Ni, Al, etc. are used as the N-type metal used to form the first source/drain metal layer 114 and the second source/drain metal layer 118. In some embodiments, Nb, Pd, Pt, Au, etc. are used as the P-type metal for forming the first source/drain metal layer 114 and the second source/drain metal layer 118. The N-type or P-type metal layer may be formed by a suitable formation method, such as CVD, Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), and the like. In some alternative embodiments, source/drain metal layer 114 and source/drain metal layer 118 have different metal materials.

Next, referring to fig. 3, a plurality of openings 10 are formed in the layer stack 110 to expose the substrate 101. That is, the opening 10 passes through the layer stack 110, and the substrate 101 is exposed at the bottom of the opening 10. In addition, opening 10 exposes sidewalls of dielectric layer 112, dielectric layer 116 and sidewalls of conductive layer 114, conductive layer 118. Note that in the discussion herein, the sidewalls of layer stack 110 include corresponding sidewalls of all of the component layers (e.g., 112, 114, 116, and 118) of the layer stack. For example, the sidewalls of layer stack 110 exposed by opening 10 include the sidewalls of dielectric layer 112 and dielectric layer 116, and the sidewalls of conductive layer 114 and conductive layer 118 exposed by opening 10.

In some embodiments, the opening 10 is formed by an anisotropic etching process, such as a plasma etching process. A mask pattern such as a patterned photoresist layer may be formed on the layer stack 110. Then, an anisotropic etching process may be performed by using the mask pattern as an etching mask to form the opening 10. After the anisotropic etching process is completed, the mask pattern (e.g., the patterned photoresist layer) may be removed by a suitable removal process such as ashing or stripping.

Referring to fig. 4, the channel layer 120 is first formed to cover sidewalls of the opening 10. In some embodiments, the channel layer 120 is formed by depositing a channel material that conformally covers the bottom and sidewalls of the opening 10 and further covers the upper surface of the conductive layer 118; an anisotropic etch process is then performed to remove the channel material at the bottom of opening 10 and on the upper surface of conductive layer 118. In this case, the channel layer 120 may have a rounded or curved top surface adjacent to the conductive layer 118. In some embodiments, the channel layer 120 may have a flat top surface, as shown in fig. 4.

In some embodiments, the channel layer 120 may include a metal oxide such as Indium Gallium Zinc Oxide (IGZO), formed by a suitable formation method such as PVD, CVD, ALD, or the like. Other suitable materials for the channel layer 120 include zinc oxide (ZnO), indium tungsten oxide (IWO), tungsten oxide (WO), tantalum oxide (TaO), and molybdenum oxide (MoO). In an example embodiment, dielectric layer 112 and dielectric layer 116 are formed of SiO₂The conductive layer 114 and the conductive layer 118 are formed of tungsten, and the channel layer 120 is formed of IGZO.

Next, as shown in fig. 4, a ferroelectric layer 122 is formed in the opening 10 to cover the channel layer 120. The ferroelectric layer 122 may include a ferroelectric material such as HZO, HSO, HfSiO, HfLaO, HfO doped with La, Y, Si, or Ge₂、HfZrO₂、ZrO₂Or HfO₂And may be formed by PVD, CVD, ALD, etc. In some embodiments, the ferroelectric layer 122 is formed by depositing a ferroelectric material that conformally covers the channel layer 120, the bottom of the opening 10, and further covers the upper surface of the conductive layer 118; an anisotropic etch process is then performed to remove the ferroelectric material at the bottom of opening 10 and on the upper surface of conductive layer 118. In this case, the ferroelectric layer 122 may have a rounded or curved top surface.

Thereafter, as shown in fig. 4, a conductive material is formed to fill the opening 10. The conductive material may include copper, tungsten, cobalt, aluminum, tungsten nitride, ruthenium, silver, gold, rhodium, molybdenum, nickel, cadmium, zinc, alloys thereof, combinations thereof, and the like, and may be formed by a suitable deposition method, such as CVD, PVD, ALD, electroplating, and the like. After the conductive material is formed, a planarization process, such as a Chemical Mechanical Planarization (CMP) process, may be performed to remove excess portions of the conductive material from the upper surface of conductive layer 118. In this case, the remaining portion of the conductive material in the opening 10 forms a conductive pillar 124 (also referred to as a gate electrode 124).

After forming the conductive pillars 124, as shown in fig. 4, a plurality of gate structures 125 are formed in the openings 10. In detail, each gate structure 125 may include a channel layer 120, a ferroelectric layer 122, and a conductive pillar 124. Ferroelectric layer 122 encapsulates conductive pillars 124. Ferroelectric layer 122 is sandwiched between and in physical contact with channel layer 120 and conductive pillars 124. The channel layer 120 is disposed between the layer stack 110 and the ferroelectric layer 122. That is, the channel layer 120 (or gate structure 125) is surrounded by the dielectric layer 112, the dielectric layer 116, and the conductive layer 114, 118.

Referring to fig. 5, portions of conductive layer 118 and portions of dielectric layer 116 are removed by one or more etching processes (e.g., an anisotropic etching process) using an etch mask, thereby forming stepped region 150. The etch time of each etch process may be adjusted to achieve a different amount (e.g., depth) of etch.

As shown in fig. 5, after the stepped region 150 is formed, a portion of the upper surface of the conductive layer 114 is exposed. In the example of fig. 5, dielectric layer 112 and conductive layer 114 have the same width W1. Dielectric layer 116 and conductive layer 118 have the same width W2 that is less than width W1. That is, conductive layer 118 in stepped region 150 has sidewalls that are aligned along the same line as corresponding sidewalls of dielectric layer 116. In addition, the widths of the conductive layer 114 and the conductive layer 118 each increase in a direction toward the substrate 101, so that the width of the upper conductive layer 118 is smaller than the width of the lower conductive layer 114. The stepped region 150 facilitates access of subsequently formed contacts 128 to the conductive layer 114 (see fig. 6A).

Referring to fig. 6A, a dielectric material 126 is formed on the structure of fig. 5. A plurality of contacts 128 (also referred to as contact plugs) are formed in the dielectric material 126 and electrically coupled to the conductive pillars 124 or conductive layer 114 and conductive layer 118. In some embodiments, the contacts 128 electrically coupled to the conductive pillars 124 are also referred to as gate contacts 128G, and the contacts 128 electrically coupled to the conductive layer 114 and the conductive layer 118 are also referred to as source/drain contacts 128 SD. In some embodiments, the length of source/drain contact 128SD contacting conductive layer 114 is greater than the length of source/drain contact 128SD contacting conductive layer 118.

The dielectric material 126 may include an organic dielectric material or an inorganic dielectric material. The organic dielectric material may be a polymer such as Polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), and the like. The inorganic dielectric material may include: nitrides such as silicon nitride and the like; oxides such as silicon oxide; an oxynitride such as silicon oxynitride; phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), the like, or combinations thereof. The dielectric material 126 may be formed by spin coating, lamination, CVD, or the like. Further, the contacts 128 may be formed by forming openings in the dielectric material 126 to expose underlying conductive features (e.g., 124, 114, or 118), and filling the openings with a conductive material, such as copper, tungsten, cobalt, gold, silver, alloys thereof, combinations thereof, and the like.

Next, a plurality of connections 130 (also referred to as conductive connections or conductive bumps) are formed over the contacts 128 and electrically coupled to the contacts 128. The connections 130 may be solder balls, metal posts, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold technology (ENEPIG) formed bumps, combinations thereof (e.g., metal posts with solder balls attached thereto), and the like. The connection 130 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or a combination thereof. In some embodiments, the connection 130 comprises a eutectic material, and may comprise a solder bump or ball, as examples. The solder may be, for example, lead-based and lead-free solders, such as lead-tin compositions for lead-based solders; a lead-free solder comprising indium antimonide; tin, silver and copper (SAC) components; and other eutectic materials that have a common melting point and form conductive solder connections in electrical applications. The connectors 130 may form a grid, such as a Ball Grid Array (BGA). In some embodiments, a reflow process may be performed, in some embodiments, to impart a partially spherical shape to the connection 130. Alternatively, the connector 130 may include other shapes. The connection 130 may also include a non-spherical conductive connection.

In some embodiments, the connection 130 comprises a metal component (such as a copper post or copper wire) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like, with or without a solder material thereon. The metal posts may be solderless and have substantially vertical sidewalls or tapered sidewalls.

FIG. 6B illustrates the 3D memory device of FIG. 6A but along section I-I' in FIG. 6A. In the cross-sectional view of fig. 6B, the ferroelectric layer 122 wraps around (e.g., surrounds) the conductive pillars 124, and the channel layer 120 wraps around the ferroelectric layer 122. The region to the right of the dotted line 160 corresponds to the stepped region 150 of the 3D memory device 100.

As shown in fig. 6A, a memory cell 140 of the 3D memory device 100 is shown by a dotted line box in fig. 6A. The 3D memory device 100 includes a plurality of such memory cells. Memory cell 140 includes a gate structure 125, as well as conductive layer 114 and conductive layer 118 (hereinafter S/D layer 124), through layer stack 110. The gate structure 125 may include a conductive pillar 124 (hereinafter referred to as a gate electrode 124), a ferroelectric layer 122 wrapping the gate electrode 124, a channel layer 120, and the channel layer 120 between the layer stack 110 and the ferroelectric layer 122. In the illustrated embodiment, since the channel layer 120 is disposed between the S/D layers 114 and 118 of the layer stack 110, each memory cell 140 of the 3D memory device 100 is a transistor having a ferroelectric layer 122. Dashed arrows 145 in fig. 6A illustrate possible current flow directions in the channel layer 120 when the transistor of the memory cell is turned on.

In the example of FIG. 6A, two memory cells are shown side-by-side. To avoid clutter, memory cells other than memory cell 140 are not marked with a dashed box. Memory cell 140 may be programmed (e.g., written to and/or read from) through connection 130 (e.g., connection 130 labeled Vg1, Vs1, and Vd1) electrically coupled to the gates and S/D terminals of the transistors of the memory cell. Similarly, the connections 130 labeled Vg2, Vs1, Vd1 may be used to program another memory cell disposed next to memory cell 140.

In order to perform a write operation on a specific memory cell (e.g., memory cell 140), a write voltage is applied on a portion of ferroelectric layer 122 corresponding to memory cell 140. For example, canThe write voltage is applied by applying a first voltage to the gate electrode 124 of the memory cell 140 (through connection 130 labeled Vg 1) and a second voltage to the S/D layer 114 and S/D118 (through connection 130 labeled Vs1 or Vd 1). The voltage difference between the first voltage and the second voltage sets the polarization direction of the ferroelectric layer 122. V of the corresponding transistor of memory cell 140 according to the polarization direction of ferroelectric layer 122_TThe voltage can be from a low threshold voltage V_LSwitching to a high threshold voltage V_HAnd vice versa. Threshold voltage value (V) of transistor_LOr V_H) May be used to indicate either a bit "0" or "1" stored in the memory cell.

To perform a read operation on memory cell 140, it will be the low threshold voltage V_LAnd a high threshold voltage V_HA read voltage of a voltage in between is applied to the transistor, for example, between the gate electrode 124 and the second S/D layer 118. Depending on the polarization direction of ferroelectric layer 122 (or the threshold voltage of the transistor), the transistor of memory cell 140 may be conductive or non-conductive. As a result, when a voltage is applied, for example, at the first S/D layer 114, current may or may not flow between the first S/D layer 114 and the second S/D layer 118 through the channel layer 120. Thus, the current may be sensed to determine the digital bit stored in the memory cell.

It should be noted that in this embodiment, the gate structure 125 is vertically disposed on the substrate 101 and passes through the layer stack 110 such that the S/D layer 114 and the S/D layer 118 wrap around or surround the gate structure 125, thereby forming a similar Gate All Around (GAA) memory device. In this case, the memory cells are surrounded by the S/D layer 114 and the S/D layer 118 disposed at the same layer, so that the memory cells share the same S/D voltage (Vs1 or Vd1), thereby simplifying the wiring layout of the S/D layer. Further, the memory device of the present embodiment can effectively utilize the area of the chip in the horizontal direction and increase the integration density of the memory device, compared to a planar memory device, thereby contributing to the miniaturization of the chip.

As another example, although the disclosed embodiments illustrate the process of forming S/D layer 114 and S/D layer 118, these embodiments are illustrative and not limiting. In alternative embodiments, the S/D layers 114 and 118 may be formed by a replacement process. Specifically, a layer stack including a first oxide layer, a first nitride layer, a second oxide layer, and a second nitride layer stacked in this order is formed on the substrate 101. An opening 10 is formed in the layer stack to expose the substrate 101. The gate structures 125 are formed in the openings 10, respectively. One or more slits are formed alongside the opening 10 and through the stack of layers. The first and second nitride layers are then replaced with source/drain (S/D) material, such as W, Ru. In some embodiments, the replacement process comprises the steps of: removing the first nitride layer and the second nitride layer by an etching process such as a wet etching process so as to form a plurality of gaps between the first oxide layer and the second oxide layer; and an S/D material is filled in a gap between the first oxide layer and the second oxide layer, thereby forming the S/D layer 114 and the S/D layer 118. Prior to the replacement process, portions of S/D layer 114 and S/D layer 118 are removed to form stepped region 150.

Fig. 7A is a cross-sectional view of a 3D memory device 300 according to a second embodiment. Fig. 7B is a plan view along the section II-II' of fig. 7A. The 3D memory device 200 is similar to the 3D memory device 100 of fig. 6A, but with the additional process of increasing (e.g., doubling) the memory cell density.

In some embodiments, to form the 3D memory device 200, the process steps of fig. 1 to 5 for the 3D memory device 100 are followed. Next, slot-shaped openings are formed in each conductive post 124. The slot-shaped openings extend vertically from the upper surface of the conductive pillars 124 away from the substrate 101 to the lower surface of the conductive pillars 124 facing the substrate 101. The slot-shaped opening extends along, for example, the diameter of the conductive pillar 124 in plan view, and divides the conductive pillar 124 into two separate gate pillars 124A and 124B (hereinafter referred to as gate electrodes). In the example shown in fig. 7B, the slot-shaped opening also extends into the ferroelectric layer 122 and the channel layer 120, and the ferroelectric layer 122 is cut into two separate segments 122A and 122B, and the channel layer 120 is further cut into two separate segments 120A and 120B. That is, the slotted opening cuts the gate structure 125 into two separate portions 125A and 125B.

In addition, as shown in fig. 7A, each of the gate electrodes 124A and 124B has a top portion extending along the upper surface of the ferroelectric layer 122, and thus, the conductive pillar 124A (or the conductive pillar 124B) has an L-shaped cross section. The tops of gate electrodes 124A and 124B allow for more flexibility in selecting the location of connections 130 coupled to the gate electrodes. In some alternative embodiments, the tops of gate electrodes 124A and 124B may be omitted if the widths of gate electrodes 124A and 124B embedded in layer stack 110 are large enough to couple to connectors 130.

Next, as shown in fig. 7A, a dielectric material 127 such as silicon oxide, silicon nitride, or the like is formed to fill the trench-shaped openings. Dielectric material 127 can be referred to as an isolation structure to electrically isolate gate electrode 124A from gate electrode 124B. Thereafter, a dielectric material 126 is formed over conductive layer 118, and contacts 128 are formed in dielectric material 126 to electrically couple to respective underlying conductive features (e.g., gate electrodes 124A/124B or S/D layer 114/118). Next, the connection members 130 are formed on the respective contacts 128 and electrically coupled to the respective contacts 128. Fig. 7B illustrates a cross-sectional view of the 3D memory device 200 of fig. 7A but taken along section II-II' in fig. 7A. In some embodiments, the filling of the slot-shaped opening and the formation of dielectric material 126 are performed together in the same deposition process, and thus, dielectric material 127 filling the slot-shaped opening is the same as dielectric material 126 on conductive layer 118. However, embodiments of the present invention are not limited thereto, and in other embodiments, dielectric material 127 and dielectric material 126 may be formed in different deposition processes and may have different dielectric materials.

Since the dielectric material 127 divides the conductive pillar 124 into two independent, independently controlled (e.g., having different gate voltages) gate electrodes 124A and 124B, the number of memory cells in the 3D memory device 200 is twice that of the 3D memory device 100. Dashed-line box 140A and dashed-line box 140B in fig. 7A show two memory cells formed in the area corresponding to memory cell 140 in fig. 6A. As shown in FIG. 7A, each memory cell 140A/140B is half the size of the memory cell 140 in FIG. 6A. In the example of fig. 7A, there are four connections 130 (labeled Vg1, Vg2, Vg3, and Vg4), each of which is electrically coupled to the gate of a transistor of a memory cell. In addition, there are two connections 130 labeled Vs1 and Vd1, where the two connections 130 are coupled to the S/D layer 114 and the S/D layer 118 of the transistors of the memory cells. Thus, the example of FIG. 7A shows four memory cells, where each memory cell can be programmed by applying appropriate voltages to the gate and S/D terminals of each memory cell' S transistor.

Fig. 8 is a cross-sectional view of a 3D memory device 300 according to a third embodiment.

The 3D memory device 300 is similar to the 3D memory device 100 of fig. 6A, but the connections 130 labeled Vg1 and Vg2 in fig. 6A are replaced by conductive features 136 in the substrate 101. The conductive features 136 may be formed as part of the interconnect structure of the substrate 101. In addition, conductive region 132 is formed in substrate 101, is located below gate electrode 124 (e.g., directly below and in physical contact with gate electrode 124), and is electrically coupled to gate electrode 124. In some embodiments, the conductive region 132 is an epitaxial region comprising epitaxially grown semiconductor material. In some embodiments, conductive region 132 is a doped region, such as a semiconductor region doped with N-type or P-type dopants. Fig. 8 also shows electrical paths 134, such as conductive lines in the substrate 101, connecting the conductive features 136 with the respective conductive regions 132. The electrical paths 134 can be conductive lines in the interconnect structure of the substrate 101. A gate voltage of the 3D memory device 300 is applied to the gate electrode 124 through the conductive member 136.

Fig. 9 is a cross-sectional view of a 3D memory device 400 according to a fourth embodiment.

The 3D memory device 400 is similar to the 3D memory device 300 of fig. 8, but the conductive region 132 is electrically coupled to the connection 138 at the bottom surface of the substrate 101 through another electrical path 135, such as a Through Substrate Via (TSV). Accordingly, the gate voltage of the 3D memory device 400 is applied to the connection 138.

It should be noted that in some embodiments, the gate voltage of the 3D memory device 300 or 400 may be applied from the interconnect structure of the substrate 101, thereby simplifying the wiring layout of the gate electrode. Furthermore, the disclosed embodiments allow for easy modifications to increase the number of memory cells in a memory device, thereby increasing memory cell density. The disclosed method of forming a 3D memory device can be easily integrated into an existing BEOL process, thereby enabling the memory device to be integrated into various semiconductor devices at low production costs.

Fig. 10 to 16 are sectional views of a method of forming a 3D memory device 500 according to a fifth embodiment. The 3D memory device 500 is similar to the 3D memory device 100 of fig. 6A, but with additional processes to increase (e.g., double) the memory cell density.

In some embodiments, to form the 3D memory device 500, the process steps of fig. 1-6A for the 3D memory device 100 are followed. Next, referring to fig. 10, a dielectric material 226A is formed over the structure of fig. 6A. In some embodiments, the dielectric material 226a may include an organic dielectric material or an inorganic dielectric material. The organic dielectric material may be a polymer such as Polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), and the like. The inorganic dielectric material may include: nitrides such as silicon nitride and the like; oxides such as silicon oxide; an oxynitride such as silicon oxynitride; phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), the like, or combinations thereof. The dielectric material 226a may be formed by spin coating, lamination, CVD, or the like.

Referring to fig. 11, a plurality of contacts 228a (also referred to as contact plugs) are formed in dielectric material 226a and electrically coupled to connections 130 labeled Vs1 and Vd 1. In some embodiments, the contact 228a may be formed by forming an opening in the dielectric material 226a to expose the underlying connection 130 labeled Vs1 and Vd1 and filling the opening with a conductive material such as copper, tungsten, cobalt, gold, silver, alloys thereof, combinations thereof, and the like. After forming the conductive material, a planarization process, such as a CMP process, may be performed to remove excess portions of the conductive material from the upper surface of dielectric material 226 a.

Referring to fig. 12, a conductive layer 214 and a dielectric layer 212 are sequentially formed on a dielectric material 226 a. The conductive layer 214 and dielectric layer 212 are then patterned to expose the top surface of the contact 228a, labeled Vd1 in the stepped region 150, while the contact 228a, labeled Vs1, is covered by the conductive layer 214 and dielectric layer 212. The structure, material, and function of the conductive layer 214 and/or the dielectric layer 212 are similar to those of the conductive layer 114 and/or the dielectric layer 112, and have been described in the above embodiments, so the details thereof are omitted here.

Referring to fig. 13, a dielectric material 226b is formed alongside the conductive layer 214 and the dielectric layer 212 and covers the dielectric material 226 a. Contact 228b is formed on contact 228a, and contact 228a is coupled to a connector 130 labeled Vd 1. That is, the contact 228a is elongated to reach the height of the top surface of the dielectric layer 212. Dielectric material 226b and dielectric material 226a may be the same, such as SiO₂The dielectric material of (1). In other words, the dielectric materials 226a and 226b may be referred to as the same dielectric layer or film 226. In addition, the contacts 228a and 228b may have the same metal material such as copper. In other words, the contacts 228a and 228b may be considered identical contact plugs or conductive vias 228. In some embodiments, the length of the contact 228 contacting the connector 130 designated Vd1 is greater than the length of the contact 228a contacting the connector 130 designated Vs 1.

Referring to fig. 14, conductive layer 218 and dielectric layer 216 are sequentially formed on dielectric material 226b and conductive layer 214, thereby forming layer stack 210. Specifically, conductive layer 218 is in physical contact with contact plug 228 connected to connection 130 labeled Vd 1. On the other hand, the conductive layer 214 is in physical contact with the contact 228 connected to the connection 130 labeled Vs 1. In the example of fig. 14, the dielectric layer 212 and the conductive layer 214 have the same width W3. The dielectric layer 216 and the conductive layer 218 have the same width W4 that is greater than the width W3. That is, the conductive layer 214 in the stepped region 150 has sidewalls that are aligned along the same line as corresponding sidewalls of the dielectric layer 212.

The structure, material, and function of the conductive layer 218 and/or the dielectric layer 216 are similar to those of the conductive layer 118 and/or the dielectric layer 116, and have been described in the above embodiments, and thus the details thereof are omitted herein.

Referring to fig. 15, a plurality of gate structures 225 are respectively formed in the plurality of openings 20 passing through the layer stack 210. In detail, each gate structure 225 may include a channel layer 220, a ferroelectric layer 222, and a conductive pillar 224. Ferroelectric layer 222 encapsulates conductive pillars 224. Ferroelectric layer 222 is sandwiched between and in physical contact with channel layer 220 and conductive pillars 224. The channel layer 220 is disposed between the layer stack 210 and the ferroelectric layer 222. That is, the channel layer 220 (or gate structure 225) is surrounded by the dielectric layer 212, the dielectric layer 216, and the conductive layers 214, 218. The structure, material, and function of the channel layer 220, ferroelectric layer 222, and conductive pillars 224 are similar to those of the channel layer 120, ferroelectric layer 122, and conductive pillars 124, and have already been described in the above embodiments, and thus the details are omitted herein.

Referring to fig. 16, a dielectric material 227 is formed over the structure of fig. 15. A plurality of contacts 229 (also referred to as contact plugs) are then formed in the dielectric material 227 and electrically coupled to the conductive posts 224. In some embodiments, the contacts 229 electrically coupled to the conductive pillars 224 are also referred to as gate contacts 229G. Next, a plurality of connections 230 (also referred to as conductive connections or conductive bumps) are formed over the contacts 229 and electrically coupled to the contacts 229. The structures, materials, and functions of the dielectric material 227, the contact 229, and the connection member 230 are similar to those of the dielectric material 126, the contact 128, and the connection member 130, and have been described in the above embodiments, and thus the details are omitted here.

As shown in fig. 16, after the connection 230 is formed, the memory device 500 is completed. In detail, the memory device 500 may include a first layer T1 on the substrate 101 and a second layer T2 stacked over the first layer T1. The first layer T1 may include a first layer stack 110 and a first gate structure 125 passing through the first layer stack 110. The second layer T2 may include a second layer stack 210 and a second gate structure 225 passing through the second layer stack 210. The memory device 500 also includes a first electrical path P1 and a second electrical path P2 in the stepped region 150 between the first layer T1 and the second layer T2. First electrical path P1 is electrically connected to conductive layer 114 and conductive layer 218 and has a first S/D voltage from connection 130 labeled Vd 1. Second electrical path P2 is electrically connected to conductive layer 118 and conductive layer 214 and has a second S/D voltage from connection 130 labeled Vs 1. That is, conductive layer 114 and conductive layer 218 share a first S/D voltage, while conductive layer 118 and conductive layer 214 share a second S/D voltage different from the first S/D voltage.

In addition, a memory cell 240 of the 3D memory device 500 is also shown by a dotted frame in fig. 16. The 3D memory device 500 includes a plurality of such memory cells. The memory cell 240 includes a second gate structure 225 passing through the second layer stack 210, and conductive layers 214 and 218 (hereinafter referred to as S/D layers 224). The second gate structure 225 may include a conductive pillar 224 (hereinafter, referred to as a gate electrode 224), a ferroelectric layer 222 wrapping the gate electrode 224, a channel layer 220, and the channel layer 220 between the second layer stack 210 and the ferroelectric layer 222. Since the channel layer 220 is disposed between the S/D layers 214 and 218 of the second layer stack 210, in the illustrated embodiment, each memory cell 240 of the 3D memory device 500 is a transistor having a ferroelectric layer 222. Dashed arrows 245 in fig. 16 show possible current flow directions in the channel layer 220 when the transistor of the memory cell is turned on.

Since the second layer T2 having the memory cells 240 is stacked over the first layer T1 having the memory cells 140, the number of memory cells in the 3D memory device 500 is twice that of the 3D memory device 100. In the example of FIG. 16, four memory cells are shown. To avoid clutter, memory cells other than memory cell 140 and memory cell 240 are not marked with dashed boxes. Memory cell 140 may be programmed (e.g., written to and/or read from) through connection 130 (e.g., connection 130 labeled Vg1, Vs1, and Vd1) electrically coupled to the gates and S/D terminals of the transistors of the memory cell. Similarly, the connections 130 labeled Vg2, Vs1, Vd1 may be used to program another memory cell disposed next to memory cell 140. Memory cell 240 may be programmed through connection 230 and connection 130, where connection 230 is electrically coupled to the gate terminal of the transistor of the memory cell, such as connection 230 labeled Vg3, and connection 130 is electrically coupled to the S/D terminal of the transistor of the memory cell, such as connection 130 labeled Vs1 and Vd 1. Similarly, connection 230 labeled Vg2 and connection 130 labeled Vs1, Vd1 may be used to program other memory cells disposed next to memory cell 240. In some embodiments, gate structure 125 and gate structure 225 are electrically independent of each other, making wiring layout and operation more flexible.

It should be noted that in the present embodiment, memory cell 240 is stacked on memory cell 140 to allow easy modification to increase the number of memory cells in the memory device, thereby increasing memory cell density. In addition, dielectric material 226a is disposed between memory cell 140 and memory cell 240 to reduce or eliminate leakage current between two vertically adjacent memory cells 140 and 240, thereby improving device performance. As another example, while the disclosed embodiments show two layers T1 and T2 above the substrate 101, these embodiments are illustrative and not limiting. Those skilled in the art will readily appreciate that more than two layers may be formed over the substrate 101. This will allow more memory cells to be formed in the 3D memory device.

Fig. 17 is a cross-sectional view of a 3D memory device 600 according to a sixth embodiment.

The 3D memory device 600 is similar to the 3D memory device 500 of fig. 16, i.e., the structure, materials, and functions of the 3D memory device 600 are similar to those of the 3D memory device 500 and have been described in the above-described embodiments, and thus the details thereof are omitted herein. The main difference between the 3D memory devices 500 and 600 is that the gate structure 225 and the gate structure 125 share the same gate voltage (Vg1 or Vg2) through the third electrical path P3 between the memory cells 140 and 240, thereby simplifying circuit complexity.

Fig. 18 is a cross-sectional view of a 3D memory device 700 according to a seventh embodiment.

The 3D memory device 700 is similar to the 3D memory device 500 of fig. 16, i.e., the structure, materials, and functions of the 3D memory device 700 are similar to those of the 3D memory device 500 and have been described in the above-described embodiments, and thus the details thereof are omitted herein. The main difference between the 3D memory devices 500 and 700 is that the conductive layer 114, the conductive layer 118, the conductive layer 214, and the conductive layer 218 of the memory device 700 are electrically independent of each other.

Specifically, the memory device 700 includes a second layer T2 stacked over the first layer T1. Second layer T2 ' may include a second layer stack 210 ', second layer stack 210 ' including a dielectric layer 212, a conductive layer 214, a dielectric layer 216, and a conductive layer 218 sequentially formed on dielectric material 226 a. In the example of fig. 18, the dielectric layer 212 and the conductive layer 214 have the same width W5. The dielectric layer 216 and the conductive layer 218 have the same width W6 that is less than the width W5. That is, the conductive layer 218 in the stepped region 150 has sidewalls that are aligned along the same line as corresponding sidewalls of the dielectric layer 216. The second gate structure 225 passes through the second layer stack 210'. A dielectric material 227 is formed over the second layer stack 210' and the second gate structure 225. Contacts 229 are formed in the dielectric material 227 and are electrically coupled to the conductive posts 224 or conductive layer 214 and conductive layer 218. In some embodiments, the contacts 229 electrically coupled to the conductive pillars 224 are also referred to as gate contacts 229G, and the contacts 229 electrically coupled to the conductive layer 214 and the conductive layer 218 (hereinafter referred to as the S/D layer) are also referred to as source/drain contacts 229 SD. The connection 230 is formed over the contact 229 and electrically coupled with the contact 229.

In the example of fig. 18, there are four connections 130 and 230 (labeled Vg1, Vg2, Vg3, and Vg4), each of which is electrically coupled to the gate of a transistor of a memory cell. In addition, there are two connections 130 labeled Vs1 and Vd1, where the two connections 130 are coupled to the S/D layer 114 and the S/D layer 118 of the transistors of the memory cells. In addition, there are two connections 230 labeled Vs2 and Vd2, where the two connections 230 are coupled to the S/D layers 214 and 218 of the transistors of the memory cells. Thus, the example of FIG. 18 shows four memory cells, where each memory cell can be programmed by applying appropriate voltages to the gate and S/D terminal of each memory cell' S transistor.

Note that although only two layers T1 and T2' are shown in fig. 18, embodiments of the present invention are not limited thereto. In other embodiments, more than two layers may be formed over the substrate 101. This will allow more memory cells to be formed in the 3D memory device. The disclosed method of forming a 3D memory device can be easily integrated into an existing BEOL process, thereby enabling the memory device to be integrated into various semiconductor devices at low production costs.

In addition, the first layer T1 of the 3D memory devices 500, 600, and 700 may be replaced by the structure 400 shown in fig. 9. In this case, another layer or layer stack may be stacked under the bottom surface of the substrate 101, thereby increasing memory cell density.

Fig. 19 illustrates a flow diagram 1000 of a method of forming a memory device according to some embodiments. It should be understood that the embodiment method shown in FIG. 19 is merely exemplary of many possible embodiment methods. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, various steps shown in FIG. 19 may be added, removed, substituted, rearranged, or repeated.

Referring to fig. 19, at block 1010, a first layer stack is formed on a substrate, wherein the first layer stack includes a first dielectric layer, a first conductive layer, a second dielectric layer, and a second conductive layer sequentially stacked. At block 1020, a first opening is formed in the first layer stack to pass through the first layer stack. At block 1030, a first gate structure is formed in the first opening. At block 1040, a portion of the second conductive layer and a portion of the second dielectric layer are removed to expose a portion of the first conductive layer, thereby forming a stepped region. At block 1050, a second layer stack is formed on the first layer stack, wherein the second layer stack includes a third conductive layer, a third dielectric layer, a fourth conductive layer, and a fourth dielectric layer, which are sequentially stacked. At block 1060, a first electrical path electrically connected to the first conductive layer and the fourth conductive layer and a second electrical path electrically connected to the second conductive layer and the third conductive layer are formed in the stepped region between the first layer stack and the second layer stack, respectively. At block 1070, a second opening is formed in the second layer stack to pass through the second layer stack. At block 1080, a second gate structure is formed in the second layer stack, wherein the second gate structure and the first gate structure are electrically independent from each other.

According to one embodiment, a memory device includes a first layer on a substrate and a second layer on the first layer. The first layer comprises a first layer stack; a first gate electrode passing through the first layer stack; a first channel layer between the first layer stack and the first gate electrode; and a first ferroelectric layer between the first channel layer and the first gate electrode. The second layer comprises a second layer stack; a second gate electrode passing through the second layer stack; a second channel layer between the second layer stack and the second gate electrode; and a second ferroelectric layer between the second channel layer and the second gate electrode.

In some embodiments, the first layer stack comprises: a first dielectric layer; a first conductive layer disposed on the first dielectric layer; a second dielectric layer disposed on the first conductive layer; and a second conductive layer disposed on the second dielectric layer, wherein the first channel layer is in contact with the first dielectric layer, the first conductive layer, the second dielectric layer, and the second conductive layer. In some embodiments, the first dielectric layer and the first conductive layer have a first width, the second dielectric layer and the second conductive layer have a second width, and the second width is less than the first width. In some embodiments, the second layer stack comprises: a third conductive layer disposed over the second conductive layer; a third dielectric layer disposed on the third conductive layer; a fourth conductive layer disposed on the third dielectric layer; and a fourth dielectric layer disposed on the fourth conductive layer, wherein the second channel layer is in contact with the third conductive layer, the third dielectric layer, the fourth conductive layer, and the fourth dielectric layer. In some embodiments, the third conductive layer and the third dielectric layer have a third width, the fourth conductive layer and the fourth dielectric layer have a fourth width, and the fourth width is greater than the third width. In some embodiments, the first and fourth conductive layers are connected to a first connector, and the second and third conductive layers are connected to a second connector different from the first connector. In some embodiments, the first gate electrode and the second gate electrode are connected to a third connection. In some embodiments, the second layer stack comprises: a third dielectric layer disposed over the second conductive layer; a third conductive layer disposed on the third dielectric layer; a fourth dielectric layer disposed on the third conductive layer; and a fourth conductive layer disposed on the fourth dielectric layer, wherein the second channel layer is in contact with the third dielectric layer, the third conductive layer, the fourth dielectric layer, and the fourth conductive layer. In some embodiments, the third conductive layer and the third dielectric layer have a third width, the fourth conductive layer and the fourth dielectric layer have a fourth width, and the fourth width is less than the third width. In some embodiments, the first, second, third, and fourth conductive layers are electrically independent of each other.

According to an embodiment, a method of forming a memory device includes: forming a first layer stack on a substrate, wherein the first layer stack comprises a first dielectric layer, a first conductive layer, a second dielectric layer and a second conductive layer which are stacked in sequence; forming a first opening in the first layer stack to pass through the first layer stack; forming a first gate structure in the first opening; removing portions of the second conductive layer and the second dielectric layer to expose portions of the first conductive layer to form a stepped region; forming a second layer stack on the first layer stack, wherein the second layer stack includes a third conductive layer, a third dielectric layer, a fourth conductive layer, and a fourth dielectric layer, which are sequentially stacked; forming a first electrical path and a second electrical path in the stepped region between the first layer stack and the second layer stack, respectively, wherein the first electrical path is electrically connected to the first conductive layer and the fourth conductive layer, and the second electrical path is electrically connected to the second conductive layer and the third conductive layer; forming a second opening in the second layer stack to pass through the second layer stack; and forming a second gate structure in the second layer stack, wherein the second gate structure and the first gate structure are electrically independent from each other.

In some embodiments, the forming the first gate structure comprises: forming a first channel layer on sidewalls of the first opening, wherein the first conductive layer and the second conductive layer surround the first channel layer and are in physical contact with the first channel layer; forming a first ferroelectric layer on the first channel; and filling the first opening with a conductive material to form a first gate electrode. In some embodiments, forming the second gate structure comprises: forming a second channel layer on sidewalls of the second opening, wherein the third conductive layer and the fourth conductive layer surround and are in physical contact with the second channel layer; forming a second ferroelectric layer on the second channel; and filling the second opening with a conductive material to form a second gate electrode. In some embodiments, the first electrical path comprises a first contact plug in physical contact with the first conductive layer, the second electrical path comprises a second contact plug in physical contact with the second conductive layer, and the length of the first contact plug is greater than the length of the second contact plug. In some embodiments, the second electrical path includes a third contact plug in physical contact with the third conductive layer, the first electrical path includes a fourth contact plug in physical contact with the fourth conductive layer, and a length of the fourth contact plug is greater than a length of the third contact plug.

According to an embodiment, a memory device includes: a layer stack disposed on the substrate, wherein the layer stack includes a first dielectric layer, a first source/drain layer, a second dielectric layer, and a second source/drain layer, which are sequentially stacked; a first conductive pillar through the layer stack; a first ferroelectric layer wrapping the first conductive pillar; and a first channel layer between the first ferroelectric layers, wherein the first ferroelectric layers are in contact with the first channel layer and the first conductive pillars.

In some embodiments, portions of the first source/drain layer are exposed by the second dielectric layer and the second source/drain layer to form a stepped region. In some embodiments, the memory device further comprises: a first contact plug disposed on the first source/drain layer in the stepped region; a second contact plug disposed on the second source/drain layer in the stepped region, wherein a length of the first contact plug is greater than a length of the second contact plug; a second conductive pillar disposed alongside the first conductive pillar and through the layer stack; the second ferroelectric layer wraps the second conductive column; and a second channel layer disposed between the layer stack and the second ferroelectric layer, wherein the second ferroelectric layer is in contact with the second channel layer and the second conductive pillar, and the first conductive pillar and the second conductive pillar are electrically independent from each other. In some embodiments, the memory device further comprises: and the isolation structure is embedded in the first conductive column so as to divide the first conductive column into two grid poles. In some embodiments, the memory device further comprises: a conductive region disposed in the substrate under the first conductive pillar, wherein the conductive region is in contact with a bottom surface of the first conductive pillar; a connector disposed in or on a bottom surface of the substrate; and an electrical path electrically connected to the conductive region and the connector.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.