阅读说明：本技术 时钟门控系统和设备 (Clock gating system and apparatus ) 是由 马修·贝尔津什 拉利特库马尔·莫塔吉 希亚姆·阿加瓦尔 于 2020-03-12 设计创作，主要内容包括：提供一种时钟门控系统和设备。根据一个总体方面,一种设备可包括：锁存器电路,被配置为部分地根据状态或至少一个使能信号,将时钟信号传送为输出信号。锁存器电路可包括：通过时钟信号和一个或多个使能信号控制的输入级。锁存器电路可包括：被配置为产生输出信号的输出级。输入级和输出级可共享通过时钟信号控制的公共晶体管。(A clock gating system and apparatus are provided. According to one general aspect, an apparatus may comprise: a latch circuit configured to transfer the clock signal as an output signal based in part on the state or the at least one enable signal. The latch circuit may include: an input stage controlled by a clock signal and one or more enable signals. The latch circuit may include: an output stage configured to generate an output signal. The input stage and the output stage may share a common transistor controlled by a clock signal.)

1. A clock gating apparatus comprising:

a latch circuit configured to transfer the clock signal as an output signal based in part on a state of at least one enable signal, wherein the latch circuit comprises:

an input stage controlled by a clock signal and the at least one enable signal, an

An output stage configured to generate an output signal, an

Wherein the input stage and the output stage share a common transistor controlled by a clock signal.

2. The clock gating apparatus of claim 1, wherein the output stage comprises a common transistor and a second transistor, both controlled by the clock signal and connected in series to reduce leakage current from the output stage.

3. The clock gating apparatus of claim 1, wherein the latch circuit further comprises a feedback circuit having an inverter, wherein the inverter is powered by the output signal.

4. The clock gating apparatus of claim 3, wherein an output of the inverter is configured to: the high voltage is only present when the clock signal is at the high voltage and the at least one enable signal is active.

5. The clock gating apparatus of claim 3, wherein the inverter is configured to: power down based at least in part on the at least one enable signal.

6. The clock gating apparatus of claim 1 wherein the output stage comprises a precharge circuit controlled by the clock signal.

7. The clock gating apparatus of claim 1, wherein the latch circuit is configured to: there is no full transition from the high power rail to the low power rail when the at least one enable signal indicates that the output signal should be disabled.

8. The clock gating apparatus of claim 1, wherein the at least one enable signal comprises a power mode enable signal and a test mode enable signal, and

wherein the latch circuit further comprises an enable circuit configured to: a boolean or of the power mode enable signal and the test mode enable signal is generated as a combined enable signal.

9. The clock gating apparatus of claim 1 wherein the latch circuit accepts as input only a single clock signal, wherein the clock signal is not inverted and is directly connected to the gate terminal of the latch circuit transistor.

10. A clock gating apparatus comprising:

a latch circuit configured to transfer the clock signal as an output signal based in part on a state of at least one enable signal, wherein the latch circuit comprises:

a feedback circuit configured to hold the output signal, wherein the feedback circuit includes an inverter powered by the output signal.

11. The clock gating apparatus of claim 10, wherein the latch circuit further comprises:

an input stage controlled by a clock signal and the at least one enable signal, an

An output stage configured to generate an output signal, an

Wherein the input stage and the output stage share a common transistor controlled by a clock signal.

12. The clock gating apparatus of claim 11, wherein the output stage comprises a common transistor and a second transistor, both controlled by the clock signal and connected in series to reduce leakage current from the output stage.

13. The clock gating apparatus of claim 10, wherein an output of the inverter is configured to: the first voltage is present only when the clock signal is at the first voltage and the at least one enable signal is active.

14. The clock gating apparatus of claim 10, wherein the inverter is configured to: power down based at least in part on the at least one enable signal.

15. The clock gating apparatus of claim 10, wherein the latch circuit is configured to: there is no full transition from the high power rail to the low power rail when the at least one enable signal indicates that the output signal should be disabled.

16. The clock gating apparatus of claim 10, wherein the at least one enable signal comprises a power mode enable signal and a test mode enable signal, and

wherein the latch circuit further comprises an enable circuit configured to: a boolean or of the power mode enable signal and the test mode enable signal is generated as a combined enable signal.

17. The clock gating apparatus of claim 10 wherein the latch circuit accepts as input only a single clock signal, wherein the clock signal is not inverted and is directly connected to the gate terminal of the latch circuit transistor.

18. A clock gating system comprising:

a clock generator circuit configured to generate a first clock signal;

a clock gater circuit configured to receive as inputs a first clock signal and at least one enable signal and to generate a second clock signal; and

logic circuitry configured to perform a synchronized logic function at least in part by a second clock signal; and is

Wherein, clock gate controller circuit includes:

an input stage controlled by a first clock signal and the at least one enable signal, an

An output stage configured to generate a second clock signal, an

Wherein the input stage and the output stage share a common transistor controlled by a first clock signal.

19. The clock gating system of claim 18, wherein the clock gater circuit further comprises: a feedback circuit having an inverter, wherein the inverter is powered by the second clock signal.

20. The clock gating system of claim 18, wherein the clock gater circuit is configured to: when the at least one enable signal indicates that the second clock signal should be disabled, there is no full transition from the high power rail to the low power rail.

Technical Field

The present description relates to clock management and, more particularly, to a low power integrated clock gating system and method.

Background

Clock gating is a popular technique used in many synchronous circuits for reducing dynamic power consumption. Clock gating saves power by adding more logic to the circuit to prune the clock tree. Trimming portions of the clock disable circuit so that the flip-flops in them do not have to switch states. Switching states consumes power. When switching is not performed, switching power consumption becomes zero, and only leakage current is caused.

In an electronic device, a flip-flop is a circuit that has two stable states and can be used to store state information. The flip-flop is a flip-flop. The circuit may be caused to change state by a signal applied to one or more control inputs and may have one or two outputs. This is the basic storage element in sequential logic. Flip-flops and latches are basic building blocks of digital electronic systems used in computers, communications, and many other types of systems.

Disclosure of Invention

According to one general aspect, an apparatus may include a latch circuit configured to transfer a clock signal as an output signal based in part on a state of at least one enable signal. The latch circuit may include an input stage controlled by a clock signal and one or more enable signals. The latch circuit may include an output stage configured to generate an output signal. The input stage and the output stage may share a common transistor controlled by a clock signal.

According to another general aspect, an apparatus may include a latch circuit configured to transfer a clock signal as an output signal based in part on a state of at least one enable signal. The latch circuit may include a feedback circuit configured to hold the output signal. The feedback circuit may include an inverter powered by the output signal.

According to another general aspect, a system may include a clock generator circuit configured to generate a first clock signal. The system may include a clock gater circuit configured to receive as inputs a first clock signal and at least one enable signal and to generate a second clock signal. The system may include logic circuitry configured to perform the synchronized logic function at least in part by the second clock signal. The clock gater circuit may include an input stage controlled by a first clock signal and one or more enable signals. The clock gater circuit may include an output stage configured to generate the second clock signal. The input stage and the output stage may share a common transistor controlled by the first clock signal.

The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features will be apparent from the description and drawings, and from the claims.

A system and/or method for clock management, and more particularly to a low power integrated clock gating system and method, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.

Drawings

Fig. 1 is a block diagram of an example embodiment of a system in accordance with the disclosed subject matter.

Fig. 2A, 2B, and 2C are circuit diagrams of example embodiments of systems according to the disclosed subject matter.

Fig. 3 is a circuit diagram of an example embodiment of a system according to the disclosed subject matter.

Fig. 4A, 4B, 4C, and 4D are circuit diagrams of example embodiments of systems according to the disclosed subject matter.

FIG. 5 is a schematic block diagram of an information handling system that may include devices formed in accordance with the principles of the disclosed subject matter.

Like reference symbols in the various drawings indicate like elements.

Detailed Description

Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some example embodiments are shown. The subject matter of the present disclosure may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the subject matter of the disclosure to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity.

It will be understood that when an element or layer is referred to as being "on," "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. Like numbers refer to like elements throughout. As used herein, the term "and/or" includes any and all combinations of any one or more of the associated listed items.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the presently disclosed subject matter.

Spatially relative terms, such as "below … …," "below … …," "below," "above … …," "above," and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures for ease of description. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below … …" can encompass both an orientation of above and below. The device may be otherwise positioned (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Likewise, for ease of description, electrical terms such as "high," "low," "pull-up," "pull-down," "1," "0," and the like may be used herein to describe voltage levels or currents relative to other voltage levels or relative to additional elements or features as illustrated in the figures. It will be understood that the electrically relative terms are intended to encompass different reference voltages of the device in use or operation in addition to the voltages or currents depicted in the figures. For example, if a device or signal in the figures is inverted or other reference voltage, current, or charge is used, then an element described as "high" or "pull-up" will subsequently be "low" or "pull-down" compared to the new reference voltage or current. Thus, the exemplary term "high" may encompass both a relatively low or relatively high voltage or current. The device may additionally be based on a different electrical frame of reference and the electrical relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the subject matter of the present disclosure. As used herein, the singular is intended to include the plural unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized example embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface where the implantation occurs. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the presently disclosed subject matter.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the presently disclosed subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Hereinafter, example embodiments will be explained in detail with reference to the accompanying drawings.

Fig. 1 is a block diagram of an example embodiment of a system 100 in accordance with the disclosed subject matter. In various embodiments, the system 100 may include computing devices such as processors, systems on a chip (SoC), laptop computers, desktop computers, workstations, personal digital assistants, smart phones, tablet computers, and other suitable computers or their virtual machines or virtual computing devices.

In the illustrated embodiment, the system 100 may include a clock generator circuit 102 configured to generate a clock signal. The clock signal may then be distributed throughout the system 100. In various embodiments, this may involve a grid or tree structure.

In the illustrated embodiment, the system 100 may include a plurality of Integrated Clock Gaters (ICGs) (or latch circuits) or clock gater circuits (e.g., circuits 104A, 104B, and 104C). In various embodiments, these ICGs may be configured to stop or block clock signals based on one or more enable signals (not shown).

In the illustrated embodiment, the system 100 may include one or more logic circuits (e.g., circuits 106A, 106B, and 106C) configured to perform tasks. In various embodiments, these logic circuits may include execution units (e.g., load/store units, arithmetic logic units, floating point units, etc.), blocks of Functional Units (FUBs), Combinational Logic Blocks (CLBs), or sub-portions thereof. According to an example embodiment, the logic circuit may perform a synchronized logic function based at least in part on the clock signal output by the integrated clock gater.

As described above, in various embodiments, an ICG may be configured to turn off the clock of the logic circuit (and thus turn off the switches and power consumption). In various embodiments, these ICGs may be integrated into, or may be integrated as part of, various integrated circuits.

In various embodiments, the ICG may also be configured to shape and gate the clock signal. Traditionally, ICG architectures have used additional gates in the critical timing path to accomplish the desired timing adjustments. As shown in later figures, in the illustrated embodiment, the ICG does not include additional gates in the critical timing path.

Fig. 2A, 2B, and 2C are circuit diagrams of example embodiments of a circuit or system 200 according to the disclosed subject matter. Fig. 2A, 2B, and 2C highlight various aspects of system 200 because a single view of these aspects may appear overly cluttered. In various embodiments, as described above, the system 200 may include an Integrated Clock Gater (ICG).

In various embodiments, the system 200 may be configured to transfer the clock signal CLK 297 as the enable clock signal ECK or the inverted enable clock signal ECKN295 based on the (inverted) enable signal EN 296. In such embodiments, CLK signal 297 may be freely (in inverted form) passed as ECKN295 when enable signal EN 296 is active (e.g., low). Conversely, when the enable signal EN 296 is inactive (e.g., high), the enable clock ECKN295 may remain at a stable value (e.g., high). As mentioned above, this may have the effect of: any logic circuitry that depends on the enable clock ECKN295 is powered down for synchronization.

In the illustrated embodiment, system 200 may be powered by power rails (power rail) VDD 299 and VSS 298. In various embodiments, system 200 may utilize Complementary Metal Oxide Semiconductor (CMOS) technology, which uses two power supplies: a high voltage (VDD 299) and a low voltage or ground (VSS 298).

In the illustrated embodiment, the circuit 200 may include P-type metal oxide semiconductor (PMOS) transistors 210, 211, 214, 216, 219, 220. The circuit 200 may include N-type metal oxide semiconductor (NMOS) transistors 212, 213, 215, 217, 218, and 221. In various embodiments, a MOS transistor may include a source terminal, a drain terminal, and a gate terminal.

In the illustrated embodiment, transistors 210, 211, 212, and 213 may include input stage 202 (highlighted in FIG. 2B). These transistors may be connected in series between VDD 299 and VSS 298. Transistor 210 may be controlled by its gate terminal or connected to CLK signal 297 via its gate terminal. The transistors 211 and 212 may be controlled by an enable signal EN 296. The transistor 213 may be controlled by the output signal or the inverted enable clock 295.

In the illustrated embodiment, the transistors 210, 219, 216, 217, and 218 may include an output stage 204 (highlighted in fig. 2B). These transistors may be connected in series between VDD 299 and VSS 298. Transistors 210 and 219 may be controlled by their gate terminals or connected to CLK signal 297 via their gate terminals. The transistors 216 and 217 may be controlled by a feedback node or signal 294. Transistors 219, 217, and 218 may at least partially generate an output signal or inverted enable clock 295.

In the illustrated embodiment, the transistors 214, 215, 218, 220, and 221 may include the feedback circuit 206 (highlighted in fig. 2C). Transistors 214, 215, and 218 may be connected in series between VDD 299 and VSS 298. Similarly, transistors 220 and 221 may be connected in series between inverted enable clock 295 and VSS 298.

Transistors 220 and 221 may form an inverter connected between the output signal or inverted enable clock 295 and VSS 298. They may be controlled by a feedback node or signal 294. They may output an inverted feedback signal FBN 294N.

Transistors 216, 210, 219, 217, and 218 may form a nand gate connected between VDD 299 and VSS 298. The transistors 216 and 217 may be controlled by a feedback node or signal 294. Transistors 210, 219, and 218 may be controlled by CLK signal 297.

Transistors 216 and 217 may be connected between VDD 299 and transistor 218 controlled by CLK 297. The transistor 214 may be controlled by the output signal or the inverted enable clock 295. The transistor 215 is controllable by the inverted feedback signal FBN 294N. Transistors 214 and 215 may at least partially generate feedback signal 294.

In the illustrated embodiment, when the input clock signal CLK 297 is low and the input (inverted) enable signal EN 296 is low, the feedback node 294 is pulled high by PMOS transistors 211 and 210. Further, the PMOS transistors 210 and 219 precharge the ECKN signal 295 high whenever CLK 297 is low.

In such an embodiment, when CLK 297 transitions from low to high, NMOS transistors 217 and 218 pull ECKN295 low if enable signal EN 296 is active or low when CLK 297 is high (inverted). The transistor 214 holds the feedback node FB 294 high, thereby ensuring that ECKN295 remains low (via transistors 217 and 218).

In contrast, in the illustrated embodiment, if the input enable signal EN 296 is inactive or high, the NMOS transistors 212 and 213 pull the feedback node 294 low. When clock CLK 297 transitions from low to high, the output ECKN295 is held high by PMOS transistor 216 since FB 294 is low. Meanwhile, the transistors 220 and 221 form an inverter using the ECKN295 as a power source or a high voltage power source. The output of the inverter is an inverted feedback signal FBN294N, and when the feedback node FB 294 is low, the inverted feedback signal FBN294N is high. If the enable signal EN 296 input while CLK 297 is high changes to active or low, the transistors 215 and 218 hold the feedback node FB 294 low and ECKN295 high or inactive.

In such embodiments, ECKN295 is prevented from switching or gating ECKN295 when input enable signal EN 296 is inactive. Conversely, when the input enable signal EN 296 is asserted, the ECKN295 follows CLK 297 (and inverts CLK 297), or CLK 297 (in inverted form) is transferred as ECKN295, as it were.

In such embodiments, the transistor 210 may be shared between the input stage 202 and the output stage 204. Furthermore, in various embodiments, the transistors 210 and 219 may be configured for the dual purpose of reducing leakage current in the output stage 204 and balancing the enable output clock ECKN295 over rise and fall delays. In various embodiments, the PMOS stacks 210 and 219 may be almost identical to the NMOS stacks of 217 and 218.

In various embodiments, the inverter formed by transistors 220 and 221 utilizes the voltage supply from ECKN295, as described above. In such an embodiment, it is ensured that there are no unnecessary transitions or handovers. Since CMOS technology requires a voltage difference to operate, the inverter may not allow switching or may be substantially powered down when ECKN295 is low (or substantially the same as VSS 298). In such embodiments, the system 200 is configured to: when the enable signal EN 296 indicates that the enable clock signal ECKN295 should be disabled, there is no full transition from the high (VDD 299) power rail to the low (VSS 298) power rail.

In the illustrated embodiment, the output of the inverter (inverted feedback signal FBN 294N) needs to be high only when EN 296 is active and CLK 297 is high. This indicates that ECKN295 will be high and needs to be maintained high. With FBN294N and high CLK 297, NMOS transistors 215 and 218 help maintain FB 294 low, which in turn ensures that ECKN295 is high. This indicates that power is reduced in both the ON mode and the OFF mode (EN 296 active and inactive).

In the illustrated embodiment, the free running or ungated clock CLK 297 may be connected to only three transistors: transistors 210, 219, and 218. In such an embodiment, if enable signal EN 296 is inactive for an extended period of time, the load on the CLK 297 network is reduced (as compared to conventional designs), which indicates that OFF or non-enabled power consumption is relatively low. Further, as described above, the circuit 200 does not have internal full rail transitions when the enable signal EN 296 is inactive for multiple clock CLK 297 transitions.

In the illustrated embodiment, it is noted that system 200 only employs a single clock signal CLK 297 as an input. In addition, the clock signal CLK 297 has no internal delay. Further, the clock signal CLK 297 is directly connected to the gate terminals of the transistors 210, 218, and 219. This is in contrast to conventional ICG designs, which accept multiple free-running clock signals as inputs or internally delay/invert the clock signals to generate control signals for the transmission gates or other transistors. As described above, this minimal or reduced use of clock signal CLK 297 represents less capacitance on the clock network, and therefore less power consumption. It is to be understood that the above are merely some illustrative examples, and the disclosed subject matter is not limited thereto.

Fig. 3 is a circuit diagram of an example embodiment of a circuit or system 300 according to the disclosed subject matter. In various embodiments, as described above, the system 300 may include an Integrated Clock Gater (ICG).

Similar to the system described with reference to fig. 2A, the system 300 may be configured to transfer the clock signal CLK 297 to the enable clock signal ECK 294 based on the enable signals E396 and SE 395.

In the illustrated embodiment, system 300 may be powered by power rails VDD 299 and VSS 298. In various embodiments, system 300 may utilize Complementary Metal Oxide Semiconductor (CMOS) technology, which uses two power supplies: a high voltage (VDD 299) and a low voltage or ground (VSS 298).

In the illustrated embodiment, the circuit 300 may include P-type metal oxide semiconductor (PMOS) transistors 210, 211, 214, 216, 219, 220. The circuit 300 may include N-type metal oxide semiconductor (NMOS) transistors 212, 213, 215, 217, 218, and 221. In various embodiments, a MOS transistor may include a source terminal, a drain terminal, and a gate terminal.

In the illustrated embodiment, the system 300 may include an output inverter 304. Inverter 304 may be configured to invert inverted enable clock ECKN295 to non-inverted enable clock ECK 294.

In the illustrated embodiment, the system 300 may be configured to input a plurality of enable signals. In such embodiments, system 300 may transfer free-running clock CLK 297 as enable clock signal 294 if any of the enable signals are active (or high). In the illustrated embodiment, the system 300 may include an enable circuit 302 that performs an OR (OR) OR NOR (NOR) Boolean operation on the enable signal (to generate EN 296). In another embodiment, other logical combinations of the plurality of enable signals may produce various states or modes of operation. It is to be understood that the above is merely one illustrative example, and the disclosed subject matter is not so limited.

In the illustrated embodiment, the plurality of enable signals may include a first enable signal E396, the first enable signal E396 configured to turn on/off the clock 297 as part of a power mode or other normal operating mode. In the illustrated embodiment, the plurality of enable signals may include a second enable signal SE 395, the second enable signal SE 395 configured to turn on/off clock 297 when circuit 300 is in a test mode (such as a scan mode). It is to be understood that the above are merely some illustrative examples, and the disclosed subject matter is not limited thereto.

In various embodiments, system 300 may include one or both of inverter 304 and enable circuit 302. Further, it will be appreciated that one skilled in the art will recognize that the order, grouping, and even number of transistors may be varied to produce similar effects. It is to be understood that the above is merely one illustrative example, and that the disclosed subject matter is not so limited.

Fig. 4A is a circuit diagram of an example embodiment of a system 400 according to the disclosed subject matter. In various embodiments, system 400 may include an Integrated Clock Gater (ICG) as described above. Similar to the system described with reference to fig. 3, the system 400 may be configured to transfer the clock signal CLK 297 to the enable clock signal ECK 294 based on the enable signals E396 and SE 395.

In the illustrated embodiment, system 400 may be powered by power rails VDD 299 and VSS 298. In the illustrated embodiment, the circuit 400 may include P-type metal oxide semiconductor (PMOS) transistors 210, 211, 214, 216, 219, 220. The circuit 400 may include N-type metal oxide semiconductor (NMOS) transistors 212, 213, 215, 217, 218, and 221. In various embodiments, a MOS transistor may include a source terminal, a drain terminal, and a gate terminal.

In the illustrated embodiment, the transistor 215 may be connected at a drain terminal with a drain terminal of the transistor 212. In the illustrated embodiment, the transistor 212 may be connected between ground 298 and the transistor 213. However, the transistor 213 may be connected between the transistor 212 and the transistor 211.

As described above, in various embodiments, the location, order, grouping, and even number of transistors may be varied to produce similar effects. It is to be understood that the above is merely one illustrative example, and the disclosed subject matter is not so limited.

Fig. 4B is a circuit diagram of an example embodiment of a system 401 according to the disclosed subject matter. In various embodiments, system 401 may include an Integrated Clock Gater (ICG) as described above. Similar to the system described with reference to fig. 3, system 401 may be configured to transfer clock signal CLK 297 to enable clock signal ECK 294 based on enable signal EN 496B.

In the illustrated embodiment, system 401 may be powered by power rails VDD 299 and VSS 298. In the illustrated embodiment, the circuit 401 may include P-type metal oxide semiconductor (PMOS) transistors 210, 211, 214, 216, 219, 220. The circuit 401 may include N-type metal oxide semiconductor (NMOS) transistors 212, 213, 215, 217, 218, and 221. In various embodiments, a MOS transistor may include a source terminal, a drain terminal, and a gate terminal.

In the illustrated embodiment, enable signal 496B may be generated by enable generator circuit 499. In various embodiments, enable generator circuit 499 may comprise a nor gate as previously shown or similar and combine multiple enable inputs into a single signal 496B. In another embodiment, other forms of logic (possibly more complex) may be used to generate enable signal 496B. In another embodiment, enable signal 496B may be a direct input without enabling generator circuit 499. In some embodiments, other enable signals than enable signal 496B may not be used at all.

In the illustrated embodiment, the transistor 210 may not be shared between the input and output stages of the system 401. Conversely, transistor 219 may be connected to VDD 299 instead of transistor 210. It is to be understood that the above is merely one illustrative example, and the disclosed subject matter is not so limited.

As described above, in various embodiments, the location, order, grouping, and even number of transistors may be varied to produce similar effects. It is to be understood that the above is merely one illustrative example, and the disclosed subject matter is not so limited.

Fig. 4C is a circuit diagram of an example embodiment of a system 402 according to the disclosed subject matter. In various embodiments, the system 402 may include an Integrated Clock Gater (ICG) as described above. Similar to the system described with reference to fig. 3, the system 402 may be configured to transfer the clock signal CLK 297 to the enable clock signal ECK 294 based on the enable signals E396 and SE 395.

In the illustrated embodiment, system 402 may be powered by power rails VDD 299 and VSS 298. In the illustrated embodiment, circuit 402 may include P-type metal oxide semiconductor (PMOS) transistors 210, 211, 214, 216, 219, and 417C. The circuit 402 may include N-type metal oxide semiconductor (NMOS) transistors 212, 213, 215, 218, 221, and 420C. In various embodiments, a MOS transistor may include a source terminal, a drain terminal, and a gate terminal.

In the illustrated embodiment, transistor 420C may be connected between transistors 219 and 221. In such an embodiment, the transistor 420C may be controlled with the feedback node FB 294 (via the gate terminal).

In the illustrated embodiment, transistor 417C may be connected between transistors 216 and 218. In such embodiments, the transistor 417C may be controlled with the feedback node FB 294 (via the gate terminal).

In the illustrated embodiment, the transistor 210 may not be shared between the input and output stages of the system 402. Conversely, transistor 219 may be connected to VDD 299 instead of transistor 210. It is to be understood that the above is merely one illustrative example, and the disclosed subject matter is not so limited.

As described above, in various embodiments, the location, order, grouping, and even number of transistors may be varied to produce similar effects. It is to be understood that the above is merely one illustrative example, and the disclosed subject matter is not so limited.

Fig. 4D is a circuit diagram of an example embodiment of a system 403 according to the disclosed subject matter. In various embodiments, the system 403 may include an Integrated Clock Gater (ICG) as described above. Similar to the system described with reference to fig. 3, the system 403 may be configured to transfer the clock signal CLK 297 to the enable clock signal ECK 294 based on the enable signals E396 and SE 395.

In the illustrated embodiment, system 403 may be powered by power rails VDD 299 and VSS 298. In the illustrated embodiment, circuit 403 may include P-type metal oxide semiconductor (PMOS) transistors 210, 211, 214, 216, 219, and 420D. Circuit 403 may include N-type metal oxide semiconductor (NMOS) transistors 212, 213, 215, 218, 415D, and 417D. In various embodiments, a MOS transistor may include a source terminal, a drain terminal, and a gate terminal.

In the illustrated embodiment, transistor 420D may be connected to transistors 219 and 215. In such an embodiment, the drain terminal of transistor 420D may be connected with the gate terminal of transistor 215. In such an embodiment, the transistor 420D may be controlled with the feedback node FB 294 (via the gate terminal).

In the illustrated embodiment, transistor 415D may be connected between transistors 214 and 215. In such an embodiment, transistor 417D may be controlled by clock signal 297 (via a gate terminal).

In the illustrated embodiment, the transistor 210 may not be shared between the input and output stages of the system 403. Conversely, transistor 219 may be connected to VDD 299 instead of transistor 210. It is to be understood that the above is merely one illustrative example, and the disclosed subject matter is not so limited.

As described above, in various embodiments, the location, order, grouping, and even number of transistors may be varied to produce similar effects. It is to be understood that the above is merely one illustrative example, and the disclosed subject matter is not so limited.

Fig. 5 is a schematic block diagram of an information handling system 500 that may include semiconductor devices formed in accordance with the principles of the disclosed subject matter.

Referring to FIG. 5, an information handling system 500 may include one or more devices constructed in accordance with the principles of the disclosed subject matter. In another embodiment, information handling system 500 may employ or perform one or more techniques in accordance with the principles of the disclosed subject matter.

In various embodiments, the information handling system 500 may include computing devices (such as laptop computers, desktop computers, workstations, servers, blade servers, personal digital assistants, smart phones, tablet computers, and other suitable computers or their virtual machines or virtual computing devices). In various embodiments, information handling system 500 may be used by a user (not shown).

The information handling system 500 according to the disclosed subject matter may also include a Central Processing Unit (CPU), logic, or processor 510. In some embodiments, processor 510 may include one or more blocks of Functional Units (FUBs) or Combinational Logic Blocks (CLBs) 515. In such embodiments, the combinational logic block may include various boolean logic operations (e.g., NAND, NOR, NOT, XOR), stable logic devices (e.g., flip-flops, latches), other logic devices, or combinations thereof. These combinational logic operations may be configured in a simple or complex manner to process the input signals to achieve the desired result. It is to be understood that while some illustrative examples of synchronous combinational logic operations are described, the disclosed subject matter is not so limited and may include asynchronous operations or a mixture thereof. In one embodiment, the combinational logic operation may include a plurality of Complementary Metal Oxide Semiconductor (CMOS) transistors. In various embodiments, these CMOS transistors may be arranged in gates that perform logical operations; it is understood that other techniques may be used and are within the scope of the disclosed subject matter.

The information processing system 500 according to the disclosed subject matter may also include volatile memory 520 (e.g., Random Access Memory (RAM)). Information handling system 500 according to the disclosed subject matter may also include non-volatile memory 530 (e.g., a hard disk drive, optical memory, NAND, or flash memory). In some embodiments, volatile memory 520, non-volatile memory 530, or combinations or portions thereof, may be referred to as "storage media". In various embodiments, the volatile memory 520 and/or nonvolatile memory 530 may be configured to store data in a semi-permanent or substantially permanent form.

In various embodiments, the information handling system 500 may include one or more network interfaces 540, the one or more network interfaces 540 configured to allow the information handling system 500 to become part of and communicate via a communication network. Examples of Wi-Fi protocols can include, but are not limited to, Institute of Electrical and Electronics Engineers (IEEE)802.11g, IEEE802.11 n. Examples of cellular protocols may include, but are not limited to: IEEE 802.16m (also known as wireless-MAN (metropolitan area network) advanced), Long Term Evolution (LTE) advanced, enhanced data rates for GSM evolution (EDGE), evolved high speed packet access (HSPA +). Examples of wired protocols may include, but are not limited to, IEEE 802.3 (also known as ethernet), fibre channel, power line communications (e.g., HomePlug, IEEE 1901). It is to be understood that the above are merely some illustrative examples, and the disclosed subject matter is not limited thereto.

The information processing system 500 according to the disclosed subject matter may also include a user interface unit 550 (e.g., a display adapter, a haptic interface, a human interface device). In various embodiments, the user interface unit 550 may be configured to receive input from a user and/or provide output to a user. Other kinds of devices may also be used to provide for interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic, speech, or tactile input.

In various embodiments, the information handling system 500 may include one or more other devices or hardware components 560 (e.g., a display or monitor, a keyboard, a mouse, a camera, a fingerprint reader, a video processor). It is to be understood that the above are merely some illustrative examples, and the disclosed subject matter is not limited thereto.

The information handling system 500 according to the disclosed subject matter may also include one or more system buses 505. In such embodiments, the system bus 505 may be configured to communicatively connect the processor 510, the volatile memory 520, the non-volatile memory 530, the network interface 540, the user interface unit 550, and the one or more hardware components 560. Data processed by the processor 510 or data input from outside the non-volatile memory 530 may be stored in the non-volatile memory 530 or the volatile memory 520.

In various embodiments, the information handling system 500 may include or execute one or more software components 570. In some embodiments, the software components 570 may include an Operating System (OS) and/or applications. In some embodiments, the OS may be configured to provide one or more services to applications and manage or mediate between the applications and various hardware components (e.g., processor 510, network interface 540) of the information handling system 500. In such embodiments, the information handling system 500 may include one or more native applications that may be installed locally (e.g., locally within the non-volatile memory 530) and configured to be executed directly by the processor 510 and to interact directly with the OS. In such embodiments, the native application may comprise pre-compiled machine executable code. In some embodiments, the native application may include a script interpreter (e.g., C shell (csh), AppleScript, AutoHotkey) or a virtual execution machine (VM) (e.g., Java virtual machine, Microsoft common language runtime) configured to convert source or object code into executable code that is then executed by the processor 510.

The above semiconductor devices may be packaged using various packaging techniques. For example, a semiconductor device constructed in accordance with the principles of the disclosed subject matter may be packaged using any of the following: package on package (PoP) technology, Ball Grid Array (BGA) technology, Chip Scale Package (CSP) technology, leaded plastic chip carrier (PLCC) technology, plastic dual in-line package (PDIP) technology, waffle-die package technology, die in wafer form, Chip On Board (COB) technology, ceramic dual in-line package (CERDIP) technology, Plastic Metric Quad Flat Pack (PMQFP) technology, Plastic Quad Flat Pack (PQFP) technology, small outline package (SOIC) technology, Shrink Small Outline Package (SSOP) technology, Thin Small Outline Package (TSOP) technology, Thin Quad Flat Pack (TQFP) technology, system-in-package (SIP) technology, multi-chip package (MCP) technology, wafer-level fabrication package (WFP) technology, wafer-level processing stack package (WSP) technology, and other technologies as will be appreciated by those skilled in the art.

Method steps can be performed by one or more programmable processors executing a computer program to perform functions by operating on input data and generating output. Method steps can also be performed by, and an apparatus can be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit).

In various embodiments, a computer-readable medium may include instructions that, when executed, cause an apparatus to perform at least a portion of the method steps. In some embodiments, the computer readable medium may be included in magnetic media, optical media, other media, or a combination thereof (e.g., CD-ROM, hard drive, read-only memory, flash drive). In such embodiments, the computer-readable medium may be a tangible and non-transitory article of manufacture.

While the principles of the disclosed subject matter have been described with reference to example embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the disclosed concepts. Accordingly, it is to be understood that the above embodiments are not limiting, but merely illustrative. Accordingly, the scope of the disclosed concept is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing description. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the embodiments.