阅读说明：本技术 考虑多输入切换的操作时序分析装置和方法 (Operation timing analysis apparatus and method considering multi-input switching ) 是由 金汶洙 于 2019-09-06 设计创作，主要内容包括：提供一种考虑多输入切换(MIS)的半导体器件的操作时序分析装置,包括：时序输入单元,其生成构成半导体器件的多个单元中的每一个的MIS模型；以及MIS分析器,其接收多个单元中的每一个的时序数据并基于MIS模型和时序数据动态地计算MIS系数。(There is provided an operation timing analysis apparatus of a semiconductor device considering Multiple Input Switching (MIS), including: a timing input unit that generates a MIS model of each of a plurality of cells constituting the semiconductor device; and a MIS analyzer that receives the time series data of each of the plurality of cells and dynamically calculates MIS coefficients based on the MIS model and the time series data.)

1. An apparatus for operation timing analysis of a semiconductor device including a Multiple Input Switching (MIS) element that considers a MIS effect, the apparatus comprising:

a timing input unit that generates a MIS model for each MIS element; and

an MIS analyzer that receives the timing data for each MIS element and dynamically calculates MIS coefficients based on the MIS model and the timing data for each MIS element.

2. The apparatus of claim 1, wherein the timing input unit loads timing data for the semiconductor device and a design list for the semiconductor device and generates the MIS model based on the timing data and the design list.

3. The apparatus of claim 1, wherein the timing input unit generates a training set using results of a MIS simulation and a Single Input Switching (SIS) simulation, generates a predictive model function for on-chip variation (OCV) sigma of the MIS based on the training set, and generates a MIS variation model based on the predictive model function for OCV sigma of the MIS.

4. The apparatus of claim 3, wherein the MIS analyzer calculates a ratio of the MIS delay to an original delay without consideration of the MIS effect based on a predictive model function of the OCV sigma for the MIS effect, and generates dynamic MIS coefficients based on the ratio of the MIS delay to the original delay.

5. The apparatus of claim 1, wherein the timing data comprises at least one of arrival time data, transition data, load data, and delay data.

6. The apparatus of claim 1, wherein the timing input unit comprises a timing library Database (DB) in which functional attributes of each MIS element are stored, and the MIS analyzer analyzes the functional attributes of each MIS element to obtain a MIS timing path whose delay is changed due to MIS effects.

7. The apparatus of claim 6, wherein the MIS analyzer generates MIS timing information indicating an input pin having a minimum timing among the plurality of input pins for the MIS element.

8. An apparatus for operation timing analysis of a semiconductor device including a Multiple Input Switching (MIS) element that considers a MIS effect, the apparatus comprising:

a Static Timing Analysis (STA) module that generates timing data for each MIS element without considering MIS effects; and

an MIS analyzer that receives the MIS model of each MIS element and dynamically calculates MIS coefficients based on the MIS model and the time series data,

wherein the STA module performs the STA considering the MIS effect based on the MIS coefficient.

9. The apparatus of claim 8, wherein the STA module obtains a MIS timing path for each of a plurality of input pins associated with the MIS element, analyzes an arrival window of the MIS timing path, and calculates a timing variation due to MIS effects by applying MIS coefficients when the arrival windows of the plurality of input pins overlap each other.

10. The apparatus of claim 8, wherein the MIS model of each MIS element includes a MIS variation model based on a predictive model function of OCV sigma for the MIS, and the STA module performs STA accounting for MIS effects based on the MIS variation model.

11. A method of analyzing operation timing of a semiconductor device including a Multiple Input Switching (MIS) element considering MIS effect, the method comprising:

generating a MIS model for each MIS element;

generating timing data for each MIS element without considering MIS effects;

calculating MIS coefficients of each MIS element based on the MIS model and the time series data; and

the STA considering the MIS effect is performed for each MIS element based on the MIS coefficient.

12. The method of claim 11, wherein generating the MIS model for each MIS element comprises:

loading timing data for the semiconductor device and a design list for the semiconductor device; and

generating a MIS model based on the loaded timing data and the design list.

13. The method of claim 11, wherein generating the MIS model for each MIS element comprises:

performing MIS simulation;

performing SIS simulation;

generating a training set by using MIS simulation and SIS simulation;

generating a predictive model function for the OCV sigma of the MIS element based on the training set; and

the MIS variation model is generated based on a predictive model function of OCV sigma for the MIS element.

14. The method of claim 13, wherein generating the MIS variation model further comprises:

calculating a ratio between the MIS delay and an original delay without considering the MIS effect based on a prediction model function of OCV sigma for the MIS element, an

Dynamic MIS coefficients are generated based on the ratio of the MIS delay to the original delay.

15. The method of claim 11, wherein the timing data comprises at least one of arrival time data, translation data, load data, and delay data.

16. The method of claim 11, further comprising:

acquiring an MIS time sequence path by analyzing the functional attribute of the MIS element; and

by analyzing the functional properties of the MIS element, a MIS timing path having a changed delay due to the MIS effect is acquired.

17. The method of claim 16, further comprising:

the merged current value is generated by merging values of a plurality of currents flowing from the plurality of input pins to the output pin of the MIS element.

18. The method of claim 17, further comprising:

generating MIS timing information including a minimum operation indicating an input pin having a minimum timing among the plurality of input pins.

19. The method of claim 16, further comprising:

acquiring a MIS timing path for each of a plurality of input pins of the MIS element;

analyzing an arrival window of the MIS timing path; and

when the arrival windows of the plurality of input pins overlap each other, a timing variation due to the MIS effect is calculated by applying the MIS coefficient.

20. The method of claim 16, further comprising:

analyzing an arrival window of a plurality of input pins of a semiconductor device for MIS timing arcs;

setting the MIS coefficient to a default value when the arrival windows of the plurality of input pins do not overlap with each other; and

the timing variation associated with the MIS effect is calculated.

Technical Field

Embodiments of the inventive concept relate to providing an apparatus and method of operation timing analysis in connection with a semiconductor device including an element or component providing Multiple Input Switching (MIS).

Background

Contemporary semiconductor devices are very complex in their design, performance characterization, manufacture, and operation. Various electrical signals are generated, transmitted, routed, and received (hereinafter collectively referred to as "communications") between various circuits, sub-circuits, components, circuit elements, etc. (hereinafter collectively referred to as "elements"). Exemplary semiconductor elements include at least logic elements such as and, nand, or, nor gates, and combinations thereof (e.g., so-called and-or-inverter or "AOI" gates).

Some semiconductor elements receive only a single signal input (single input switching or SIS), while others receive multiple signal inputs (multiple input switching or MIS). Here, many MIS elements include a plurality of transistors operating in parallel in response to one or more signals. In general, the signal delay associated with the MIS element is shorter than the signal delay associated with the SIS element.

Given the overall complexity involved in the design of contemporary semiconductor devices, it is not surprising that many automated tools are used in this process. In such Electronic Design Automation (EDA) tools, various signal propagation considerations and signal timing relationships must be understood to improve the overall performance of the resulting semiconductor device. Unfortunately, many signal performance analyses for many semiconductor elements (e.g., logic cells) make assumptions based on SIS element behavior predictions. Therefore, the analysis resulting from these assumptions may not accurately reflect the actual operation of the MIS element. In extreme cases, poorly understood and insufficiently designed semiconductor performance may lead to operational failures (e.g., signal hold time failures).

Disclosure of Invention

Embodiments of the inventive concept provide apparatus and methods of modeling a Multiple Input Switching (MIS) element (e.g., a logic gate or cell) in a semiconductor device.

Embodiments of the inventive concept provide an MIS analysis apparatus and method of a semiconductor device capable of improving accuracy and efficiency of operation timing analysis by accurately reflecting MIS analysis using a graph-based analysis (GBA) method when analyzing operation timing of the semiconductor device.

An operation timing analysis apparatus of a semiconductor device including a MIS element according to an embodiment of the inventive concept includes a timing input unit and a MIS analyzer. The timing input unit generates a MIS model of each of a plurality of cells constituting the semiconductor device. The MIS analyzer receives the time series data for each of the plurality of cells and dynamically calculates MIS coefficients based on the MIS model and the time series data.

An operation timing analysis apparatus of a semiconductor device for considering MIS effect according to an embodiment of the inventive concept includes a Static Timing Analysis (STA) module and a MIS analyzer. The STA module generates timing data of each of a plurality of cells constituting the semiconductor device. The MIS analyzer receives the MIS model for each of the plurality of cells and dynamically calculates MIS coefficients based on the MIS model and the time series data.

An operation timing analysis method of a semiconductor device including a MIS element according to an embodiment of the inventive concept includes: generating a model of each of the plurality of MIS elements; generating timing data without considering MIS effect of each MIS element; calculating MIS coefficients of each MIS element based on the MIS model and the time series data; and performing STA considering the MIS effect for each MIS element based on the MIS coefficient.

Drawings

Fig. 1 is a block diagram illustrating an operation timing analysis apparatus of a semiconductor device accurately reflecting an MIS effect according to an embodiment of the inventive concept.

Fig. 2 is a flow chart summarizing a method of analyzing the operation timing of a semiconductor device reflecting MIS effects in one example.

Fig. 3 is a conceptual diagram illustrating a driving method for a MIS model generator in one example.

Fig. 4 is another conceptual diagram illustrating a driving method for the MIS analyzer in one example.

Fig. 5 is a conceptual diagram illustrating a set of signal waveforms and a method of generating a MIS model and MIS coefficients.

FIG. 6 is a diagram further illustrating a machine learning method for generating a merged model.

Fig. 7 is another conceptual diagram illustrating a method of calculating the MIS current and the MIS delay.

Fig. 8 is another conceptual diagram illustrating a method of generating a delay report for MIS variation.

Fig. 9 is still another conceptual diagram illustrating a method of generating a minimum operation optimized for MIS.

The above and other objects, features and advantages of the present inventive concept will become more apparent to those of ordinary skill in the art by describing in detail exemplary embodiments thereof with reference to the attached drawings.

Detailed Description

Certain embodiments of the inventive concept will now be described with reference to the accompanying drawings. As an illustrative example, these embodiments teach at least the fabrication and use of a particular operational timing analysis apparatus and corresponding methods. Here, the operation timing analysis apparatus and/or method can be advantageously applied to design, performance characterization, manufacture, and/or analysis of a semiconductor device, particularly a semiconductor device including a MIS element.

Some phenomenon related to the operation of MIS elements has been noted previously. That is, when a plurality of transistors are simultaneously switched in the MIS element, the signal delay (i.e., the period of time required for a signal to propagate through the element) of the MIS element is smaller than the analog signal delay of the SIS element. Therefore, when conventional operational timing analysis, which cannot accurately distinguish MIS element signal delays from SIS element signal delays, is performed on certain semiconductor devices, erroneous signal timing conclusions may be drawn. As a result, the actual operation timing is different from the expected (or design-specified) operation timing, and such variation may cause malfunction of the semiconductor device.

In view of these potentially undesirable results, certain embodiments of the inventive concept provide an operation timing analysis apparatus and/or method that properly accounts for the presence and actual operation of MIS elements within semiconductor devices. In a related approach, one or more MIS coefficients designated as inputs to the operational timing analysis may be used. For example, when input signal arrival times overlap, the corresponding signal delay may be reduced by applying (e.g., multiplying) MIS coefficients such that MIS phenomena are accounted for and input signal arrival times are defined such that they do not arrive in an overlapping manner.

In another related approach, the MIS coefficients may be used to appropriately modify the Static Timing Analysis (STA) when overlapping timing windows of signals applied to input pins of a semiconductor device occur.

An apparatus and method for operation timing analysis of a semiconductor device according to an embodiment of the inventive concept may calculate a MIS coefficient using various timing information and a Complex Current Source (CCS) to accurately reflect a MIS phenomenon. Further, when performing graph-based analysis (GBA) for operation timing analysis, unnecessary elements can be eliminated by optimizing minimum operations.

Fig. 1 is a block diagram illustrating an operation timing analysis apparatus of a semiconductor device that can be used to accurately reflect an MIS phenomenon according to an embodiment of the inventive concept.

Referring to fig. 1, the operation timing analysis apparatus 10 may include a timing input unit 100, a MIS analyzer 200, and a Static Timing Analysis (STA) module 300. The timing input unit 100 may include an Integrated Circuit (IC) design list 110 (e.g., a netlist), a timing library Database (DB)120, and a MIS model generator 130. The MIS analyzer 200 may include a MIS timing path generator 210, a MIS coefficient generator 220, and a MIS timing information update module 230.

The components constituting the timing input unit 100, the MIS analyzer 200, and the STA module of the operation timing analysis apparatus 10 may be variously configured using software, hardware, and/or firmware. For example, the operation timing analysis apparatus 10 of fig. 1 may be implemented as one or more software programs on a general purpose computing platform (e.g., a PC, laptop, tablet, or smartphone).

Fig. 2 is a flowchart illustrating a method of analyzing an operation timing of a semiconductor device while accurately reflecting an MIS phenomenon in one example. Fig. 3 is a conceptual diagram further illustrating one possible driving method of the MIS model generator 130 of fig. 1.

Referring collectively to fig. 1, 2 and 3, STA may be performed using STA module 300 as long as an accurate MIS model has been previously generated.

Accordingly, the timing input unit 100 may load the IC design list 110 for the semiconductor device under analysis and also load the corresponding timing information for the loaded IC design list from the timing library DB 120. MIS model generator 130 may then generate MIS model 130a based on the loaded IC design list and timing information. Since the effect caused by the presence of the MIS element may affect not only the basic cell delay but also the variation therein, the MIS variation model 130b may be generated in consideration of the variation (S10). The timing input unit 100 may generate the MIS model 130a and the MIS variation model 130b for each of a plurality of elements (e.g., cells or logic gates) in the semiconductor device or some portion thereof (e.g., a chip portion, a semiconductor layer, a designated circuit or a circuit portion, etc.).

The timing input unit 100 can generate a learning model using the MIS simulation result and the SIS simulation result as a training set for machine learning. For example, the timing input unit 100 may calculate the MIS coefficient according to the following equation in order to generate the learning model:

y＝b1*x1+b2*x2+b3*x3+b4*x4+b5，

where "y" is the value to be predicted, and "x 1, x 2.

Here, the timing input unit 100 may define "y" and "x 1, x 2. The timing input unit 100 may perform a function for calculating "y" by numerically calculating "b 1, b 2., b 5". Then, the timing input unit 100 may predict the value of "y" when actual data is input.

The timing input unit 100 can generate a predictive model function for on-chip variation (OCV) sigma associated with the MIS element based on a training set. The timing input unit 100 may generate a MIS variation model according to process variation based on a prediction model function of an OCV sigma (OCV _ sigma) of the MIS. When the nominal signal (nominal signal) delay is short due to the MIS phenomenon, the OCV sigma associated with the MIS element may be less than the typical OCV sigma (OCV _ sigma). The timing input unit 100 can generate a MIS variation model using a predictive model of OCV sigma to improve accuracy of MIS analysis of MIS elements (e.g., cells).

Fig. 4 is another flow chart further illustrating, in one example, a driving method for the MIS analyzer 200 of fig. 1.

Referring now to fig. 1, 2 and 4, the STA module 300 may acquire timing data by performing STA without considering MIS effect (S20). The timing data acquired in the STA module 300 may include arrival time data, transition data, load data, and delay data. The STA module 300 may provide the time of arrival data, the conversion data, the payload data, and the delay data to the MIS analyzer 200. The STA module 300 can acquire arrival time data, conversion data, load data, and signal delay data of each of a plurality of MIS elements (e.g., a plurality of cells) constituting a part of a semiconductor device (e.g., a chip) without considering the MIS effect.

Subsequently, the MIS analyzer 200 may dynamically calculate the MIS coefficient based on the MIS model generated by the timing input unit 100 and the arrival time data, the conversion data, the load data, and the delay data acquired in the STA module 300 without considering the MIS effect (S30).

The MIS timing path generator 210 can acquire a timing path of the MIS by analyzing a functional attribute of each of a plurality of units constituting the chip. The MIS timing path generator 210 can acquire a timing path where delay may change due to MIS effects. That is, MIS timing path generator 210 may generate a timing path from an input pin of a cell to an output pin of the cell. The MIS timing path generator 210 analyzes a signal delay of output switching by two or more parallel switching inputs, and can acquire a path in which the delay is shortened by simultaneously inputting two or more signals. The MIS timing path generator 210 can acquire a timing path in which delay is shortened due to MIS by parsing the functional attributes stored in the timing base DB 120.

The MIS coefficient generator 220 of the MIS analyzer 200 can analyze the arrival windows of all MIS timing paths. When STA is executed, MIS coefficients may be applied when the timing windows of the input pins overlap each other.

MIS coefficient generator 220 may dynamically calculate MIS coefficients using the timing data (e.g., arrival window, transition data, load data, etc.) and the MIS model. MIS coefficient generator 220 may combine values of a plurality of currents flowing from a plurality of input pins to a plurality of output pins of the semiconductor device to generate a combined current (i.e., a combined i (t)) value. In order to generate the combined i (t), a method of combining current values should be set in advance. In some embodiments of the inventive concept, a machine learning approach may be used to generate the merged model.

Subsequently, the MIS timing information update module 230 of the MIS analyzer 200 may update the arrival time of the output pin of the semiconductor device (e.g., IC chip) after reflecting the effect (or "MIS effect") of the MIS (S40). The MIS timing information update module 230 can update the arrival time of the output pin of the semiconductor device (e.g., IC chip) by reflecting the MIS influence. The MIS timing information update module 230 may include a minimum operation optimized for MIS while updating the arrival time of the output pin. That is, the MIS timing information updating module 230 may update the MIS timing information including a minimum operation indicating an input pin having a minimum timing among the plurality of input pins.

Thus, the described "functional attributes" may be used to represent the logical relationship between the input pins and the output pins. As one example, in the case of an AND/OR unit, the output pin Y may have the following relationship with the input pins a AND B.

AND (unit) Y ═ a AND B (example 1)

OR (unit) Y ═ a OR B. (example 2)

Analysis of the functional properties shows that in the case of an OR cell (example 2), when a and B become 1 simultaneously (e.g., rise time transition), the cell delay is shortened due to MIS.

Subsequently, the STA module 300 may perform STA in consideration of the MIS effect (S50). As one example, the STA module 300 may analyze the arrival window to calculate timing variations due to MIS effects. The STA module 300 may analyze an arrival window of each pin along the MIS timing path and calculate a timing variation due to the MIS effect by applying MIS coefficients when the arrival windows overlap each other.

When the arrival windows do not overlap each other, the STA module 300 may set the MIS coefficient to a default value (e.g., 1.0) and calculate the timing variation without considering the MIS effect. That is, the MIS effect may be applied not only to the default cell delay but also to the variation. Finally, the effects caused by MIS can be reflected in timing. When the output pins are to be merged, the STA module 300 may perform minimal operations optimized for MIS.

Fig. 5 is a conceptual set arrangement of signal waveforms illustrating a method of generating MIS models and associated MIS coefficients.

Referring to fig. 5, the operation timing analysis apparatus 10 may calculate the MIS effect by reflecting the pre-calculated timing information when the STA is executed using the CCS model.

When a transition occurs from the input pin to the output pin based on the SIS, the operation timing analysis apparatus 10 of the semiconductor device can store a waveform while performing the STA.

The MIS analyzer 200 may calculate a value of the first SIS I (t) at a timing arc where a signal flows from the input terminal I1 to the output terminal O (I1 → O). The MIS analyzer 200 may calculate a value of the second SIS I (t) at a timing arc where the signal flows from the input terminal I2 to the output terminal O (I2 → O). MIS analyzer 200 may calculate a merged I (t) reflecting the MIS condition by merging the value of the first SIS I (t) and the value of the second SIS I (t).

The MIS analyzer 200 may generate dynamic MIS coefficients. MIS analyzer 200 may assume SIS delays of D1 and D2, respectively, and the delay of the merged i (t) is Dm. Here, the dynamic MIS coefficients may be Dm/D1 and Dm/D2 as shown in fig. 5.

FIG. 6 is a diagram further describing a machine learning method for generating a merged model in one example.

As shown in fig. 2 and 6, the method of combining the multiple current values to produce a combined i (t) value may be predetermined. However, in certain embodiments of the inventive concept, a machine-learned merge model may be used to generate the merged i (t).

The current may be generated and stored using a piecewise linear model, as shown in equation 1 below. A separate linear function for time may be defined for each timing interval and represented as a non-linear waveform.

Fig. 7 is a conceptual diagram illustrating one possible method of calculating MIS current and MIS delay.

Referring to fig. 1, 2, 3 and 7, the timing input unit 100 may perform MIS simulation under various conditions. After performing MIS simulations under various conditions, simulations of SIS may also be performed. The timing input unit 100 may record the results of the MIS simulation and the SIS simulation as shown in table 1 below.

TABLE 1

In table 1, the upper load limit for each time interval of each SIS current, as well as the slope and intercept of the linear function (e.g., training data) can be described. Current values (e.g., training data) for each interval may also be recorded for the MIS. In table 1, "I12 (b 1)" and "I12 (b 2)" are the output (y) of the training, the rest may be the input variables that affect y.

MIS model generator 130 may generate a model "F" that predicts an intercept value in the next interval of MIS elements (for example) for each cell based on training data.

This model is the result of performing training in advance by a machine learning method using the characterization data before the STA. The MIS model generated by MIS model generator 130 may be used as an input to the STA.

When the STA is executed by the STA module 300, timing data (arrival time data, conversion data, load data, delay data) such as a load upper limit value and an SIS current waveform of each pin after timing analysis may be acquired. Thus, the STA module 300 may predict the MIS current by applying the timing data to the generated prediction model at the time of characterization.

The STA module 300 may calculate the intercept of the MIS current. The intercept of the MIS current may be zero (0) in the initial time interval. The intercept of the MIS current in the next time interval may be calculated using a model in which one or more of the MIS intercept, the slope of the SIS, and the intercept of the SIS in the previous time interval are used as inputs.

As described above, the STA module 300 may calculate the intercept of the MIS current. The STA module 300 may calculate the MIS delay from the MIS current. The dynamic MIS coefficient may be calculated from the ratio of the MIS delay to the original delay without considering the MIS.

Fig. 8 is another conceptual diagram illustrating a method of generating a delayed report of MIS changes in one example.

Referring to fig. 1, 2, 3 and 8, to account for process variations, when a STA is executed, the STA module 300 may analyze not only the nominal delay but also the variations. When a STA is executed, STA module 300 may perform an analysis of nominal delays and variations to generate 3-sigma level delay reports consistent with table 2 below.

TABLE 2

Wherein Delay _ reported ± 3 × ocv _ sigma

Here, delay _ nominal is a delay value when there is no process change (variation). OCV sigma (OCV sigma) may refer to a delay variation of the order of 1-sigma. In table 2, "OCV _ sigma" is the output of the training (y), and the rest may be the input variables that affect y.

When the delay is changed due to MIS effects, the variation (variation) may also be changed. Therefore, both of these issues should be considered when conducting accurate analysis.

MIS model generator 130 may use the results of the MIS simulation and the SIS simulation to generate a training set. Subsequently, the MIS model generator 130 may generate a predictive model function "G" for each cell for the MIS's OCV sigma (OCV _ sigma) using the generated training set.

The MIS analyzer 200 may use the MIS coefficient model F to calculate the MIS nominal delay when performing the actual timing analysis.

In addition, when the nominal delay is input to the function "G" together with the SIS information of each input pin, a predicted value of the OCV sigma (OCV _ sigma) of the MIS can be obtained. At this time, MIS coefficients for variation, that is, dynamic MIS coefficients (dMCV) for variation may be generated. Here, dMCV may be calculated by the following equation 2.

Mcmv MIS _ OCV _ sigma/SIS _ OCV _ sigma equation 2

Fig. 9 is a conceptual diagram illustrating a method of generating a minimal operation optimized for MIS effects in one example.

Referring to fig. 1, 2, 3 and 9, when there is an interval in which the arrival windows of the three pins overlap each other, the operation timing analysis apparatus 10 of the semiconductor device can reflect the MIS Coefficient (MC) for the timing arc.

Therefore, the operation timing analysis apparatus 10 applies the GBA method in calculating the timings of the plurality of paths associated with the cell having the plurality of input pins. Here, the slowest path and the fastest path may be stored. The operation timing analysis apparatus 10 of the semiconductor device can perform GBA and find a path where a problem may occur in the delay timing of the signal. After finding a path that may cause delay timing problems for the signal, a path-based analysis (PBA) may be performed, and finally, the timing analysis may be completed.

The operation timing analysis apparatus 10 may determine the minimum value at the output pin O as shown in table 3 below.

The operation timing analysis apparatus 10 of the semiconductor device can find the fastest path when signals flow from the three input pins A, B and C to the output pin O. Here, finding the smallest delay, i.e., the fastest path, when a signal flows from a plurality of input pins to an output pin may be referred to as "MIN operation".

TABLE 3

The operation timing analysis means 10 can analyze the timing by dividing the arrival window based on the overlap. Therefore, unnecessary elements in the timing analysis can be eliminated.

In fig. 9, the operation timing analysis apparatus 10 may divide the arrival window a associated with the pin a into a1, a2, and a 3. Then, the operation timing analysis apparatus 10 can accurately calculate the MIS effect in relation to the divided windows ai, bi, and ci as shown in the following tables 4 and 5, where table 4 is an example of calculating the MIS effect from the nominal delay and table 5 is an example of calculating the MIS effect from the variation perception timing.

TABLE 4

As shown in table 4, the operation timing analysis apparatus 10 can calculate the MIS effect from the nominal delay. The operation timing analysis apparatus 10 of the semiconductor device can predict a path "a 1 → O: a1(e) + D1 × dMC (a, B) ", and path" a1 → O: the delay time "10 +5 × 0.5 ═ 12.5" of a1(e) + D1 × dMC (a, B) ".

TABLE 5

As shown in table 5, the operation timing analysis apparatus 10 can calculate the MIS effect from the variation perception timing. The operation timing analysis apparatus 10 of the semiconductor device can predict a path "b 1 → O with the smallest delay among paths flowing from the plurality of inputs a, b, and c to the output O: b1(e) + D2 ", and the path" b1 → O: delay time "5 +8-3 × 0.8 ═ 10.6" of b1(e) + D2 ".

The operation timing analysis apparatus and method for design and characterization of a semiconductor device according to an embodiment of the inventive concept may dynamically generate the MIS coefficient described above using information and a current waveform generated when the STA is performed.

Such an operation timing analysis apparatus and method can obtain a combined current waveform in view of the MIS effect. To this end, the current waveforms may be combined in the form of "a × t + b" using a piecewise linear model.

The operation timing analysis apparatus and method may iteratively calculate a value of the combined current while changing the time interval to calculate the combined current when MIS occurs.

The operation timing analysis apparatus and method may perform machine learning to predict a value of OCV sigma (OCV _ sigma).

The operation timing analysis apparatus and method can calculate MIS effects for a subset of the defined window rather than the entire arrival window. Thus, unnecessary elements that might otherwise interfere with minimal operation may be eliminated.

The operation timing analysis apparatus and method may dynamically generate the MIS coefficient using information and a current waveform generated when the STA is performed.

The operation timing analysis apparatus and method can obtain a combined current waveform when the MIS effect exists. To this end, the current waveforms may be combined in the form of a × t + b using a piecewise linear model.

The operation timing analysis apparatus and method may iteratively calculate values of the combined currents while changing the time interval to calculate the combined currents when MIS occurs.

The operation timing analysis apparatus and method may perform machine learning to predict the value of OCV sigma.

The operation timing analysis apparatus and method can calculate MIS effects associated with a subset window rather than an entire arrival window. Therefore, unnecessary elements occurring in the minimum operation for finding the fastest path (the path with the smallest delay) can be eliminated.

Although the embodiments of the inventive concept have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various modifications may be made without departing from the scope of the inventive concept and without changing the essential features. Accordingly, the above-described embodiments should be considered in descriptive sense only and not for purposes of limitation.