阅读说明：本技术 一种基于fpga的可扩展的多端口ddr3控制器 (Extensible multiport DDR3 controller based on FPGA ) 是由 夏明敏 李正刚 朱天雄 于 2020-04-27 设计创作，主要内容包括：本发明涉及通讯技术领域,尤其涉及一种基于FPGA的可扩展的多端口DDR3控制器,包括仲裁模块、读写空间大小管理模块、DDR3 IP核控制模块和FIFO接口控制模块,所述仲裁模块、读写空间大小管理模块、DDR3 IP核控制模块和FIFO接口控制模块依次电连接；所述仲裁模块用于根据读写空间大小管理模块提供的读写剩余可用地址空间大小、各端口所对应的FIFO容量阈值和各端口按实际需求排列的优先级信息来综合仲裁管理各端口的读写请求。本发明具有标准FIFO读写接口形式、端口数量可配置、单次读写大小可配置、各端口地址空间大小总量可配置以及控制器内部提供各端口读写优先级仲裁。(The invention relates to the technical field of communication, in particular to an extensible multi-port DDR3 controller based on an FPGA (field programmable gate array), which comprises an arbitration module, a read-write space size management module, a DDR3IP (Internet protocol) core control module and an FIFO (first in first out) interface control module, wherein the arbitration module, the read-write space size management module, the DDR3IP core control module and the FIFO interface control module are electrically connected in sequence; the arbitration module is used for comprehensively arbitrating and managing the read-write requests of the ports according to the size of the read-write residual available address space provided by the read-write space size management module, the FIFO capacity threshold corresponding to each port and the priority information arranged by each port according to actual requirements. The invention has the advantages of standard FIFO read-write interface form, configurable port number, configurable single read-write size, configurable total address space size of each port and arbitration of read-write priority of each port provided in the controller.)

1. An FPGA-based scalable multi-port DDR3 controller, comprising: the device comprises an arbitration module, a read-write space size management module, a DDR3IP core control module and an FIFO interface control module, wherein the arbitration module, the read-write space size management module, the DDR3IP core control module and the FIFO interface control module are electrically connected in sequence;

the arbitration module is used for comprehensively arbitrating and managing the read-write requests of the ports according to the size of the read-write residual available address space provided by the read-write space size management module, FIFO capacity thresholds corresponding to the ports and priority information arranged by the ports according to actual requirements;

the read-write space size management module is used for managing the read-write process of each port, carrying out address statistics and management on the read-write flow of each port every time according to the single read-write size of global configuration and the total size of the address space of each port, and calculating and updating the size of the current read-write residual available address space after each read-write;

the DDR3IP core control module is used for controlling a Burst read-write time sequence process of the IP core, and the FIFO interface control module is used for controlling an FIFO read-write time sequence process of each port.

2. The FPGA-based scalable multi-port DDR3 controller of claim 1, wherein: the DDR3IP core control module and the FIFO interface control module are further used for sending and receiving signal interface logic control module data.

3. The FPGA-based scalable multi-port DDR3 controller of claim 1, wherein: the arbitration module arranges the read-write priority of each channel according to the design requirement, and then reads the read-write space size management module to calculate the read-write residual available address space size corresponding to each port from the feedback; for the write-in data, judging that if the size of the residual available write address space is larger than or equal to the size of single write-in configured in the global and the FIFO readable pre-empty mark at the write-in data stream side is 0, the write-in data request of the corresponding port is arbitrated to pass; for the read data, judging that if the size of the residual available read address space is larger than or equal to the size of the globally configured single read-write and the read data stream side FIFO can write the pre-full flag 0, the read data request of the corresponding port is arbitrated to pass.

4. The FPGA-based scalable multi-port DDR3 controller of claim 3, wherein: the read-write space size management module is used for arbitrating the passing port of the write data request, accumulating and counting the write data volume in the process of writing data, and clearing the accumulated and counted write data volume and negating the write overflow flag bit when the write data volume reaches the total size of the address space configured by the port; and accumulating and counting the read data quantity of the port through which the read data request passes in the process of reading the data, and clearing the accumulated and counted read data quantity and negating a read overflow flag bit when the read data quantity reaches the total amount of the size of the address space configured by the port.

5. The FPGA-based scalable multi-port DDR3 controller of claim 4, wherein: the write overflow flag bit and the read overflow flag bit of the same port include four logic relations: the system comprises a write overflow flag bit logic 0 and a read overflow flag bit logic 0, a write overflow flag bit logic 0 and a read overflow flag bit logic 1, a write overflow flag bit logic 1 and a read overflow flag bit logic 0, and a write overflow flag bit logic 1 and a read overflow flag bit logic 1, wherein the read-write space size management module calculates the size of the port read-write residual available address space according to the four logic relations.

6. The FPGA-based scalable multi-port DDR3 controller of claim 1, wherein: the data signals written by the user in the FIFO signal interface of the FIFO interface control module are as follows:

port N data write request fifo chn _ wrreq _ ddr 3;

port N write data fifo _ data _ ddr 3;

port N writes the pre-full flag fifo chn _ prog _ full _ ddr 3;

where N refers to the channel number.

7. The FPGA-based scalable multi-port DDR3 controller of claim 6, wherein: the data signals read by the user in the FIFO signal interface of the FIFO interface control module are as follows:

port N data read request fifo _ rdreq _ ddr 3;

port N reads data fifo _ q _ ddr 3;

port N reads the pre-empty flag fifo _ prog _ empty _ ddr 3;

where N refers to the channel number.

8. The FPGA-based scalable multi-port DDR3 controller of claim 7, wherein: the calculation of the prog _ full pre-full threshold of the FIFO at the write data stream side in the FIFO interface control module is that the size of the user single write data stream is subtracted by 1.5 times from the depth value of the FIFO and is equal to the threshold, and the calculation of the prog _ empty pre-threshold of the FIFO at the write data stream side in the FIFO interface control module is that the size of the single read and write is subtracted by 1 and is equal to the threshold.

9. The FPGA-based scalable multi-port DDR3 controller of claim 8, wherein: the calculation of the prog _ full pre-full threshold of the FIFO on the read data stream side in the FIFO interface control module is that the size of single read data stream of a user is subtracted by 1.5 times from the depth value of the FIFO and is equal to the threshold, and the calculation of the prog _ empty pre-threshold of the FIFO on the read data stream side in the FIFO interface control module is that the size of single read data stream is subtracted by 1 and is equal to the threshold.

10. The FPGA-based scalable multi-port DDR3 controller of claim 1, wherein: and replacing the read-write space size management module with a signal interface logic control module, wherein the signal interface logic control module is used for configuring the number of ports according to port expansion requirements, and the DDR3IP core control module and the FIFO interface control module are also used for sending and receiving signal interface logic control module data.

Technical Field

The invention relates to the technical field of communication, in particular to an extensible multi-port DDR3 controller based on an FPGA.

Background

With the rapid development of semiconductor memory technology, DDR3 memory particles have the advantages of large capacity, high read-write speed, stable operation, and the like, so DDR3 memories are widely used in the fields of computers, electronic communications, and the like. The FPGA has super large logic gate resources, can simultaneously process multiple paths of complex data streams, and can realize multiple complex algorithms, so the FPGA is widely applied to the fields of communication, image processing and the like.

The DDR3 hardmac resource interface of the latest kintex-7 series FPGAs in the market implements the physical layer connection of the DDR3PHY, but its hardmac IP provides only a single read-write interface for the user, including read-write address input app _ addr, read-write control command app _ cmd, command enable app _ en, write data app _ wdf _ data, write enable app _ wdf _ wren, write end app _ wdf _ end, read data app _ rd _ data, read enable app _ wdf _ wren, read end app _ rd _ data _ end, read valid app _ rd _ data _ valid, read-write ready app _ rdy, and so on. Since the interface method can only perform read-write operation of one port data stream and is complex, the requirement of multi-port application that multi-path high-speed complex data stream cache needs to be processed simultaneously cannot be met. To this end, we propose an FPGA-based scalable multi-port DDR3 controller.

Disclosure of Invention

Based on the technical problems in the background art, the invention provides an extensible multi-port DDR3 controller based on an FPGA, which has the characteristics of more convenient read-write operation and higher use efficiency of a DDR3, and solves the problem that the prior art cannot meet the multi-port application requirement of simultaneously processing multi-path high-speed complex data stream cache.

The invention provides the following technical scheme: an extensible multi-port DDR3 controller based on an FPGA comprises an arbitration module, a read-write space size management module, a DDR3IP core control module and an FIFO interface control module, wherein the arbitration module, the read-write space size management module, the DDR3IP core control module and the FIFO interface control module are electrically connected in sequence;

the arbitration module is used for comprehensively arbitrating and managing the read-write requests of the ports according to the size of the read-write residual available address space provided by the read-write space size management module, FIFO capacity thresholds corresponding to the ports and priority information arranged by the ports according to actual requirements;

the read-write space size management module is used for managing the read-write process of each port, carrying out address statistics and management on the read-write flow of each port every time according to the single read-write size of global configuration and the total size of the address space of each port, and calculating and updating the size of the current read-write residual available address space after each read-write;

the DDR3IP core control module is used for controlling a Burst read-write time sequence process of the IP core, and the FIFO interface control module is used for controlling an FIFO read-write time sequence process of each port.

Preferably, the device further comprises a signal interface logic control module, wherein the signal interface logic control module is used for configuring the number of the ports according to the port expansion requirement, and the DDR3IP core control module and the FIFO interface control module are further used for sending and receiving signal interface logic control module data.

Preferably, the arbitration module arranges the read-write priority of each channel according to design requirements, and then reads the read-write space size management module to calculate the read-write residual available address space size corresponding to each port from the feedback; for the write-in data, judging that if the size of the residual available write address space is larger than or equal to the size of single write-in configured in the global and the FIFO readable pre-empty mark at the write-in data stream side is 0, the write-in data request of the corresponding port is arbitrated to pass; for the read data, judging that if the size of the residual available read address space is larger than or equal to the size of the globally configured single read-write and the read data stream side FIFO can write the pre-full flag 0, the read data request of the corresponding port is arbitrated to pass.

Preferably, the read-write space size management module counts the write data amount in the process of writing data for the port through which the write data request arbitrates, and clears the counted write data amount and negates the write overflow flag bit when the write data amount reaches the total address space size configured for the port; and accumulating and counting the read data quantity of the port through which the read data request passes in the process of reading the data, and clearing the accumulated and counted read data quantity and negating a read overflow flag bit when the read data quantity reaches the total amount of the size of the address space configured by the port.

Preferably, the write overflow flag bit and the read overflow flag bit of the same port include four logical relations: the system comprises a write overflow flag bit logic 0 and a read overflow flag bit logic 0, a write overflow flag bit logic 0 and a read overflow flag bit logic 1, a write overflow flag bit logic 1 and a read overflow flag bit logic 0, and a write overflow flag bit logic 1 and a read overflow flag bit logic 1, wherein the read-write space size management module calculates the size of the port read-write residual available address space according to the four logic relations.

Preferably, the data signal written by the user in the FIFO signal interface of the FIFO interface control module is:

port N data write request fifo chn _ wrreq _ ddr 3;

port N write data fifo _ data _ ddr 3;

port N writes the pre-full flag fifo chn _ prog _ full _ ddr 3;

where N refers to the channel number, i.e., port number.

Preferably, the data signal read by the user in the FIFO signal interface of the FIFO interface control module is:

port N data read request fifo _ rdreq _ ddr 3;

port N reads data fifo _ q _ ddr 3;

port N reads the pre-empty flag fifo _ prog _ empty _ ddr 3;

where N refers to the channel number, i.e., port number.

Preferably, the calculation of the prog _ full pre-full threshold of the FIFO on the write data stream side in the FIFO interface control module is that the size of a single write data stream of a user is subtracted by 1.5 times from the depth value of the FIFO and is equal to the threshold, and the calculation of the prog _ empty pre-threshold of the FIFO on the write data stream side in the FIFO interface control module is that the size of a single read and write is subtracted by 1 and is equal to the threshold.

Preferably, the threshold calculation of prog _ full pre-full of the FIFO on the read data stream side in the FIFO interface control module is that the size of single read data stream of a user is subtracted by 1.5 times from the depth value of the FIFO and is equal to the threshold, and the threshold calculation of prog _ empty of the FIFO on the read data stream side in the FIFO interface control module is that the size of single read data stream is subtracted by 1 and is equal to the threshold.

Preferably, the read-write space size management module is replaced by a signal interface logic control module, the signal interface logic control module is used for configuring the number of ports according to port expansion requirements, and the DDR3IP core control module and the FIFO interface control module are further used for sending and receiving signal interface logic control module data.

The invention provides an extensible multi-port DDR3 controller based on an FPGA, a user can configure the number of data flow channels according to actual use requirements, and a read-write interface adopts a standard FIFO interface form, so that the read-write operation is more convenient, the data read-write of different clock domains is isolated, and the generation of a metastable state is avoided.

The user may integrate the write bandwidth and the read bandwidth of the matching data stream based on the actual write data stream logic and the read data stream logic, making DDR3 more efficient to use. A user can set the size of an access address space according to the actual data stream cache size requirement of each port, and the memory space of DDR3 is saved.

When the user uses the controller, the read-write condition of the DDR3 and the internal read-write bandwidth problem do not need to be concerned, and whether data can be written or read currently is determined according to prog _ full and prog _ empty of the FIFO interface.

Drawings

FIG. 1 is a block diagram of an FPGA-based scalable multi-port DDR3 controller;

FIG. 2 is a FIFO signal interface diagram;

FIG. 3 is a signal relationship diagram between core modules;

FIG. 4 is a read-write data flow diagram.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The invention provides a technical scheme that: