Three-dimensional junction-free semiconductor memory device and manufacturing method and operating method thereof
阅读说明：本技术 一种三维无结半导体存储器件及其制造方法、操作方法 (Three-dimensional junction-free semiconductor memory device and manufacturing method and operating method thereof ) 是由 肖德元 张汝京 于 2019-02-15 设计创作，主要内容包括：本发明提供一种三维无结半导体存储器件及其制造方法、操作方法,该三维无结半导体存储器件包括衬底、多个垂直沟道结构及多个栅极层,其中,垂直沟道结构包括在X方向上相对设置的一对平面侧面及在Y方向上相对设置的一对弧面侧面,使得垂直沟道结构的横截面形状呈跑道型,栅极层环绕于垂直沟道结构四周,相邻栅极层之间通过绝缘层隔离。跑道型沟道相对较大的周长使得栅极层与信息储存层的接触面积相应增大,在相同的栅极电压下,栅极层对电荷俘获层中电荷的束缚能力增强,电荷不易泄露,可有效延长存储单元中电荷的保持时间,提高存储单元的存储性能。栅极层三侧的电荷俘获层进一步增加了被俘获电子的可分布区域,有利于实现优秀的三位控制能力。(The invention provides a three-dimensional junctionless semiconductor memory device, a manufacturing method and an operation method thereof, wherein the three-dimensional junctionless semiconductor memory device comprises a substrate, a plurality of vertical channel structures and a plurality of gate layers, wherein each vertical channel structure comprises a pair of plane side surfaces which are oppositely arranged in an X direction and a pair of cambered surface side surfaces which are oppositely arranged in a Y direction, so that the cross section of each vertical channel structure is in a runway shape, the gate layers surround the periphery of the vertical channel structures, and adjacent gate layers are isolated by insulating layers. The relatively larger circumference of the runway-type channel enables the contact area between the grid layer and the information storage layer to be correspondingly increased, under the same grid voltage, the constraint capacity of the grid layer on charges in the charge trapping layer is enhanced, the charges are not easy to leak, the retention time of the charges in the storage unit can be effectively prolonged, and the storage performance of the storage unit is improved. The charge trapping layer on three sides of the gate layer further increases the distributable area of trapped electrons, which is beneficial to realizing excellent three-dimensional control capability.)
1. A method of fabricating a three-dimensional, junctionless semiconductor memory device, comprising the steps of:
providing a substrate, and forming a plurality of vertical channel structures extending upwards from the substrate, wherein each vertical channel structure comprises a pair of plane side surfaces oppositely arranged in an X direction and a pair of cambered surface side surfaces oppositely arranged in a Y direction, so that the cross section of each vertical channel structure is in a runway shape, the upwards extending direction of each vertical channel structure is set to be a Z direction, and the X direction, the Y direction and the Z direction are mutually perpendicular;
and forming a plurality of grid layers stacked in the Z direction, wherein the grid layers surround the periphery of the vertical channel structure, and the adjacent grid layers are isolated by insulating layers.
2. The method of manufacturing a three-dimensional junction-less semiconductor memory device of claim 1, wherein forming the vertical channel structure comprises:
forming a composite laminated structure on the substrate, wherein the composite laminated structure comprises the insulating layers and the sacrificial layers which are alternately stacked in the Z direction, and the uppermost layer of the composite laminated structure is the insulating layer;
forming a channel hole in the composite laminated structure, wherein the channel hole is opened from the top surface of the composite laminated structure and extends downwards to the surface of the substrate, and the cross section outline of the channel hole is in a runway shape;
and forming a channel material layer in the channel hole to obtain the vertical channel structure.
3. The method of manufacturing a three-dimensional junction-less semiconductor memory device according to claim 2, wherein: and replacing the sacrificial layer with a conductive layer to obtain the gate layer.
4. The method of manufacturing a three-dimensional junction-less semiconductor memory device according to claim 3, wherein the forming of the gate layer comprises the steps of:
forming a plurality of word line cuts in the composite laminated structure, wherein the word line cuts are opened from the top surface of the composite laminated structure and extend downwards to the surface of the substrate, and the word line cuts divide the plurality of vertical channel structures into a plurality of groups;
removing the sacrificial layer to obtain a plurality of transverse gaps separated by the insulating layer;
forming an information storage layer on the side of the vertical channel structure exposed by the lateral gap;
forming the conductive layer in the word line cut and the lateral gap;
and removing the part of the conductive layer in the word line cut, wherein the rest of the conductive layer in the lateral gap forms the gate layer.
5. The method of manufacturing a three-dimensional junction-less semiconductor memory device according to claim 4, wherein: the word line cuts extend in the Y direction.
6. The method of manufacturing a three-dimensional junction-less semiconductor memory device according to claim 4, wherein: when the information storage layer is formed on the side surface of the vertical channel structure exposed by the transverse gap, the information storage layer is also formed on the surface of the insulating layer exposed by the word line cut and the transverse gap.
7. The method of manufacturing a three-dimensional junction-less semiconductor memory device according to claim 4, wherein: the lowest layer of the composite laminated structure is the sacrificial layer, and when the information storage layer is formed on the side surface of the vertical channel structure exposed by the transverse gap, the information storage layer is also formed on the surface of the substrate exposed by the word line cut and the transverse gap.
8. The method of manufacturing a three-dimensional junction-less semiconductor memory device according to claim 7, wherein: and a source electrode connecting line is arranged in the substrate, and the projections of the source electrode connecting line and the vertical channel structure on the horizontal plane are not overlapped with each other.
9. The method of manufacturing a three-dimensional junction-less semiconductor memory device according to claim 4, wherein: the information storage layer comprises a tunneling dielectric layer, a charge trapping layer and a high-K dielectric layer, the tunneling dielectric layer is connected to the vertical channel structure, the high-K dielectric layer is connected to the gate electrode layer, the charge trapping layer is located between the tunneling dielectric layer and the high-K dielectric layer, and the dielectric constant K of the high-K dielectric layer is larger than 4.
10. The method of manufacturing a three-dimensional junction-less semiconductor memory device according to claim 4, wherein: further comprising the step of forming an isolation dielectric layer over the vertical channel structure, the isolation dielectric layer closing the top opening of the word line cut.
11. The method of manufacturing a three-dimensional junction-less semiconductor memory device according to claim 10, wherein: the isolation dielectric layer also fills into the word line cutouts.
12. The method according to claim 1, further comprising etching the insulating layer and the gate layer to form a step-and-step structure on at least one side of a stacked structure of the gate layers and the insulating layers.
13. The method of manufacturing a three-dimensional junction-less semiconductor memory device according to claim 12, wherein: the step of forming the word line connecting columns and the word line connecting lines is further included, the word line connecting lines are connected to the upper ends of the word line connecting columns, the step table of the stepped structure comprises the exposed surface of the insulating layer, the lower ends of the word line connecting columns penetrate through the step table and extend downwards to the surface of the grid layer, or the step table of the stepped structure comprises the exposed surface of the grid layer, and the lower ends of the word line connecting columns are connected to the step table.
14. The method of manufacturing a three-dimensional junction-less semiconductor memory device according to claim 12, wherein: and sequentially etching the plurality of insulating layers and the plurality of gate electrode layers by using the masks which are sequentially reduced or increased to obtain the stepped step structure.
15. The method of manufacturing a three-dimensional junction-less semiconductor memory device according to claim 1, wherein: further comprising the step of forming a bit line contact connected to a top end of the vertical channel structure and a bit line connected to a top end of the bit line contact.
16. The method of manufacturing a three-dimensional junction-less semiconductor memory device according to claim 1, wherein: the method further comprises a step of forming an upper conductive connecting portion or a lower conductive connecting portion, wherein the upper conductive connecting portion connects the two layers of the grid layer located at the topmost layer and the second-to-top layer, and the lower conductive connecting portion connects the two layers of the grid layer located at the bottommost layer and the second-to-bottom layer.
17. A three-dimensional, junctionless semiconductor memory device, comprising:
a substrate;
a plurality of vertical channel structures extending upward from the substrate, the vertical channel structures including a pair of planar side surfaces oppositely disposed in an X-direction and a pair of arc side surfaces oppositely disposed in a Y-direction, such that cross-sectional shapes of the vertical channel structures are racetrack-shaped, wherein a direction in which the vertical channel structures extend upward is set as a Z-direction, and the X-direction, the Y-direction, and the Z-direction are perpendicular to each other;
and the grid layers are stacked in the Z direction, surround the periphery of the vertical channel structure, and are isolated by insulating layers.
18. The three-dimensional junction-free semiconductor memory device according to claim 17, wherein: the three-dimensional junction-free semiconductor memory device further includes word line cutouts that vertically penetrate the gate layer and the insulating layer to divide the plurality of vertical channel structures into a plurality of groups.
19. The three-dimensional junction-free semiconductor memory device according to claim 18, wherein: the word line cuts extend in the Y direction.
20. The three-dimensional junction-free semiconductor memory device according to claim 18, wherein: the three-dimensional junction-free semiconductor memory device further includes an isolation dielectric layer located over the vertical channel structure and closing a top opening of the word line cut.
21. The three-dimensional junction-free semiconductor memory device according to claim 20, wherein: the isolation dielectric layer also fills into the word line cutouts.
22. The three-dimensional junction-free semiconductor memory device according to claim 17, wherein: the three-dimensional junctionless semiconductor memory device further comprises a plurality of word line connecting columns and a plurality of word line connecting lines, wherein the word line connecting lines are connected to the upper ends of the word line connecting columns, at least one side of a stacked structure formed by the gate electrode layers and the insulating layers forms a stepped structure, a stepped mesa of the stepped structure comprises an exposed surface of the insulating layer, the lower ends of the word line connecting columns penetrate through the stepped mesa and extend downwards to the surface of the gate electrode layer, or the stepped mesa of the stepped structure comprises the exposed surface of the gate electrode layer, and the lower ends of the word line connecting columns are connected to the stepped mesa.
23. The three-dimensional junction-free semiconductor memory device according to claim 17, wherein: the three-dimensional junction-free semiconductor memory device further includes an information storage layer between the vertical channel structure and the gate layer.
24. The three-dimensional junction-less semiconductor memory device of claim 21, wherein: the information storage layer is also located between the insulating layer and the gate layer.
25. The three-dimensional junction-less semiconductor memory device of claim 21, wherein: the information storage layer is also located between the gate layer and the substrate.
26. The three-dimensional junction-free semiconductor memory device according to claim 17, wherein: the three-dimensional junction-less semiconductor memory device further includes a bit line contact connected to a top end of the vertical channel structure and a bit line connected to a top end of the bit line contact.
27. The three-dimensional junction-free semiconductor memory device according to claim 17, wherein: the three-dimensional junction-free semiconductor memory device further comprises an upper conductive connecting part or a lower conductive connecting part, wherein the upper conductive connecting part connects the two gate layers positioned at the topmost layer and the next-to-topmost layer, and the lower conductive connecting part connects the two gate layers positioned at the bottommost layer and the next-to-bottommost layer.
28. A method of operating a three-dimensional junction-less semiconductor memory device as claimed in any one of claims 17 to 27, wherein:
applying a channel voltage V to the vertical channel structure of the memory string having the selected memory cell during a programming operationcApplying a first gate voltage V to the gate layer of the selected memory cellg1Applying a second gate voltage V to the gate layer of unselected memory cells in the memory stringg2Wherein V isg1Selected from the first programming voltage V1A second programming voltage V2A third programming voltage V3A fourth programming voltage V4A fifth programming voltage V5A sixth programming voltage V6A seventh programming voltage V7And an eighth programming voltage V8To obtain any one of the memory states 000, 001, 010, 011, 100, 101, 110, 111, V1＝0V，0V<Vg2<V2<V3<V4<V5<V6<V7<V7<V8，0.5V≤V8≤10V，-3V≤Vc≤-10V。
29. The method of operating a three-dimensional, junction-less semiconductor memory device of claim 28, wherein:
applying a channel voltage V to the vertical channel structure of the memory string having the selected memory cell during an erase operationc', for the selected memory cellApplying an erase voltage V to the gate layereFloating the gate layer of unselected memory cells in the memory string, wherein 3V ≦ Vc’≤10V，-3V≤Ve≤-10V。
Technical Field
The invention belongs to the technical field of semiconductor integrated circuits, and relates to a three-dimensional junction-free semiconductor memory device, and a manufacturing method and an operating method thereof.
Background
The demand for inexpensive semiconductor devices with high performance continues to push integration density. In turn, increased integration density places higher demands on semiconductor manufacturing processes. The integration density of two-dimensional (2D) or planar semiconductor devices is determined in part by the area occupied by the individual elements (e.g., memory cells) that make up the integrated circuit. The area occupied by the individual elements is largely determined by the dimensional parameters (e.g., width, length, pitch, narrowness, adjacent spacing, etc.) of the patterning technique used to define the individual elements and their interconnections. In recent years, providing increasingly "fine" patterns requires the development and use of very expensive patterning devices. Therefore, significant improvements in integration density of contemporary semiconductor devices have been made at considerable expense, yet designers are still competing with the practical boundaries of fine pattern development and fabrication.
Due to the foregoing and many related manufacturing challenges, the recent increase in integration density has required the development of multilayer or so-called three-dimensional (3D) semiconductor devices. For example, the single fabrication layer traditionally associated with memory cell arrays of two-dimensional (2D) semiconductor memory devices is being replaced by multiple fabrication layers or three-dimensional (3D) arrangements of memory cells. The Single-Level Cell (SLC) means that each memory Cell only stores 1-bit (1bit) information, and outputs data depending on the presence or absence of an electron capture state in a floating gate (even in a 0 state, electrons are still present in the floating gate but not much), that is, the simplest 0 and 1. Multi-Level Cell (MLC) means that each memory Cell can store two-bit (2-bit) information, and the amount of electrons in the floating gate is divided into four states, i.e. high, medium, low and none, and becomes 00, 01, 10 and 11 after being converted into binary system. The Triple-Level Cell (TLC) further divides the electron capture states in the floating gate into eight types, which are converted into binary 000, 001, 010, 011, 100, 101, 110, and 111, that is, three bits (3 bits).
The memory has experienced ETOX floating gate Charge storage Flash memory in 1971, Charge Trap Flash (CTF) in 2006, or so-called SONOS cell-Si/SiO/SiN/SiO/Si, up to three-dimensional vertical NAND in 2013, using polysilicon cylinders as the substrate silicon, with SONOS stacks oriented vertically, and others layered around the center cylinder.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a three-dimensional junction-less semiconductor memory device, a method for manufacturing the same, and a method for operating the same, which are used to solve the problem that the integration density of the conventional semiconductor memory device is to be improved.
To achieve the above and other related objects, the present invention provides a method of fabricating a three-dimensional junction-less semiconductor memory device, comprising the steps of:
providing a substrate, and forming a plurality of vertical channel structures extending upwards from the substrate, wherein each vertical channel structure comprises a pair of plane side surfaces oppositely arranged in an X direction and a pair of cambered surface side surfaces oppositely arranged in a Y direction, so that the cross section of each vertical channel structure is in a runway shape, the upwards extending direction of each vertical channel structure is set to be a Z direction, and the X direction, the Y direction and the Z direction are mutually perpendicular;
and forming a plurality of grid layers stacked in the Z direction, wherein the grid layers surround the periphery of the vertical channel structure, and the adjacent grid layers are isolated by insulating layers.
Optionally, the forming the vertical channel structure comprises the following steps:
forming a composite laminated structure on the substrate, wherein the composite laminated structure comprises the insulating layers 301 and the sacrificial layers 302 which are alternately stacked in the Z direction, and the uppermost layer of the composite laminated structure is the insulating layer;
forming a channel hole in the composite laminated structure, wherein the channel hole is opened from the top surface of the composite laminated structure and extends downwards to the surface of the substrate, and the cross section outline of the channel hole is in a runway shape;
and forming a channel material layer in the channel hole to obtain the vertical channel structure.
Optionally, the sacrificial layer is replaced with a conductive layer to obtain the gate layer.
Optionally, forming the gate layer comprises:
forming a plurality of word line cuts in the composite laminated structure, wherein the word line cuts are opened from the top surface of the composite laminated structure and extend downwards to the surface of the substrate, and the word line cuts divide the plurality of vertical channel structures into a plurality of groups;
removing the sacrificial layer to obtain a plurality of transverse gaps separated by the insulating layer;
forming an information storage layer on the side of the vertical channel structure exposed by the lateral gap;
forming the conductive layer in the word line cut and the lateral gap;
and removing the part of the conductive layer in the word line cut, wherein the rest of the conductive layer in the lateral gap forms the gate layer.
Optionally, the wordline cuts extend in the Y-direction.
Optionally, when the information storage layer is formed on the side surface of the vertical channel structure exposed by the lateral gap, the information storage layer is further formed on the surface of the insulating layer exposed by the word line cut and the lateral gap.
Optionally, the lowest layer of the composite stacked structure is the sacrificial layer, and when the information storage layer is formed on the side surface of the vertical channel structure exposed by the lateral gap, the information storage layer is further formed on the surface of the substrate exposed by the word line cut and the lateral gap.
Optionally, a source connection line is disposed in the substrate, and projections of the source connection line and the vertical channel structure on a horizontal plane are not overlapped with each other.
Optionally, the information storage layer includes a tunneling dielectric layer, a charge-trapping layer and a high-K dielectric layer, the tunneling dielectric layer is connected to the vertical channel structure, the high-K dielectric layer is connected to the gate layer, the charge-trapping layer is located between the tunneling dielectric layer and the high-K dielectric layer, and a dielectric constant K of the high-K dielectric layer is greater than 4.
Optionally, the method further comprises a step of forming an isolation dielectric layer over the vertical channel structure, wherein the isolation dielectric layer closes the top opening of the word line cut.
Optionally, the isolation dielectric layer also fills in the word line cut.
Optionally, the method further includes a step of etching the insulating layer and the gate layer to form a step structure on at least one side of a stacked structure formed by the gate layers and the insulating layers.
Optionally, the method further includes the step of forming a plurality of word line connection pillars and a plurality of word line connection lines, the word line connection lines are connected to the upper ends of the word line connection pillars, the step mesa of the stepped structure includes the exposed surface of the insulating layer, the lower ends of the word line connection pillars penetrate through the step mesa and extend downward to the surface of the gate layer, or the step mesa of the stepped structure includes the exposed surface of the gate layer, and the lower ends of the word line connection pillars are connected to the step mesa.
Optionally, the plurality of insulating layers and the plurality of gate layers are sequentially etched by using masks which are sequentially reduced or increased, so that the stepped step structure is obtained.
Optionally, the method further comprises the step of forming a bit line contact and a bit line, wherein the bit line contact is connected to the top end of the vertical channel structure, and the bit line is connected to the top end of the bit line contact.
Optionally, the method further includes a step of forming an upper conductive connection portion or a lower conductive connection portion, where the upper conductive connection portion connects the two gate layers located at the topmost layer and the next-to-topmost layer, and the lower conductive connection portion connects the two gate layers located at the bottommost layer and the next-to-bottommost layer.
The present invention also provides a three-dimensional junction-less semiconductor memory device, comprising:
a substrate;
a plurality of vertical channel structures extending upward from the substrate, the vertical channel structures including a pair of planar side surfaces oppositely disposed in an X-direction and a pair of arc side surfaces oppositely disposed in a Y-direction, such that cross-sectional shapes of the vertical channel structures are racetrack-shaped, wherein a direction in which the vertical channel structures extend upward is set as a Z-direction, and the X-direction, the Y-direction, and the Z-direction are perpendicular to each other;
and the grid layers are stacked in the Z direction, surround the periphery of the vertical channel structure, and are isolated by insulating layers.
Optionally, the three-dimensional junction-less semiconductor memory device further comprises word line cuts vertically penetrating the gate layer and the insulating layer to divide the plurality of vertical channel structures into a plurality of groups.
Optionally, the wordline cuts extend in the Y-direction.
The three-dimensional junction-free semiconductor memory device according to claim 18, wherein: the three-dimensional junction-free semiconductor memory device further includes an isolation dielectric layer located over the vertical channel structure and closing a top opening of the word line cut.
Optionally, the isolation dielectric layer also fills in the word line cut.
Optionally, the three-dimensional junction-less semiconductor memory device further includes a plurality of word line connection pillars and a plurality of word line connection lines, the word line connection lines are connected to upper ends of the word line connection pillars, at least one side of a stacked structure formed by the plurality of gate layers and the plurality of insulating layers forms a stepped structure, a step mesa of the stepped structure includes an exposed surface of the insulating layer, a lower end of the word line connection pillar passes through the step mesa and extends downward to a surface of the gate layer, or the step mesa of the stepped structure includes an exposed surface of the gate layer, and a lower end of the word line connection pillar is connected to the step mesa.
Optionally, the three-dimensional junction-less semiconductor memory device further comprises an information storage layer located between the vertical channel structure and the gate layer.
Optionally, the information storage layer is further located between the insulating layer and the gate layer.
Optionally, the information storage layer is further located between the gate layer and the substrate.
Optionally, the three-dimensional junction-less semiconductor memory device further comprises a bit line contact and a bit line, the bit line contact is connected to a top end of the vertical channel structure, and the bit line is connected to a top end of the bit line contact.
Optionally, the three-dimensional junction-less semiconductor memory device further includes an upper conductive connection portion connecting the two gate layers located at the topmost layer and the next-to-topmost layer, or a lower conductive connection portion connecting the two gate layers located at the bottommost layer and the next-to-bottom layer.
The present invention also provides an operating method of a three-dimensional junction-less semiconductor memory device, in which:
applying a channel voltage V to the vertical channel structure of the memory string having the selected memory cell during a programming operationcApplying a first gate voltage V to the gate layer of the selected memory cellg1Applying a second gate voltage V to the gate layer of unselected memory cells in the memory stringg2Wherein V isg1Selected from the first programming voltage V1A second programming voltage V2A third programming voltage V3A fourth programming voltage V4A fifth programming voltage V5A sixth programming voltage V6A seventh programming voltage V7And an eighth programming voltage V8To obtain any one of the memory states 000, 001, 010, 011, 100, 101, 110, 111, V1＝0V，0V<Vg2<V2<V3<V4<V5<V6<V7<V7<V8，0.5V≤V8≤10V，-3V≤Vc≤-10V。
Optionally, in an erase operation, a channel voltage V is applied to the vertical channel structure of the memory string in which the selected memory cell is locatedc' applying an erase voltage V to the gate layer of a selected memory celleFloating the gate layer of unselected memory cells in the memory string, wherein 3V ≦ Vc’≤10V，-3V≤Ve≤-10V。
As described above, the three-dimensional junction-less semiconductor memory device of the present invention has a vertical channel structure including a pair of planar side surfaces oppositely disposed in an X direction and a pair of arc side surfaces oppositely disposed in a Y direction, such that a cross-sectional shape of the vertical channel structure is racetrack-shaped, and a plurality of gate layers stacked in the vertical direction, the gate layers surrounding the vertical channel structure. Compared with the round and other non-corner shapes, the runway-type channel has a relatively larger perimeter, so that the contact area between the grid layer and the information storage layer is correspondingly increased, the coupling efficiency of the control word line grid and the channel is improved, and the reliability of the device can be improved. Under the same grid voltage, the constraint capacity of the grid layer on the charges in the charge trapping layer is enhanced, the charges are not easy to leak, the retention time of the charges in the storage unit can be effectively prolonged, and the storage performance of the storage unit is improved. The charge trapping layer covers three sides (upper surface, side surface and lower surface) of the gate layer, and can further increase the distributable region of trapped electrons on the basis of increasing the contact area of the channel-type structure, so that the memory cell can present more electron quantity states, and different electron quantity states can be easily distinguished, thereby realizing excellent three-dimensional control capability and increasing the storage capacity of the device.
Drawings
Fig. 1 shows a process flow diagram of a method of fabricating a three-dimensional junction-less semiconductor memory device according to the present invention.
Fig. 2 is a schematic diagram illustrating a method for fabricating a three-dimensional junction-less semiconductor memory device according to the present invention, in which a composite stacked structure is formed on the substrate.
Fig. 3 is a schematic view illustrating the formation of a channel hole in the composite stacked structure according to the method for fabricating a three-dimensional junction-less semiconductor memory device of the present invention.
Fig. 4 is a schematic diagram illustrating a method of fabricating a three-dimensional junction-less semiconductor memory device according to the present invention, in which a channel material layer is formed in the channel hole.
Fig. 5 is a schematic diagram illustrating the formation of a plurality of word line cuts in the composite stacked structure according to the method for fabricating a three-dimensional junction-free semiconductor memory device of the present invention.
Fig. 6 is a schematic view showing the removal of the sacrificial layer for the method of fabricating the three-dimensional junction-less semiconductor memory device according to the present invention.
Fig. 7 is a schematic view illustrating a method of fabricating a three-dimensional junction-less semiconductor memory device according to the present invention, in which an information storage layer is formed on a side surface of the vertical channel structure exposed by the lateral gap.
Fig. 8 is a schematic view illustrating a method of fabricating a three-dimensional junction-less semiconductor memory device according to the present invention, in which a conductive layer is formed in the word line cut and the lateral gap.
Fig. 9 is a schematic view showing a method of fabricating a three-dimensional junction-less semiconductor memory device according to the present invention, in which portions of the conductive layer located in the word line cutouts are removed.
Fig. 10 is a cross-sectional view showing a memory cell in the three-dimensional junction-less semiconductor memory device of the present invention.
Fig. 11 is a longitudinal sectional view showing a memory string in the three-dimensional junction-less semiconductor memory device of the present invention.
Fig. 12 is a schematic diagram illustrating a step structure, a bit line contact and a bit line formed by the method for fabricating a three-dimensional junction-less semiconductor memory device according to the present invention.
Fig. 13 is a perspective view of a three-dimensional junction-less semiconductor memory device of the present invention in another embodiment.
Fig. 14 is a cross-sectional view of a three-dimensional junction-less semiconductor memory device of the present invention in another embodiment.
Description of the element reference numerals
1 substrate
2 source electrode connecting wire
3 composite laminated structure
301 insulating layer
302 sacrificial layer
4 channel hole
5 vertical channel structure
6 word line cut
7 transverse gap
8 information storage layer
801 tunneling dielectric layer
802 charge trapping layer
803 high-K dielectric layer
9 conductive layer
10 grid layer
11 bit line contact
12 bit line
13 word line connection
14 word line connecting line
15 isolation dielectric layer
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 14. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
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