阅读说明：本技术 一种集成电路计算设备及计算处理系统 (Integrated circuit computing device and computing processing system ) 是由 古生霖 王黎明 孟智凯 贾红 陈维新 韦嶔 程显志 于 2020-02-19 设计创作，主要内容包括：本发明公开了一种集成电路计算设备,包括：第一处理模块,用于接收并处理RISC-V指令集指令,其中所述RISC-V指令集指令包括基本指令、扩展指令以及自定义指令；第二处理模块,其包括软核协处理器,所述软核协处理器通过第一接口连接所述第一处理模块,用于处理所述第一处理模块发送的所述自定义指令；第一总线,连接所述第一处理模块和所述第二处理模块；以及连接所述第一处理模块的第一端口和连接所述第二处理模块的第二端口。本发明通过在FPGA芯片中嵌入RISC-V架构硬核处理器,并在FPGA芯片的可编程部分设计了软核协处理器,使得FPGA芯片开发人员可以根据需要灵活的对处理器内核进行调整,从而增强了FPGA芯片的计算能力且保证设备面积小、功耗低、制造成本低。(The invention discloses an integrated circuit computing device, comprising: the first processing module is used for receiving and processing RISC-V instruction set instructions, wherein the RISC-V instruction set instructions comprise basic instructions, extended instructions and custom instructions; the second processing module comprises a soft core coprocessor, the soft core coprocessor is connected with the first processing module through a first interface and is used for processing the self-defined instruction sent by the first processing module; a first bus connecting the first processing module and the second processing module; and a first port connected to the first processing module and a second port connected to the second processing module. According to the invention, the RISC-V architecture hard core processor is embedded in the FPGA chip, and the soft core coprocessor is designed in the programmable part of the FPGA chip, so that the FPGA chip developer can flexibly adjust the processor core as required, thereby enhancing the computing capability of the FPGA chip and ensuring small equipment area, low power consumption and low manufacturing cost.)

1. An integrated circuit computing device, comprising:

the first processing module is used for receiving and processing RISC-V instruction set instructions, wherein the RISC-V instruction set instructions comprise basic instructions, extended instructions and custom instructions;

the second processing module comprises a soft core coprocessor, the soft core coprocessor is connected with the first processing module through a first interface and is used for processing the self-defined instruction sent by the first processing module;

a first bus connecting the first processing module and the second processing module; and

the first port connected with the first processing module and the second port connected with the second processing module.

2. The integrated-circuit computing device of claim 1, wherein the first processing module comprises: RISC-V instruction set processor, memory cell, peripheral extension unit;

the RISC-V instruction set processor is connected with the storage unit and the peripheral extension unit through a first bus, and is also connected with the soft core coprocessor through the first interface.

3. The integrated-circuit computing device of claim 2, wherein the first interface comprises:

a kernel control group signal comprising a control signal or a state signal which is sent and received by the RISC-V instruction set processor to the soft core coprocessor;

instruction register set signals including instruction signals sent by the RISC-V instruction set processor to the soft core coprocessor and received response signals;

memory bank signals including data signals sent and received by the cache of the RISC-V instruction set processor to the soft core coprocessor;

and the user-defined group signal comprises a user-defined instruction signal sent to the soft core coprocessor by the RISC-V instruction set processor and a received response signal.

4. The integrated-circuit computing device of claim 1, wherein the device further comprises:

the first debugging port is connected with the first processing module, and the second debugging port is connected with the second processing module.

5. The integrated-circuit computing device of claim 4, wherein the first processing module further comprises: and the first test access interface is connected with the RISC-V instruction set processor and the first debugging port.

6. The integrated-circuit computing device of claim 4, wherein the second processing module comprises:

the programmable logic gate array is connected with the configuration block, the configuration block is connected with the second test access interface, and the second test access interface is connected with the second debugging port.

7. The integrated circuit computing device of claim 6, wherein the second test access interface is a JTAG interface.

8. The integrated circuit computing device of claim 3, wherein the first bus interface protocol comprises an AMBA protocol or a Tile L ink protocol.

9. The integrated-circuit computing device of claim 1, wherein RISC-V instruction set processor comprises a CPU, GPU, DSP, or hardware accelerator.

10. A computing processing system comprising a host, further comprising the integrated circuit computing device of any of claims 1-9 coupled to the host.

Technical Field

The invention belongs to the field of system-level chip design, and particularly relates to integrated circuit computing equipment and a computing processing system.

Background

Currently, in an FPGA (Field Programmable Gate Array) design, a processor hard core or a processor soft core is usually embedded, that is, an ASIC (application specific Integrated Circuit) Circuit of a processor is embedded inside an FPGA chip, or a processor is implemented on a Programmable logic of an FPGA in a manner of HD L (Hardware Description L language) program codes.

However, FPGAs with embedded processor hardcores are commercial IP cores such as ARM (Advanced RISC Machine), PowerPC, etc., and the use of commercial IP greatly increases the use cost of the FPGA user, on one hand, the cost of the FPGA itself is increased, and on the other hand, when the user wants to convert the design on the FPGA into an ASIC (Application specific integrated Circuit) design, the user still needs to pay extra IP use cost; secondly, the internal design details of most commercial IP cores (internal Property cores) are invisible, which cannot meet the requirements of application scenes (such as security scenes of national defense and military industry) with the requirement that the chips are completely safe and controllable; thirdly, the design flexibility of the commercial IP is poor, on one hand, the instruction set of the processor is fixed, and a user cannot add a custom instruction to optimize the product performance; on the other hand, once a certain IP core is selected, the subsequent product upgrading is limited by the IP capability. The FPGA using the soft core needs to occupy logic resources on the FPGA when the soft core is implemented, and occupies a large power consumption, a large area, and a lower computing power compared with the hard core, so that the FPGA cannot meet application requirements of high precision and high real-time performance, and is relatively poor in practicability.

Disclosure of Invention

In order to solve the above problems in the prior art, the present invention provides an integrated circuit computing device and a computing processing system. The technical problem to be solved by the invention is realized by the following technical scheme:

an embodiment of the present invention provides an integrated circuit computing device, including:

the first processing module is used for receiving and processing RISC-V instruction set instructions, wherein the RISC-V instruction set instructions comprise basic instructions, extended instructions and custom instructions;

the second processing module comprises a soft core coprocessor, the soft core coprocessor is connected with the first processing module through a first interface and is used for processing the self-defined instruction sent by the first processing module;

a first bus connecting the first processing module and the second processing module; and

the first port connected with the first processing module and the second port connected with the second processing module.

In one embodiment, the first processing module comprises: RISC-V instruction set processor, memory cell, peripheral extension unit;

the RISC-V instruction set processor is connected with the storage unit and the peripheral extension unit through a first bus, and is also connected with the soft core coprocessor through the first interface.

In one embodiment, the first interface comprises:

a kernel control group signal comprising a control signal or a state signal which is sent and received by the RISC-V instruction set processor to the soft core coprocessor;

instruction register set signals including instruction signals sent by the RISC-V instruction set processor to the soft core coprocessor and received response signals;

memory bank signals including data signals sent and received by the cache of the RISC-V instruction set processor to the soft core coprocessor;

and the user-defined group signal comprises a user-defined instruction signal sent to the soft core coprocessor by the RISC-V instruction set processor and a received response signal.

In one embodiment, the apparatus further comprises:

the first debugging port is connected with the first processing module, and the second debugging port is connected with the second processing module.

In one embodiment, the first processing module further comprises: and the first test access interface is connected with the RISC-V instruction set processor and the first debugging port.

In one embodiment, the first test access interface is a JTAG interface.

In one embodiment, the second processing module comprises:

the programmable logic gate array is connected with the configuration block, the configuration block is connected with the second test access interface, and the second test access interface is connected with the second debugging port.

In one embodiment, the second test access interface is a JTAG interface.

In one embodiment, the first bus interface protocol includes AMBA protocol or Tile L ink protocol.

In one embodiment, the RISC-V instruction set processor includes a CPU, GPU, DSP, or hardware accelerator.

An embodiment of the present invention also provides a computing processing system, which includes a host and the integrated circuit computing device coupled to the host.

Compared with the prior art, the invention has the beneficial effects that:

the embodiment of the invention embeds the RISC-V architecture hard core processor in the FPGA chip, designs the soft core coprocessor in the programmable part of the FPGA chip, and the coprocessor can help the RISC-V hard core processor to realize the standard extension instruction set and the user-defined extension instruction of the RISC-V instruction set, so that the FPGA chip developer can flexibly adjust the processor core according to the requirement, thereby enhancing the computing capability of the FPGA chip and ensuring small equipment area, low power consumption and low manufacturing cost.

Drawings

FIG. 1 is a block diagram of an integrated circuit computing device module according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of an integrated circuit computing device according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a first interface design of an integrated circuit computing device according to an embodiment of the present invention;

FIG. 4 is a diagram illustrating an embodiment of signals of a first interface of an integrated circuit computing device.

Detailed Description

The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.