阅读说明：本技术 三维存储器件结构及形成方法 (Three-dimensional memory device structure and forming method ) 是由 李思晢 张磊 高晶 曾凡清 周文斌 于 2020-03-18 设计创作，主要内容包括：本发明提供了一种三维存储器件结构及形成方法,所述形成方法的特征在于：在基底上形成有多个存储堆叠结构,相邻的所述存储堆叠结构之间通过设置切割道进行分隔,在所述切割道中形成有虚设图形结构,光刻对准图形形成于所述虚设图形结构与所述存储堆叠结构之间。本发明在三维存储器件结构的形成过程中,通过在切割道中引入虚设图形结构,将光刻对准图形形成于所述虚设图形结构与所述存储堆叠结构之间,使所述光刻对准图形不会因热处理等工艺过程的应力影响而产生偏移,确保光刻工艺的对准精度。(The invention provides a three-dimensional memory device structure and a forming method, wherein the forming method is characterized in that: the method comprises the steps that a plurality of storage stacking structures are formed on a substrate, adjacent storage stacking structures are separated through arrangement of cutting channels, dummy pattern structures are formed in the cutting channels, and photoetching alignment patterns are formed between the dummy pattern structures and the storage stacking structures. In the forming process of the three-dimensional memory device structure, the dummy pattern structure is introduced into the cutting channel, and the photoetching alignment pattern is formed between the dummy pattern structure and the memory stacking structure, so that the photoetching alignment pattern is not deviated due to the stress influence of the process procedures such as heat treatment and the like, and the alignment precision of the photoetching process is ensured.)

1. A method for forming a three-dimensional memory device structure, comprising: the method comprises the steps that a plurality of storage stacking structures are formed on a substrate, adjacent storage stacking structures are separated through arrangement of cutting channels, dummy pattern structures are formed in the cutting channels, and photoetching alignment patterns are formed between the dummy pattern structures and the storage stacking structures.

2. The method of forming a three-dimensional memory device structure of claim 1, wherein: the dummy pattern structure and the storage stack structure have the same alternating layer stack structure.

3. The method of forming a three-dimensional memory device structure of claim 2, wherein: the alternating layer stacking structure is formed by alternately stacking silicon nitride layers and silicon oxide layers.

4. The method of forming a three-dimensional memory device structure of claim 2, wherein: the dummy pattern structure and a peripheral portion of the memory stack structure are formed with a step structure.

5. The method of forming a three-dimensional memory device structure of claim 4, wherein: the formation process of the dummy pattern structure and the storage stack structure includes the following steps:

forming an alternating layer stack structure on the substrate;

and synchronously forming the dummy pattern structure containing the step structure and the storage stacking structure by etching.

6. The method of forming a three-dimensional memory device structure of claim 5, wherein: after forming the dummy pattern structure and the memory stack structure, further comprising the steps of:

depositing a capping dielectric layer in and over the gap between the dummy pattern structure and the memory stack structure;

removing the covering dielectric layer above the dummy pattern structure and other areas except the area where the step structure is located in the storage stacking structure by photoetching and etching;

and removing a part of the covering dielectric layer higher than the dummy pattern structure and the top of the storage stack structure by chemical mechanical polishing.

7. The method of forming a three-dimensional memory device structure of claim 1, wherein: at least one centerline of the dummy pattern structure passes through a center region of an adjacent at least one of the storage stack structures.

8. A three-dimensional memory device structure, characterized by: the method comprises the following steps:

a substrate;

a plurality of storage stacking structures formed on the substrate, wherein adjacent storage stacking structures are separated by arranging a cutting channel;

a dummy pattern structure formed on the substrate, the dummy pattern structure being located in the scribe line;

a lithographic alignment pattern formed between the dummy pattern structure and the storage stack structure.

9. The three-dimensional memory device structure of claim 8, wherein: the dummy pattern structure and the storage stack structure have the same alternating layer stack structure.

10. The three-dimensional memory device structure of claim 9, wherein: the alternating layer stacking structure is formed by alternately stacking silicon nitride layers and silicon oxide layers.

11. The three-dimensional memory device structure of claim 9, wherein: the dummy pattern structure and a peripheral portion of the memory stack structure are formed with a step structure.

12. The three-dimensional memory device structure of claim 8, wherein: at least one centerline of the dummy pattern structure passes through a center region of an adjacent at least one of the storage stack structures.

Technical Field

The present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly, to a three-dimensional memory device structure and a method of forming the same.

Background

In the process of manufacturing the 3D NAND memory, as the number of stacked layers is increased, the etching aspect ratio of the channel hole is increased, which results in an increase in difficulty of the etching process.

At present, in order to solve the problem of the reduction of the etching process window caused by the increase of the number of stacked layers, the existing process adopts a process of forming a channel hole by two-step etching. And two through holes obtained by two times of etching are connected up and down to form a channel hole. Therefore, the difficulty of the channel hole etching process is greatly reduced, and the etching process window is improved.

However, the above process places new demands on the alignment of the lithography. In the above process, two through holes designed to be connected up and down need to be accurately aligned in the formation process thereof to form a complete channel hole. The precise alignment of the through holes is mainly realized by the alignment of the alignment patterns in the through hole photoetching process. The alignment pattern is generally disposed in a scribe line of the wafer, and the thermal expansion coefficients of the dielectric layer material deposited in the scribe line and the device region material are often greatly different. The above difference causes a large shift in the position of the alignment pattern due to the imbalance of stress after the heat treatment process. This offset will seriously affect the alignment of via lithography, which in turn affects device performance and product yield.

Therefore, there is a need for a new three-dimensional memory device structure and method for forming the same that solves the above-mentioned problems.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, it is an object of the present invention to provide a three-dimensional memory device structure and a method for forming the same, which are used to solve the problem of the prior art that the alignment pattern affects the lithography alignment due to the deviation of the thermal process.

In order to achieve the above and other related objects, the present invention provides a method for forming a three-dimensional memory device structure, wherein a plurality of memory stack structures are formed on a substrate, adjacent memory stack structures are separated by a scribe line, a dummy pattern structure is formed in the scribe line, and a photolithography alignment pattern is formed between the dummy pattern structure and the memory stack structures.

As an alternative of the invention, the dummy pattern structure and the memory stack structure have the same alternating layer stack structure.

As an alternative of the present invention, the alternating layer stack structure is formed by alternately stacking silicon nitride layers and silicon oxide layers.

As an alternative of the present invention, the dummy pattern structure and the peripheral portion of the memory stack structure are formed with a step structure.

As an alternative of the present invention, the process of forming the dummy pattern structure and the memory stack structure includes the steps of:

depositing a capping dielectric layer in and over the gap between the dummy pattern structure and the memory stack structure;

removing the covering dielectric layer above the dummy pattern structure and other areas except the area where the step structure is located in the storage stacking structure by photoetching and etching;

and removing a part of the covering dielectric layer higher than the dummy pattern structure and the top of the storage stack structure by chemical mechanical polishing.

As an alternative of the invention, at least one center line of the dummy pattern structure passes through a center area of an adjacent at least one of the storage stack structures.

The invention also provides a three-dimensional memory device structure, which is characterized in that: the method comprises the following steps:

a substrate;

a plurality of storage stacking structures formed on the substrate, wherein adjacent storage stacking structures are separated by arranging a cutting channel;

a dummy pattern structure formed on the substrate, the dummy pattern structure being located in the scribe line;

a lithographic alignment pattern formed between the dummy pattern structure and the storage stack structure.

As an alternative of the invention, the dummy pattern structure and the memory stack structure have the same alternating layer stack structure.

As an alternative of the present invention, the alternating layer stack structure is formed by alternately stacking silicon nitride layers and silicon oxide layers.

As an alternative of the present invention, the dummy pattern structure and the peripheral portion of the memory stack structure are formed with a step structure.

As an alternative of the invention, at least one center line of the dummy pattern structure passes through a center area of an adjacent at least one of the storage stack structures.

As described above, the present invention provides a three-dimensional memory device structure and a forming method thereof, which have the following advantages:

according to the invention, by introducing a novel three-dimensional memory device structure and a forming method, in the forming process of the three-dimensional memory device structure, the dummy pattern structure is introduced into the cutting channel, and the photoetching alignment pattern is formed between the dummy pattern structure and the memory stacking structure, so that the photoetching alignment pattern is not deviated due to the stress influence of the processes such as heat treatment and the like, and the alignment precision of the photoetching process is ensured.

Drawings

Fig. 1 is a top view of a partial area of a three-dimensional memory device arrangement on a wafer surface according to the prior art.

Fig. 2 is a schematic cross-sectional view of the region a in fig. 1 taken along the direction BB'.

Fig. 3 is a top view of a partial area of a three-dimensional memory device arrangement on a wafer surface according to an embodiment of the invention.

Fig. 4 is a schematic sectional view of the region C in fig. 3 taken along the direction DD'.

Fig. 5 is a schematic cross-sectional view illustrating a trench hole structure obtained by vertically aligning two layers of through holes after etching according to an embodiment of the present invention.

Fig. 6 is a schematic cross-sectional view illustrating the formation of a dummy pattern structure and a memory stack structure on a substrate according to a first embodiment of the invention.

Fig. 7 is a schematic cross-sectional view illustrating a dielectric capping layer deposited in the gap between the dummy pattern structure and the memory stack structure and over the dummy pattern structure according to one embodiment of the present invention.

Fig. 8 is a schematic cross-sectional view illustrating the dummy pattern structure and the capping dielectric layer over the other region except the region where the step structure is located in the memory stack structure according to the first embodiment of the present invention.

Fig. 9 is a top view of a partial area of a three-dimensional memory device arrangement on a wafer surface according to a second embodiment of the invention.

Fig. 10 is a top view of a partial area of a three-dimensional memory device arrangement on a wafer surface according to a second embodiment of the invention.

Fig. 11 is a top view of a partial area of a three-dimensional memory device arrangement on a wafer surface according to a second embodiment of the invention.

Description of the element reference numerals

100 substrate

101 storage stack structure

102 cutting line

103 lithographic alignment pattern

104 cover dielectric layer

200 substrate

201 storage stack structure

201a step structure

202 cutting path

203 photo-etching alignment pattern

204 cover the dielectric layer

205 dummy pattern structure

205a step structure

206 second storage stack structure

207 first through hole

208 second through hole

301 storage stack structure

302 cutting line

303 photoetching alignment pattern

305 dummy pattern structure

401 storage stack structure

402 cutting line

403 photolithographic alignment patterns

405 dummy pattern structure

501 storage stack structure

502 cutting line

503 photoetching alignment pattern

505 dummy pattern structure

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 1 to 11. It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.