阅读说明：本技术 一种半导体结构及其制作方法和三维存储器件 (Semiconductor structure, manufacturing method thereof and three-dimensional memory device ) 是由 王清清 徐伟 周文斌 于 2020-03-23 设计创作，主要内容包括：本发明提供一种半导体结构及其制作方法和三维存储器件,该半导体结构包括衬底；栅极堆叠结构,位于所述衬底上,所述栅极堆叠结构包括沿第一方向依次设置的核心区域和连接区域,其中,所述核心区域包括主核心区和应力跳变区,所述主核心区通过所述应力跳变区与所述连接区域连接；栅线分隔槽,设置于所述栅极堆叠结构中,且沿所述第一方向延伸；若干排第一垂直沟道结构,沿第二方向间隔设置于所述核心区域中,其中,最靠近栅线分隔槽的至少一排第一垂直沟道结构的位于应力跳变区的部分被移除。利用本发明,可以避免由于3D NAND中核心区域/连接区域过渡区处局部应力梯度而导致栅线分隔槽发生倾斜时字线-字线/字线-共源极阵列的暴露,提高产品良率。(The invention provides a semiconductor structure, a manufacturing method thereof and a three-dimensional memory device, wherein the semiconductor structure comprises a substrate; the grid stacking structure is positioned on the substrate and comprises a core region and a connecting region which are sequentially arranged along a first direction, wherein the core region comprises a main core region and a stress jump region, and the main core region is connected with the connecting region through the stress jump region; a gate line separation groove disposed in the gate stack structure and extending along the first direction; and the plurality of rows of first vertical channel structures are arranged in the core region at intervals along the second direction, wherein the part, located in the stress jump region, of at least one row of first vertical channel structures closest to the grid line separation groove is removed. By using the method and the device, the word line-word line/word line-common source array can be prevented from being exposed when the grid line separating groove is inclined due to local stress gradient at the transition region of the core region/the connecting region in the 3D NAND, and the product yield is improved.)

1. A semiconductor structure, comprising:

a substrate;

the grid stacking structure is positioned on the substrate and comprises a core region and a connecting region which are sequentially arranged along a first direction, wherein the core region comprises a main core region and a stress jump region, and the main core region is connected with the connecting region through the stress jump region;

a gate line separation groove disposed in the gate stack structure and extending along the first direction;

and the plurality of rows of first vertical channel structures are arranged in the core region at intervals along the second direction, wherein the part, located in the stress jump region, of at least one row of first vertical channel structures closest to the grid line separation groove is removed.

2. The semiconductor structure of claim 1, wherein portions of at least two rows of the first vertical channel structure closest to the gate line separation trench that are located in the stress jump region are removed.

3. The semiconductor structure of claim 1, further comprising:

and a plurality of rows of second vertical channel structures which are arranged in the connecting region at intervals along the second direction, wherein the number of rows of the second vertical channel structures is less than that of the first vertical channel structures.

4. The semiconductor structure of claim 3, wherein each row of the second vertical channel structures comprises a plurality of second vertical channel structure monomers spaced along the first direction.

5. The semiconductor structure of claim 1, wherein the gate line separation trench vertically penetrates the gate stack structure.

6. The semiconductor structure of claim 1, wherein the minimum distance from the gate line separation trench to the vertical channel structure comprises a first distance and a second distance, wherein the first distance is the minimum distance from the gate line separation trench to the vertical channel structure in the primary core region, wherein the second distance is the minimum distance from the gate line separation trench to the vertical channel structure in the stress jump region, and wherein the first distance is less than the second distance.

7. The semiconductor structure of claim 1, wherein each row of the first vertical channel structures comprises a plurality of first vertical channel structure monomers spaced along the first direction.

8. The semiconductor structure of claim 7, wherein each of the first vertical channel structures in two adjacent rows of the first vertical channel structures are staggered.

9. The semiconductor structure of claim 1, wherein the connection region comprises a stepped structure.

10. The semiconductor structure of any of claims 1-9, wherein the first direction is perpendicular to the second direction.

11. A method for fabricating a semiconductor structure, comprising:

providing a substrate;

forming a gate stack structure on the substrate, wherein the gate stack structure comprises a core region and a connection region which are sequentially arranged along a first direction, the core region comprises a main core region and a stress jump region, and the main core region is connected with the connection region through the stress jump region;

forming a plurality of rows of first vertical channel structures at intervals in the core region along a second direction;

forming a gate line separation groove in the gate stack structure, the gate line separation groove extending along the first direction;

wherein a portion of at least one row of the first vertical channel structures closest to the gate line separation trench, which is located in the stress jump region, is removed.

12. The method of claim 11, wherein in the step of forming the plurality of rows of the first vertical channel structures at intervals along the second direction in the core region, portions of at least two rows of the first vertical channel structures closest to the gate line separation trench in the stress jump region are removed.

13. The method of fabricating a semiconductor structure according to claim 11, further comprising the steps of:

and forming a plurality of rows of second vertical channel structures at intervals in the connecting region along the second direction, wherein the number of rows of the second vertical channel structures is smaller than that of the first vertical channel structures.

14. The method for manufacturing a semiconductor structure according to claim 13, wherein in the step of forming a plurality of rows of second vertical channel structures at intervals along the second direction in the connection region, each row of the second vertical channel structures comprises a plurality of second vertical channel structure monomers at intervals along the first direction.

15. The method as claimed in claim 11, wherein in the step of forming the gate line separating trench in the gate stack structure, the gate line separating trench vertically penetrates through the gate stack structure.

16. The method of claim 11, wherein a minimum distance from the gate line separation trench to the vertical channel structure comprises a first distance and a second distance, wherein the first distance is a minimum distance from the gate line separation trench to the vertical channel structure in the primary core region, the second distance is a minimum distance from the gate line separation trench to the vertical channel structure in the stress jump region, and the first distance is less than the second distance.

17. The method of claim 11, wherein in the step of forming a plurality of rows of first vertical channel structures at intervals along the second direction in the core region, each row of the first vertical channel structures comprises a plurality of first vertical channel structure units at intervals along the first direction.

18. The method of claim 17, wherein in the step of forming a plurality of rows of first vertical channel structures at intervals along the second direction in the core region, each of the first vertical channel structures in two adjacent rows of the first vertical channel structures is staggered.

19. The method of claim 11, wherein the connection region comprises a step structure.

20. The method of fabricating a semiconductor structure according to any one of claims 11 to 19, wherein the first direction is perpendicular to the second direction.

21. A three-dimensional memory device comprising the semiconductor structure of any one of claims 1-20.

Technical Field

The invention belongs to the technical field of semiconductor integrated circuits, and relates to a semiconductor structure, a manufacturing method thereof and a three-dimensional memory device.

Background

NAND flash memories of planar structure have approached their practical expansion limits, posing serious challenges to the semiconductor memory industry. The new 3D NAND technology vertically stacks multiple layers of data storage units, can support accommodating higher storage capacity in a smaller space, further brings great cost saving, energy consumption reduction, and great performance improvement to comprehensively meet the requirements of numerous consumer mobile devices and enterprise deployment with the most severe requirements.

Three-dimensional memory devices typically include one or more chip (plane) memory regions (also referred to as core regions) on both sides of which symmetrical connection regions for Gate extraction are typically disposed, the connection regions typically have a staircase-Step (SS) shape, the chip and connection regions are typically divided into blocks (blocks) to form a plurality of Block memory regions, the conventional 3D NAND technology is to divide the blocks by Gate line partitions (Gate L Split, G L S), for example, a 128-layer 3D NAND, where the channel structure design of the core/connection region transition region transitions from 9 rows to 3 rows, where a large stress gradient exists, which may cause severe tilt of the etched Gate line partitions at the core/connection region transition region, which may cause Word line (Word L, W L) -ACS-Common Source Array (Array) to result in 70% yield loss.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a semiconductor structure, a method for fabricating the same, and a three-dimensional memory device, which are used to solve the problem of low yield of products caused by tilting (tilting) of a middle gate line separating trench at a transition region of a core region/a connection region in the three-dimensional memory device in the prior art.

To achieve the above and other related objects, the present invention provides a semiconductor structure, comprising:

a substrate;

the grid stacking structure is positioned on the substrate and comprises a core region and a connecting region which are sequentially arranged along a first direction, wherein the core region comprises a main core region and a stress jump region, and the main core region is connected with the connecting region through the stress jump region;

a gate line separation groove disposed in the gate stack structure and extending along the first direction;

and the plurality of rows of first vertical channel structures are arranged in the core region at intervals along the second direction, wherein the part, located in the stress jump region, of at least one row of first vertical channel structures closest to the grid line separation groove is removed.

In an alternative embodiment, the portions of the at least two rows of the first vertical channel structures closest to the gate line separating trench in the stress jump region are removed.

In an alternative embodiment, the semiconductor structure further comprises:

and a plurality of rows of second vertical channel structures which are arranged in the connecting region at intervals along the second direction, wherein the number of rows of the second vertical channel structures is less than that of the first vertical channel structures.

In an alternative embodiment, each row of the second vertical channel structures includes a plurality of second vertical channel structure monomers arranged at intervals along the first direction.

In an alternative embodiment, the gate line separation groove vertically penetrates through the gate stack structure.

In an optional embodiment, the minimum distance from the gate line separation trench to the vertical channel structure includes a first distance and a second distance, where the first distance is the minimum distance from the gate line separation trench to the vertical channel structure in the primary core region, the second distance is the minimum distance from the gate line separation trench to the vertical channel structure in the stress jump region, and the first distance is smaller than the second distance.

In an alternative embodiment, each row of the first vertical channel structures includes a plurality of first vertical channel structure monomers arranged at intervals along the first direction.

In an alternative embodiment, each of the first vertical channel structures in two adjacent rows of the first vertical channel structures is arranged in a staggered manner.

In an alternative embodiment, the connection region comprises a stepped structure.

In an alternative embodiment, the first direction is perpendicular to the second direction.

To achieve the above and other related objects, the present invention also provides a method for fabricating a semiconductor structure, comprising:

providing a substrate;

forming a gate stack structure on the substrate, wherein the gate stack structure comprises a core region and a connection region which are sequentially arranged along a first direction, the core region comprises a main core region and a stress jump region, and the main core region is connected with the connection region through the stress jump region;

forming a plurality of rows of first vertical channel structures at intervals in the core region along a second direction;

forming a gate line separation groove in the gate stack structure, the gate line separation groove extending along the first direction;

wherein a portion of at least one row of the first vertical channel structures closest to the gate line separation trench, which is located in the stress jump region, is removed.

In an optional embodiment, in the step of forming a plurality of rows of first vertical channel structures at intervals along the second direction in the core region, portions of at least two rows of the first vertical channel structures closest to the gate line separation groove in the stress jump region are removed.

In an optional embodiment, the semiconductor manufacturing method further comprises the steps of:

and forming a plurality of rows of second vertical channel structures at intervals in the connecting region along the second direction, wherein the number of rows of the second vertical channel structures is smaller than that of the first vertical channel structures.

In an alternative embodiment, in the step of forming a plurality of rows of second vertical channel structures at intervals along the second direction in the connection region, each row of the second vertical channel structures includes a plurality of second vertical channel structure monomers at intervals along the first direction.

In an optional embodiment, in the step of forming the gate line separation groove in the gate stack structure, the gate line separation groove vertically penetrates through the gate stack structure.

In an optional embodiment, the minimum distance from the gate line separation trench to the vertical channel structure includes a first distance and a second distance, where the first distance is the minimum distance from the gate line separation trench to the vertical channel structure in the primary core region, the second distance is the minimum distance from the gate line separation trench to the vertical channel structure in the stress jump region, and the first distance is smaller than the second distance.

In an optional embodiment, in the step of forming a plurality of rows of first vertical channel structures at intervals along the second direction in the core region, each row of the first vertical channel structures includes a plurality of first vertical channel structure monomers at intervals along the first direction.

In an optional embodiment, in the step of forming a plurality of rows of first vertical channel structures at intervals along the second direction in the core region, each of the first vertical channel structures in two adjacent rows of the first vertical channel structures is arranged in a staggered manner.

In an alternative embodiment, the connection region comprises a stepped structure.

In an alternative embodiment, the first direction is perpendicular to the second direction.

To achieve the above and other related objects, the present invention also provides a three-dimensional memory device including the semiconductor structure of any one of the above.

By using the invention, the number of the first vertical channel structures is reduced in the stress jump region of the core region of the three-dimensional memory (such as 3D NAND), namely the vertical channel monomer at the outermost row of the stress jump region is removed, so that the distance from the first vertical channel structure in the stress jump region to the grid line separation groove can be enlarged, thereby avoiding the exposure of the word line-word line/word line-common source array when the grid line separation groove is inclined due to the local stress gradient at the transition region of the core region/connecting region in the three-dimensional memory, avoiding the short connection of the grid line separation structure formed in the grid line separation groove 201 and the first vertical channel structure, and improving the product yield.

Drawings

FIG. 1 is a top view of a typical semiconductor structure.

Fig. 2 shows the semiconductor structure of fig. 1 and stress curves along the X-direction.

Fig. 3 is an SEM image of a product using the semiconductor structure shown in fig. 1.

Fig. 4 is a top view of a semiconductor structure according to the present invention.

Fig. 5 shows the semiconductor structure of fig. 4 and stress curves along the X-direction.

Fig. 6 is a top view of another semiconductor structure of the present invention.

FIG. 7 is a flow chart illustrating the fabrication of a semiconductor structure according to the present invention.

Description of the element reference numerals

101 grid line separating groove

102 first vertical channel structure monomer

103 second vertical channel structure monomer

201 grid line separating groove

202 first vertical channel structure monomer

203 second vertical channel structure monomer

Z1 Primary core region

Z2 stress jump zone

d1, d2 and d3 spacing

S10-S50

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.

Fig. 1 illustrates a top view of a semiconductor structure, which may be an intermediate product in the fabrication of a three-dimensional memory device (e.g., 3d nand), including a substrate (not shown), a gate stack (not shown), gate line separation trenches 101, rows of first vertical channel structures, and rows of second vertical channel structures. The gate stack structure is formed on the substrate, and comprises a core region and a connection region which are sequentially arranged along a first direction (X direction in fig. 1); the gate line separating groove 101 is disposed in the gate stack structure and extends along the first direction; a plurality of rows of first vertical channel structures are arranged in the core region at intervals along a second direction, namely along the Y direction in fig. 1; and a plurality of rows of second vertical channel structures are arranged in the connecting area at intervals along the second direction.

As shown in fig. 1, each row of the first vertical channel structure includes a plurality of first vertical channel structure single bodies 102 arranged at intervals along the X direction; each row of the second vertical channel structures comprises a plurality of second vertical channel structure single bodies 103 which are arranged at intervals along the X direction.

As can be seen from fig. 1, the number of rows of the second vertical channel structure is smaller than the number of rows of the first vertical channel structure, i.e. the number of rows of the channel structure in the transition region from the core region to the connection region is reduced, as an example, the number of rows of the channel structure in the transition region from the core region to the connection region is shifted from 9 rows to 3 rows, as shown in fig. 2, the stress simulation result shows that at the transition region from the core region to the connection region (where the second vertical dashed line from left to right in fig. 2 is located), there is a relatively large stress change, forming a local stress gradient, which causes severe tilting (tilting) of the gate line trench at the transition region from the core region to the connection region, the gate line trench 101 bends (the mouse bites), thereby causing exposure of the Word line (Word L in, W L) -Word line/Word line-Common Source Array (Common Source), which is shown in the SEM picture of the gate line at this location, and subsequently causes a reduction in the yield of the resulting first vertical channel structure.

Based on this, as shown in fig. 4, the present invention provides a semiconductor structure, which reduces the number of first vertical channel structures in a stress jump region (a region shown by Z2 in fig. 4), that is, removes the outermost row of holes of the stress jump region, so as to increase the distance from the first vertical channel structure in the stress jump region to a gate line separation groove, thereby preventing the gate line separation groove from being shorted together with the first vertical channel structure when the gate line separation groove is inclined, and improving the yield of products. The technical solution of the present invention will be described with reference to specific examples.