阅读说明：本技术 存储器总线占空比的测量、校准和调谐 (Measurement, calibration and tuning of memory bus duty cycle ) 是由 S·奈多夫 D·C·布里奇 Y·格罗斯曼 于 2019-12-05 设计创作，主要内容包括：本发明题为“存储器总线占空比的测量、校准和调谐”。本发明公开了一种用于动态监测、测量和调整操作存储设备的时钟占空比的方法和装置。一种存储设备包括测量电路,该测量电路包括耦接到第一输入线的多个触发器寄存器,其中每个触发器寄存器具有第一输入和第二输入。一个或多个延迟抽头耦接到每个触发器寄存器,并且设置在第二输入线上。当设备操作时,时钟信号经由第一输入线被直接输入到每个触发器寄存器的第一输入中。同时,时钟信号经由第二输入线通过一个或多个延迟抽头被输入到每个触发器寄存器的第二输入中。然后读取所述触发器寄存器以确定所述设备的所述时钟占空比,并且根据需要调整所述时钟频率。(The invention relates to measuring, calibrating and tuning the duty cycle of a memory bus. A method and apparatus for dynamically monitoring, measuring and adjusting the clock duty cycle of an operating memory device is disclosed. A memory device includes a measurement circuit including a plurality of flip-flop registers coupled to a first input line, where each flip-flop register has a first input and a second input. One or more delay taps are coupled to each flip-flop register and are disposed on the second input line. When the device is operating, a clock signal is directly input into the first input of each flip-flop register via the first input line. Simultaneously, a clock signal is input into the second input of each flip-flop register through one or more delay taps via a second input line. The flip-flop register is then read to determine the clock duty cycle of the device, and the clock frequency is adjusted as needed.)

1. A storage device, comprising:

one or more memory devices;

a controller coupled to the one or more memory devices; and

a measurement circuit coupled to the controller, the measurement circuit comprising:

a plurality of consecutive delay taps;

a plurality of flip-flop registers, wherein each flip-flop register of the plurality of flip-flop registers comprises a first input and a second input;

a first input line directly coupled to the first input of each of the plurality of flip-flop registers;

a second input line coupled to the second input of each of the plurality of flip-flop registers through successive ones of the plurality of successive delay taps, wherein each successive delay tap has a constant delay; and

a measurement signal configured to be able to measure a clock duty cycle of the measurement circuit.

2. The memory device of claim 1, wherein the measurement circuit is configured to measure a clock duty cycle of the memory device.

3. The memory device of claim 2, wherein the measurement circuit is configured to adjust a clock frequency of the memory device.

4. The memory device of claim 1, wherein the measurement circuit further comprises a variable delay circuit.

5. The memory device of claim 4, wherein the variable delay circuit is coupled to the second input line.

6. The memory device of claim 4, wherein the second input line is coupled to the continuous delay tap through the variable delay circuit.

7. The memory device of claim 4, wherein the variable delay circuit comprises a plurality of delay taps.

8. The memory device of claim 7, wherein the variable delay circuit is configured to increase a delay of a signal input into the second input line.

9. The memory device of claim 1, wherein the same clock signal is input into both the first input line and the second input line.

10. A method of operating a storage device, comprising:

inputting a first signal into a plurality of flip-flop registers of a measurement circuit, the first signal being directly input into a first input of each of the flip-flop registers of the plurality of flip-flop registers;

simultaneously inputting a second signal into a plurality of delay taps, wherein one or more delay taps are coupled to each of the flip-flop registers of the plurality of flip-flop registers, and wherein the second signal passes through each of the one or more delay taps to a second input of each flip-flop register of the plurality of flip-flop registers;

reading the plurality of flip-flop registers to measure a clock duty cycle; and

calibrating the clock duty cycle in response to the measurement while operating the storage device.

11. The method of claim 10, further comprising resetting the plurality of flip-flop registers prior to inputting the first signal.

12. The method of claim 10, further comprising inputting a variable delay to the second signal.

13. The method of claim 10, wherein the plurality of flip-flop registers are measured using a measurement signal.

14. The method of claim 10, wherein the first signal and the second signal are clock signals.

15. The method of claim 10, further comprising switching the storage device to an enabled state prior to inputting the first signal.

16. The method of claim 10, wherein calibrating the clock duty cycle comprises adjusting a clock frequency of the storage device.

17. A method of operating a storage device, comprising:

switching the storage device to an enabled state;

measuring a clock duty cycle of the memory device using a measurement circuit comprised of a plurality of flip-flop registers coupled to a chain of delay taps;

determining a value at which the clock duty cycle has changed;

determining a configuration value for calibrating the clock duty cycle;

calibrating the clock duty cycle; and

measuring the clock duty cycle using the measurement circuit.

18. The method of claim 17, wherein the measurement circuit further comprises:

a first clock signal directly coupled to a first input of each flip-flop register of the plurality of flip-flop registers;

a chain of delay taps comprising a plurality of delay taps, wherein one or more delay taps from the chain of delay taps are coupled to each flip-flop register of the plurality of flip-flop registers;

a second clock signal coupled to a second input of each of the plurality of flip-flop registers through the chain of delay taps, wherein the first clock signal and the second clock signal are the same clock signal;

measuring a signal; and

a variable delay circuit coupled to a beginning of the chain of delay taps.

19. The method of claim 17, further comprising continuously monitoring the clock duty cycle while the storage device is in the enabled state.

20. The method of claim 17, wherein calibrating the clock duty cycle comprises adjusting a clock frequency of the storage device.

Technical Field

Embodiments of the present disclosure generally relate to storage devices, such as Solid State Devices (SSDs).

Description of related ArtThe above-mentioned

During operation of a data storage device, such as an SSD, data may be transferred between a controller and a memory of the data storage device via a high speed parallel data bus coupling the controller and the memory. For example, one or more data values may be provided to or received from the data bus at a transfer rate based on the frequency of the clock signal. To illustrate, a first data value may be provided from a controller to a data bus in response to a rising edge or a falling edge of a clock signal.

As the demand for device performance increases, clock signal frequency requirements may increase and device environmental conditions (such as temperature and supply voltage) may change. Such changes may cause degradation in bus signal characteristics, such as setup and hold times. Degradation of bus signal characteristics limits the maximum clock signal frequency, which in turn limits system performance in some data use cases. Therefore, the clock duty cycle of the device may deviate from the margin, requiring calibration of the clock duty cycle for higher device performance.

However, calibrating the clock duty cycle of the device can be difficult. Measuring the clock duty cycle at the time of manufacture may allow tuning of the device configuration, but requires greater design margins, thereby increasing cost and reducing device performance. Measuring the clock duty cycle at manufacture also requires consideration of possible changes to environmental conditions before they occur, which may be less accurate and require additional margin. Other clock duty cycle calibrations require the memory device to stop operating to run various training sequences, which prohibits use of the memory device until reconfiguration is complete.

Accordingly, there is a need in the art for a clock duty cycle of a data storage device that can be dynamically calibrated.

Background

Disclosure of Invention

A method and apparatus for dynamically monitoring, measuring and adjusting the clock duty cycle of an operating memory device is disclosed. A memory device includes a measurement circuit including a plurality of flip-flop registers coupled to a first input line, where each flip-flop register has a first input and a second input. One or more delay taps are coupled to each flip-flop register and are disposed on the second input line. When the device is operating, a clock signal is directly input into the first input of each flip-flop register via the first input line. Simultaneously, a clock signal is input into the second input of each flip-flop register through one or more delay taps via a second input line. The flip-flop register is then read to determine the clock duty cycle of the device and the clock frequency is adjusted as needed.

In one embodiment, a memory device includes one or more memory devices, a controller coupled to the one or more memory devices, and a measurement circuit coupled to the controller. The measurement circuit includes a plurality of sequential delay taps and a plurality of flip-flop registers. Each flip-flop register of the plurality of flip-flop registers includes a first input and a second input. The measurement circuit also includes a first input line directly coupled to the first input of each of the plurality of flip-flop registers. The measurement circuit also includes a second input line coupled to the second input of each of the plurality of flip-flop registers through successive ones of a plurality of successive delay taps, each successive delay tap having a constant delay; and a measurement signal configured to be able to measure a clock duty cycle of the measurement circuit.

In another embodiment, a method of operating a storage device includes: a first signal is input into a plurality of flip-flop registers of the measurement circuit, the first signal being directly input into a first input of each of the flip-flop registers of the plurality of flip-flop registers. The method also includes simultaneously inputting a second signal to the plurality of delay taps. One or more delay taps are coupled to each of the flip-flop registers of the plurality of flip-flop registers. The second signal passes through each of the one or more delay taps to a second input of each of the plurality of flip-flop registers. The method also includes reading the plurality of flip-flop registers to measure a clock duty cycle, and calibrating the clock duty cycle in response to the measurement while operating the memory device.

In another embodiment, a method of operating a storage device includes: switching the storage device to an enabled state; measuring a clock duty cycle of the memory device using a measurement circuit comprised of a plurality of flip-flop registers coupled to a chain of delay taps; determining a value at which the clock duty cycle has changed; determining a configuration value for calibrating a clock duty cycle; calibrating a clock duty cycle; and measuring the clock duty cycle using a measurement circuit.

Drawings

So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments.

FIG. 1 illustrates an exemplary storage system according to one embodiment.

FIG. 2 shows an illustrative example of a data storage system according to another embodiment.

FIG. 3A illustrates a measurement circuit disposed in a memory device, according to one embodiment.

Fig. 3B shows a variable delay circuit disposed in a measurement circuit, according to one embodiment.

FIG. 4 illustrates a method for monitoring and measuring a clock duty cycle of a memory device using a measurement circuit, according to one embodiment.

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation.

Detailed Description

Hereinafter, reference is made to embodiments of the present disclosure. It should be understood, however, that the disclosure is not limited to the specifically described embodiments. Rather, any combination of the following features and elements, whether related to different embodiments or not, is contemplated to implement and practice the present disclosure. Moreover, although embodiments of the disclosure may achieve advantages over other possible solutions and/or over the prior art, whether or not a particular advantage is achieved by a given embodiment is not a limitation of the disclosure. Thus, the following aspects, features, embodiments and advantages are merely illustrative and are not considered elements or limitations of the appended claims except where explicitly recited in a claim(s). Likewise, reference to "the disclosure" should not be construed as a generalization of any inventive subject matter disclosed herein and should not be considered to be an element or limitation of the appended claims except where explicitly recited in a claim(s).

A method and apparatus for dynamically monitoring, measuring and adjusting the clock duty cycle of an operating memory device is disclosed. A memory device includes a measurement circuit including a plurality of flip-flop registers coupled to a first input line, where each flip-flop register has a first input and a second input. One or more delay taps are coupled to each flip-flop register and are disposed on the second input line. When the device is operating, a clock signal is directly input into the first input of each flip-flop register via the first input line. Simultaneously, a clock signal is input into the second input of each flip-flop register through one or more delay taps via a second input line. The flip-flop register is then read to determine the clock duty cycle of the device and the clock frequency is adjusted as needed.

FIG. 1 shows an illustrative storage system 100 according to one embodiment. The storage system 100 includes a host device 104 coupled to a storage device 102. Host device 104 can store data to and/or retrieve data from one or more storage devices, such as storage device 102. As shown in FIG. 1, the host device 104 may communicate with the storage device 102 via a host interface bus 108, such as a host interface bus. Host device 104 may comprise any of a variety of devices, including a computer server, a Network Attached Storage (NAS) unit, a desktop computer, a notebook (i.e., laptop) computer, a tablet computer, a set-top box, a telephone handset (such as a so-called "smart" phone), a so-called "smart" tablet, a television, a camera, a display device, a digital media player, a video game console, a video streaming device, and so forth.

The storage device 102 includes a controller 106 communicatively coupled to the host device 104 via a host interface bus 108. The controller 106 of the storage device 102 is also coupled to a non-volatile memory (NVM)110, such as a flash memory device or die, via an NVM interface bus 112. The NVM interface bus 112 (i.e., memory interface) includes a data bus. In one embodiment, NVM interface bus 112 includes a flash memory interface data bus. In some examples, storage device 102 may include additional components not shown in fig. 1 for clarity. For example, memory device 102 may include a Printed Board (PB) to which components of memory device 102 are mechanically attached and which includes conductive traces that electrically interconnect components of memory device 102, etc. In some examples, the physical dimensions and connector configuration of the storage device 102 may conform to one or more standard form factors. Some example standard form factors include, but are not limited to, 3.5 "data storage devices (e.g., HDD or SSD), 2.5" data storage devices, 1.8 "data storage devices, Peripheral Component Interconnect (PCI), PCI Express (PCI-X), PCI Express (PCIe) (e.g., PCIe X1, X4, X8, X16, PCIe Mini card, MiniPCI, etc.). In some examples, the storage device 102 may be directly coupled (e.g., soldered) to the motherboard of the host device 104.

The host interface bus 108 of the storage device 102 may include one or both of a data bus for exchanging data with the host device 104 and a control bus for exchanging commands with the host device 104. Host interface bus 108 may operate according to any suitable protocol. For example, the host interface bus 108 may operate according to one or more of the following protocols: advanced Technology Attachment (ATA) (e.g., serial ATA (sata) and parallel ATA (pata)), Fibre Channel Protocol (FCP), Small Computer System Interface (SCSI), serial attached SCSI (sas), PCI and PCIe, non-volatile memory express protocol (NVMe), and so forth. The electrical connection of the host interface bus 108 (e.g., a data bus, a control bus, or both) is electrically connected to the controller 106, thereby providing an electrical connection between the host device 104 and the controller 106, allowing data to be exchanged between the host device 104 and the controller 106. In some examples, the electrical connection of the host interface bus 108 may also allow the storage device 102 to receive power from the host device 104.

The memory device 102 includes an NVM110, which may include multiple memory devices. The NVM110 can be configured to store and/or retrieve data. For example, a memory device of the NVM110 can receive data and a message from the controller 106 instructing the memory device to store the data. Similarly, a memory device of the NVM110 can receive a message from the controller 106 instructing the memory device to retrieve data. In some examples, each of the memory devices may be referred to as a die. In some examples, a single physical chip may include multiple dies (i.e., multiple memory devices). In some examples, each memory device may be configured to store a relatively large amount of data (e.g., 128MB, 256MB, 412MB, 1GB, 2GB, 3GB, 8GB, 16GB, 32GB, 24GB, 128GB, 256GB, 412GB, 1TB, etc.).

In some examples, each memory device of the NVM110 can include any type of non-volatile memory device, such as a flash memory device, a Phase Change Memory (PCM) device, a resistive random access memory (ReRAM) device, a Magnetoresistive Random Access Memory (MRAM) device, a ferroelectric random access memory (F-RAM), a holographic memory device, and any other type of non-volatile memory device.

NVM110 may include one or more flash memory devices. Flash memory devices may include NAND and NOR based flash memory devices and may store data based on the charge contained in the floating gate of the transistor for each flash memory cell. In some flash memory devices, such as NAND memory devices, the flash memory devices may be divided into blocks, which may be divided into pages. Each block may include 128KB of data, 256KB of data, 2MB of data, 8MB of data, and so forth. In some cases, each page may include 1 Kilobyte (KB) of data, 3KB of data, 8KB of data, and so forth.

The controller 106 of the storage device 102 may manage one or more operations of the storage device 102. For example, the controller 106 may manage reading data from the NVM110 and/or writing data to the NVM110 via the NVM interface bus 112. In some embodiments, when the storage device 102 receives a write command from the host device 104, the controller 106 can initiate a data storage command to store data to the NVM110 and monitor the progress of the data storage command. The controller 106 can determine at least one operating characteristic of the storage system 100 and store the at least one operating characteristic to the NVM 110. The controller 106 also includes a measurement circuit 114. The measurement circuit 114 is configured to monitor, measure, and adjust the clock duty cycle of the memory device 102.

FIG. 2 shows an illustrative example of a data storage system 200 according to another embodiment. The data storage system 200 includes a data storage device 202 coupled to a host device 270. The data storage device 202 may be the storage device 102 of FIG. 1, and the host device 270 may be the host device 104 of FIG. 1.

The data storage device 202 may include a memory device, such as memory device 203. The memory device 203 may include one or more memory dies (e.g., one memory die, two memory dies, eight memory dies, or another number of memory dies). Memory device 203 includes memory 204, such as non-volatile memory of storage elements included in a memory die of memory device 203. The memory 204 may be the NVM110 of fig. 1. For example, as illustrative examples, memory 204 may include a flash memory, such as a NAND flash memory, or a resistive memory, such as a resistive random access memory (ReRAM). The memory 204 may have a three-dimensional (3D) memory configuration. Alternatively, memory 204 may have another configuration, such as a two-dimensional (2D) memory configuration or a non-monolithic 3D memory configuration (e.g., a stacked-die 3D memory configuration).

Memory 204 may include one or more regions of storage elements (also referred to herein as memory cells), such as a memory region 208 for storing data 206. One example of a memory area is a block, such as a NAND flash memory erase memory element group. Another example of a memory region 208 is a word line of memory elements. Each memory element of memory 204 may be programmed to indicate a state of one or more bit values (e.g., a threshold voltage in a flash configuration or a resistance state in a resistive memory configuration).

The memory device 203 also includes read/write circuits 210. Read/write circuits 210 are configured to program values to storage elements of memory 204 and to sense values from the storage elements of memory 204. The memory device 203 may also include circuitry 216 (e.g., one or more data latches, one or more control latches, or a combination thereof).

The data storage device 202 may also include a controller 230. The controller 230 may include a first interface 238 (e.g., a host interface), an Error Correction Code (ECC) engine 234, a timing device 236, a second interface 232 (e.g., a memory interface), and one or more voltage regulators 242. To further illustrate, the first interface 238 may include one or more latches to receive data and commands from the host device 270, and the second interface 232 may include one or more bus drivers to send data and commands to the circuitry 216 of the memory device 203. The controller 230 may store (or access) a file table 240, such as a File Allocation Table (FAT). The controller 230 also includes a measurement circuit 214. The measurement circuit 214 may be the measurement circuit 114 of fig. 1. The measurement circuit 214 is configured to monitor and measure the clock duty cycle of the data storage device 202.

The host device 270 may include circuitry 272. For example, the circuit 272 may include one or more bus drivers. The circuitry 272 may be integrated within or coupled to a processor or controller of the host device 270, such as within a host processing device 274 (e.g., an application processor).

Data storage device 202 and host processing device 274 are coupled via connection 250 (e.g., a bus). Connection 250 may be host interface bus 108 of fig. 1. For example, fig. 2 shows that the connections 250 may include one or more data lines 251, one or more control lines 252, and one or more timing signal lines 253. The connection 250 is coupled to the first interface 238 and the circuit 272.

The memory device 203 and the controller 230 are coupled via a connection 220 (e.g., a bus). The connection 220 may be the NVM interface bus 112 of fig. 1. For example, fig. 2 shows that connection 220 may include one or more data lines 221, one or more control lines 222, and one or more timing signal lines 223. Connection 220 is coupled to circuitry 216 and second interface 232.

In the illustrative implementation, the data storage system 200 also includes a power supply connection 273 (e.g., a "rail" for providing a power supply voltage, such as VDD, VCC, or both). The power connection 273 may be coupled to the memory device 203, the controller 230, and the host processing device 274. Depending on the implementation, the power connection 273 may be provided by a battery (e.g., a mobile device battery) or a power device (e.g., a transformer) coupled to a main power source. In other implementations, the memory device 203, the controller 230, and/or the host processing device 274 are connected to separate power connections.

During operation, the controller 230 is configured to receive data and instructions from the host device 270 using the first interface 238. For example, the controller 230 may receive the data 260 from the host device 270 via the first interface 238. To further illustrate, data 260 may be received via one or more data lines 251 in conjunction with a write access request 262 sent via one or more control lines 252. The data 260 and the request 262 may be received by the controller 230 based on timing signals 264 (e.g., one or more clock signals, one or more trip signals, or one or more read enable signals) received via one or more timing signal lines 253. For example, the first interface 238 may include one or more latches to receive the data 260 based on the timing signal 264. Although fig. 2 shows a single timing signal 264, it should be understood that more than one timing signal 264 (e.g., differential timing signal pair) may be used.

The ECC engine 234 may include a Hamming encoder, a Reed-Solomon (RS) encoder, a Bose-Chaudhuri-Hocquenghem (BCH) encoder, a Low Density parity check (L DPC) encoder, a turbo encoder, an encoder configured to encode data according to one or more other ECC schemes, or a combination thereof.

The controller 230 is configured to send data and commands to the memory device 203 using the second interface 232 and to receive data from the memory device 203 using the second interface 232. For example, the controller 230 is configured to send data (e.g., one or more ECC codewords generated by the ECC engine 234) and a write command (e.g., command 224) to cause the memory device 203 to store the data to a specified address of the memory 204. The write command may specify a physical address of a portion of memory 204 for storing data.

To further illustrate, the controller 230 may send data 228 to the memory device 203 via one or more data lines 221 in conjunction with write commands sent via one or more control lines 222. Memory device 203 may receive data 228 and write commands 224 based on timing signals 226() e.g., one or more clock signals) provided by controller 230 via one or more timing signal lines 223. For example, circuit 216 may include one or more latches configured to receive data 228 based on timing signal 264. Memory device 203 may cause read/write circuitry 210 to write data 206 to memory 204 based on timing signal 226. Data 260, data 228, and data 206 may all be the same data at different locations within system 200. While fig. 2 shows a single timing signal 226, it is to be understood that more than one timing signal 226() may be used, e.g., a differential timing signal pair). Additionally, in some cases, timing signal 226 may include a signal generated by memory device 203, such as a read enable signal.

The controller 230 is configured to send a read command (e.g., command 224) to the memory device 203 to access data from a specified address of the memory 204. For example, the controller 230 may send a read command to the memory device 203 in response to receiving a read access request from the host device 270. The read command may specify a physical address of a portion of the memory 204. For example, a read command may specify a physical address of a portion of memory 204 that stores data 206. In response to a read command, memory device 203 can cause read/write circuitry 210 to sense a portion of memory 204 that stores data 206 to generate sensed data (e.g., a representation of data that may differ with respect to the data due to one or more bit errors).

The controller 230 is configured to receive the sensed data from the memory device 203 via the second interface 232. The controller 230 may input the sensed data to the ECC engine 234 to initiate a decoding process to correct one or more bit errors (if any) in the sensed data to a particular error correction capability of a particular ECC technique. In response to decoding the sensed data, the ECC engine 234 may output data 260. The controller 230 may provide the data 260 to the host device 270 using the first interface 238.

Fig. 3A illustrates a measurement circuit 300 disposed in a memory device (such as memory device 102 of fig. 1 or memory device 202 of fig. 2) according to one embodiment. The measurement circuit 300 is firmware controlled and is configured to dynamically monitor and measure the clock duty cycle of the memory device during operation. The measurement circuit 300 may be the measurement circuit 114 disposed in the controller 106 of fig. 1 or the measurement circuit 214 disposed in the controller 230 of fig. 2.

The measurement circuit 300 includes a plurality of flip-flop registers 302a-302n coupled to a chain 304 of delay taps. In one embodiment, 128 flip-flop registers 302a-302n are included in measurement circuit 300. The chain of delay taps 304 includes a plurality of consecutive delay taps 306a-306 n. Each delay tap 306a-306n of the chain of delay taps 304 has the same or constant delay. One or more delay taps 306a-306n are coupled between each flip-flop register 302a-302 n. In one embodiment, one delay tap 306a-306n is coupled between each flip-flop register 302a-302 n.

Each flip-flop register 302a-302n has a first input 308 and a second input 310. The first input 308 may be a data input and the second input 310 may be a clock input. The clock signal 312 (labeled Clk) is split into a first input line 314 and a second input line 316. Thus, the first input line 314 and the second input line 316 are the same clock signal 312. The first input line 314 is directly coupled to the first input 308 of each flip-flop register 302a-302 n. The second input line 316 is coupled to the second input 310 of each flip-flop register 302a-302n through the chain of delay taps 304. Thus, the second input line 316 is directly coupled to the chain of delay taps 304. The chain of delay taps 304 is then coupled to the second input 310 of each flip-flop register 302a-302n via a second input line 316. The second input line 316 is coupled to a chain of delay taps 304 including a plurality of successive delay taps 306a-306n, each having a constant delay, resulting in the clock signal 312 being delayed by a predetermined, known amount of time. Thus, after the first input line 314 has been input to the first input of each flip-flop register 302a-302n, the delayed clock signal of the second input line 316 is input into the second input 310 of each flip-flop register 302a-302 n.

Measurement circuit 300 also includes a measurement signal 318 (labeled En) and a clear signal 320 (labeled Clr). The clear signal 320 is configured to reset or clear each of the flip-flop registers 302a-302n prior to inputting the clock signal 312. Once the flip-flop registers 302a-302n have been reset, the measurement signal 318 is enabled and the clock signal 312 propagates through the circuit 300. Once the clock signal 312 has propagated through the plurality of flip-flop registers 302a-302n, the measurement signal 318 is configured to allow the flip-flop registers 302a-302n to measure one cycle of the clock. The device firmware is then configured to read the flip-flop registers 302a-302n to determine the clock duty cycle of the memory device.

Based on the reading of each flip-flop register 302a-302n, a value at which the clock duty cycle is off, or a value at which the clock frequency should be adjusted, may be determined on the fly. For example, based on the measurement signal 318, the controller of the memory device is configured to dynamically determine whether and by how much the clock frequency (i.e., the high and/or low times of the clock duty cycle) needs to be adjusted. The clock frequency may be adjusted to achieve an optimal 50% clock duty cycle (i.e., 50/50 balance between high and low times), as shown by the clock duty cycle shown by the optimal register content readout 324.

In one embodiment, measurement circuit 300 also includes a variable delay circuit 322 coupled to second input line 316. In such embodiments, the variable delay circuit 322 is disposed before the first delay tap 306a in the chain of delay taps 304. Variable delay circuit 322 may be used to delay the start of a sampling window of the clock duty cycle in order to measure the slower clock.

Fig. 3B shows a variable delay circuit 322 disposed in the measurement circuit, according to one embodiment. The variable delay circuit 322 includes a chain 354 of adjustable delay taps. The chain of adjustable delay taps 354 includes a plurality of delay taps 356a-356n configured to adjust the amount of delay. The plurality of adjustable delay taps 356a-356n of the variable delay circuit 322 may delay the clock signal 312 by a smaller value or a larger value than the chain 304 of delay taps of the measurement circuit 300. The delay value added by the chain of adjustable delay taps 354 varies according to the time of the clock cycle to be measured. The delay of each adjustable delay tap 356a-356n in the chain of adjustable delay taps 354 may be adjusted such that the delay is appropriate for the measured clock. Different delays may be required for each clock cycle, and adding different amounts of delay may allow different clock cycles to be selected. The chain of adjustable delay taps 354 is coupled to a multiplexer 360, which is then coupled to the chain of delay taps 304 in the measurement circuit 300. Variable delay circuit 322 adds an incremental delay to the measurement of the clock duty cycle, moving the sampling window of cycles to allow the entire clock duty cycle to be captured in a few sampling cycles. Thus, for slower clocks, the sampling points are delayed, which allows clock transitions to be captured without increasing the number of flip-flop registers 302a-302n used in the measurement circuit 300. Utilizing variable delay circuit 322 allows a larger sampling window to be measured with the same measurement circuit 300.

FIG. 4 illustrates a method 400 for monitoring, measuring, and calibrating a clock duty cycle of a memory device using a measurement circuit, according to one embodiment. The method 400 may be used with the measurement circuit 300 of FIG. 3A. For clarity, the method 400 of FIG. 4 will be described with reference to the measurement circuit 300 of FIG. 3A.

In operation 402, the storage device is switched to an enabled state. The enabled state is a state in which the storage device is running, such as reading from and writing to non-volatile memory. The measurement circuit 300 is used to monitor and measure the clock duty cycle when the memory device is in an enabled and operational state.

Once the memory device is in the enabled mode, the method 400 proceeds to operation 404, where the clock duty cycle is measured. Measuring the clock duty cycle first includes resetting the plurality of flip-flop registers 302a-302n using a clear signal 320. Resetting the plurality of flip-flop registers 302a-302n ensures that each flip-flop register 302a-302n is enabled in the same first state, such as all being set to 0. The measurement signal 318 is then enabled for a single clock cycle. A clock signal 312 is then input, where the clock signal 312 travels directly to the first input 308 of each flip-flop register 302a-302n through a first input line 314 and to the second input 310 of each flip-flop register 302a-302n through one or more sequential delay taps 306a-306n through a second input line 316.

Since the second input line 316 propagates through one or more successive delay taps 306a-306n before being input to the second input 310 of each flip-flop register 302a-302n, the clock signal 312 of the second input line 316 is delayed to arrive at the plurality of flip-flop registers 302a-302n after the clock signal 312 of the first input line 314. Thus, when the clock signal 312 of the first input line 314 reaches each of the flip-flop registers 302a-302n, the flip-flop registers 302a-302n are switched to a second state, such as 1 (i.e., from 0 to 1). When the clock signal 312 of the second input line 316 reaches each flip-flop register 302a-302n after being input through the chain of delay taps 304, one or more of the flip-flop registers 302a-302n is switched back to the first state (i.e., from 1 to 0). The clock signal 312 propagates through the chain of delay taps 304, sequentially triggering the switching of the flip-flop registers 302a-302 n. At the end of the clock cycle, each flip-flop register 302a-302n holds the final state of the clock in the delay tap timing until reset.

In operation 406, each flip-flop register 302a-302n is read to determine whether the clock duty cycle meets the required margin. If the clock duty cycle meets the required margin, the method 400 returns to operation 404 and the measurement circuit 300 continues to monitor and measure the clock duty cycle. If a clock duty cycle deviation margin is determined, the method 400 proceeds to operation 408.

In operation 408, the configuration of the storage device is improved and/or calibrated. The transitions where the clock duty cycle deviates from the margin may be determined based on the reading of the flip-flop registers 302a-302 n. A first flip-flop register of the plurality of flip-flop registers 302a-302n that fails to toggle back to the first state after receiving the clock signal 312 from the second input line 316 may show where the transition occurred. Thus, improving the configuration may include determining the amount of clock duty cycle deviation based on the transitions and the calibration values needed to adjust the clock duty cycle and increase signal integrity. The calibration value may be that the frequency of the clock signal should be adjusted to achieve the optimal 50% clock duty cycle. In addition, the setup and hold times may also be continuously monitored based on the transition locations and the reading of the plurality of flip-flop registers 302a-302 n.

Then, based on the calibration value, the clock duty cycle is dynamically calibrated on the fly while the storage device is still in the enabled state. Calibrating the memory device may include adjusting a clock frequency. There is no need to stop the memory device operation in order to calibrate the clock duty cycle. Once the clock duty cycle is calibrated, the method 400 returns to operation 404 and the measurement circuit 300 continues to monitor and measure the clock duty cycle. Since memory devices are susceptible to environmental changes, such as temperature and supply voltage, it may be desirable to continuously monitor these devices. Thus, the method 400 may be repeated one or more times to continuously monitor the clock duty cycle without interrupting the operation of the memory device.

The use of a measurement circuit consisting of a plurality of flip-flop registers and delay taps allows the clock duty cycle of the memory device to be continuously monitored and measured while the memory device is running without causing performance degradation. If the clock duty cycle deviation margin is determined, the transition location may be determined so that the timing of the error may be subsequently determined relatively accurately, and the memory device may be dynamically and accurately configured with calibration values based on the transition. In addition, utilizing a measurement circuit consisting of multiple flip-flop registers and delay taps allows the setup and hold times of each signal to be measured continuously while the memory device is operating under normal conditions.

Furthermore, because the clock duty cycle is being monitored, there is no need to separately monitor any environmental changes that may affect the clock duty cycle or the root cause of the clock duty cycle change, allowing for multiple root causes to be supported without increasing error margins or costs. Thus, the measurement circuit enables the memory device to dynamically monitor, measure, and adjust the clock duty cycle as needed without interrupting memory device operation.

In one embodiment, a memory device includes one or more memory devices, a controller coupled to the one or more memory devices, and a measurement circuit coupled to the controller. The measurement circuit includes a plurality of sequential delay taps and a plurality of flip-flop registers. Each flip-flop register of the plurality of flip-flop registers includes a first input and a second input. The measurement circuit also includes a first input line directly coupled to the first input of each of the plurality of flip-flop registers. The measurement circuit also includes a second input line coupled to the second input of each of the plurality of flip-flop registers through successive ones of a plurality of successive delay taps, each successive delay tap having a constant delay; and a measurement signal configured to be able to measure a clock duty cycle of the measurement circuit.

The measurement circuit may be configured to measure a clock duty cycle of the memory device. The measurement circuit may be configured to adjust a clock frequency of the memory device. The measurement circuit may also include a variable delay circuit. The variable delay circuit may be coupled to the second input line. The second input line may be coupled to the continuous delay tap through a variable delay circuit. The variable delay circuit may include a plurality of delay taps. The variable delay circuit may be configured to increase a delay of a signal input into the second input line. The same clock signal may be input into both the first input line and the second input line.

In another embodiment, a method of operating a storage device includes: a first signal is input into a plurality of flip-flop registers of the measurement circuit, the first signal being directly input into a first input of each of the flip-flop registers of the plurality of flip-flop registers. The method also includes simultaneously inputting a second signal to the plurality of delay taps. One or more delay taps are coupled to each of the flip-flop registers of the plurality of flip-flop registers. The second signal passes through each of the one or more delay taps to a second input of each of the plurality of flip-flop registers. The method also includes reading the plurality of flip-flop registers to measure a clock duty cycle, and calibrating the clock duty cycle in response to the measurement while operating the memory device.

The method may further include resetting the plurality of flip-flop registers before the first signal is input. The measurement circuit may also include a variable delay circuit coupled to the plurality of delay taps. The plurality of flip-flop registers may be measured using a measurement signal of the measurement circuit. The first signal and the second signal may be clock signals. The method may further include switching the memory device to an enable state before the first signal is input. Calibrating the clock duty cycle may include adjusting a clock frequency of the memory device.

In another embodiment, a method of operating a storage device includes: switching the storage device to an enabled state; measuring a clock duty cycle of the memory device using a measurement circuit comprised of a plurality of flip-flop registers coupled to a chain of delay taps; determining a value at which the clock duty cycle has changed; determining a configuration value for calibrating a clock duty cycle; calibrating a clock duty cycle; and measuring the clock duty cycle using a measurement circuit.

The measurement circuit may further include: a first clock signal directly coupled to a first input of each of a plurality of flip-flop registers; and a chain of delay taps, the chain of delay taps comprising a plurality of delay taps. One or more delay taps from the chain of delay taps may be coupled to each flip-flop register of the plurality of flip-flop registers. The measurement circuit may also include a second clock signal coupled to a second input of each of the plurality of flip-flop registers through a chain of delay taps. The first clock signal and the second clock signal may be the same clock signal. The measurement circuit may further include a variable delay circuit coupled to the start of the chain of delay taps and the measurement signal. The method may also include continuously monitoring the clock duty cycle while the memory device is in the enabled state. Calibrating the clock duty cycle may include adjusting a clock frequency of the memory device.

While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.