阅读说明：本技术 主机自适应存储器装置优化 (Host adaptive memory device optimization ) 是由 N·格勒斯 D·A·帕尔默 于 2019-12-27 设计创作，主要内容包括：提供了用于主机自适应存储器装置优化的装置和技术。存储器装置可以维护与主机的交互的主机模型。可以评估来自所述主机的一组命令以创建所述一组命令的配置文件。可以将所述配置文件与所述主机模型进行比较以确定所述配置文件和所述主机模型之间的不一致性。然后可以基于所述不一致性修改所述存储器装置的操作。(Devices and techniques for host adaptive memory device optimization are provided. The memory device may maintain a host model of interactions with the host. A set of commands from the host may be evaluated to create a profile of the set of commands. The configuration file may be compared to the host model to determine an inconsistency between the configuration file and the host model. The operation of the memory device may then be modified based on the inconsistency.)

1. A memory device for host adaptive memory device optimization, the memory device comprising:

a storage to maintain a host model of interactions with a host; and

processing circuitry to:

evaluating a set of commands from the host to create a profile of the set of commands;

comparing the configuration file to the host model to determine an inconsistency between the configuration file and the host model; and

modifying operation of the memory device based on the inconsistency.

2. The memory device of claim 1, wherein to evaluate the set of commands, the processing circuitry is configured to measure a characteristic of a command of the set of commands.

3. The memory device of claim 2, wherein to compare the configuration file to the host model, the processing circuitry is configured to:

retrieving a representation of the characteristics of a single command from the host model;

comparing respective characteristics of a subset of commands from the set of commands to the representation of the characteristics; and

determining that the corresponding characteristic is greater than or less than the representation of the characteristic by a threshold to produce the inconsistency.

4. The memory device of claim 3, wherein the representation of the characteristic is an average.

5. The memory device of claim 2, wherein the subset of commands corresponds to a single type of command.

6. The memory device of claim 5, wherein the type of command is one of read, write, clear, erase, move, or garbage collection.

7. The memory device of claim 1, wherein the set of commands are commands in a command queue of the memory device, and wherein the inconsistency is a difference between a depth of the command queue and an average depth of the command queue stored in the host model.

8. The memory device of claim 1, wherein, to modify the operation of the memory device, the processing circuitry is configured to alter at least one of a host timeout interval, a watchdog timer, a write cache size, a flush frequency, a block alignment parameter, a garbage collection frequency, or a wear leveling parameter.

9. A method for host adaptive memory device optimization, the method comprising:

maintaining, by a memory device, a host model of interactions with a host;

evaluating a set of commands from the host to create a profile of the set of commands;

comparing the configuration file to the host model to determine an inconsistency between the configuration file and the host model; and

modifying operation of the memory device based on the inconsistency.

10. The method of claim 9, wherein evaluating the set of commands includes measuring a characteristic of a command in the set of commands.

11. The method of claim 10, wherein the characteristic is one of a data size, a pending interval, a command interval, a relationship to other types of memory device operations, an arrival rate, a depth of a command queue.

12. The method of claim 10, wherein comparing the configuration file to the host model includes:

retrieving a representation of the characteristics of a single command from the host model;

comparing respective characteristics of a subset of commands from the set of commands to the representation of the characteristics; and

determining that the corresponding characteristic is greater than or less than the representation of the characteristic by a threshold to produce the inconsistency.

13. The method of claim 12, wherein the representation of the characteristic is an average.

14. The method of claim 12, wherein a number of the subset of commands exceeds a second threshold to produce the inconsistency.

15. The method of claim 10, wherein the subset of commands corresponds to a single type of command.

16. The method of claim 15, wherein the type of command is one of read, write, clear, erase, move, or garbage collection.

17. The method of claim 9, wherein the set of commands are commands in a command queue of the memory device, and wherein the inconsistency is a difference between a depth of the command queue and an average depth of the command queue stored in the host model.

18. The method of claim 9, wherein modifying the operation of the memory device includes altering at least one of a host timeout interval, a watchdog timer, a write cache size, a flush frequency, a block alignment parameter, a garbage collection frequency, or a wear leveling parameter.

19. The method of claim 18, wherein at least one of the host timeout interval or the watchdog timer is altered based on a measure of time relative to receipt of a given command and receipt of a subsequent reset signal from the host for the given command.

20. The method of claim 9, comprising updating the host model to account for the inconsistency.

21. The method of claim 20, wherein updating the host model includes modifying an entry of a mean characteristic of the set of commands to include the inconsistency in the mean characteristic.

22. The method of claim 20, wherein the average characteristic is one of a data size, a pending interval, a relationship to other types of memory device operations, or an arrival rate.

23. A machine-readable medium comprising instructions that when executed by processing circuitry cause the processing circuitry to perform any of the methods of claims 9-22.

24. A system comprising means for performing any of the methods of claims 9-22.

Technical Field

The present application relates to memory devices, and in particular, to host adaptive memory device optimization.

Background

Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory.

Volatile memory requires power to maintain its data and includes Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), or the like.

Non-volatile memory can retain stored data when not powered and includes flash memory, Read Only Memory (ROM), electrically erasable programmable ROM (eeprom), static ram (sram), erasable programmable ROM (eprom), resistance variable memory such as Phase Change Random Access Memory (PCRAM), Resistive Random Access Memory (RRAM), or Magnetoresistive Random Access Memory (MRAM), among others.

Flash memory is used as non-volatile memory for a wide range of electronic applications. Flash memory devices typically include one or more sets of single transistor, floating gate, or charge trap memory cells to achieve high memory density, high reliability, and low power consumption.

Two common types of flash memory array architectures include NAND and NOR architectures, which are named in logical form in which the basic memory cell configuration of each architecture is arranged. The memory cells of a memory array are typically arranged in a matrix. In an example, the gate of each floating gate memory cell in a row of the array is coupled to an access line (e.g., a word line). In the NOR architecture, the drain of each memory cell in a column of the array is coupled to a data line (e.g., a bit line). In a NAND architecture, the drains of each memory cell in a string of the array are coupled together in series, source to drain, between a source line and a bit line.

Both NOR and NAND architecture semiconductor memory arrays are accessed through a decoder that activates a particular memory cell by selecting the word line coupled to its gate. In a NOR architecture semiconductor memory array, once activated, a selected memory cell places its data value on a bit line, causing different currents to flow depending on the state in which the particular cell is programmed. In a NAND architecture semiconductor memory array, a high bias voltage is applied to a drain side Select Gate (SGD) line. The word lines coupled to the gates of the unselected memory cells of each group are driven at a specified pass voltage (e.g., Vpass) to cause the unselected memory cells of each group to operate as pass transistors (e.g., pass current in a manner that is unrestricted by their stored data values). Current then flows from the source line to the bit lines through each series-coupled group, limited only by the selected memory cells of each group, placing the current encoded data values of the selected memory cells on the bit lines.

Each flash memory cell in a NOR or NAND architecture semiconductor memory array can be programmed individually or collectively to one or more program states. For example, a Single Level Cell (SLC) may represent one of two program states (e.g., 1 or 0), representing one bit of data.

However, flash memory cells can also represent one of more than two program states, allowing higher density memories to be fabricated without increasing the number of memory cells, since each cell can represent more than one binary digit (e.g., more than one bit). Such cells may be referred to as multi-state memory cells, multi-digit cells, or multi-level cells (MLCs). In some examples, MLC may refer to a memory cell that may store two bits of data per cell (e.g., one of four programmed states), a tertiary cell (TLC) may refer to a memory cell that may store three bits of data per cell (e.g., one of eight programmed states), and a quaternary cell (QLC) may store four bits of data per cell. MLC is used herein in its broader context to refer to any memory cell that can store more than one bit of data per cell (i.e., can represent more than two programmed states).

A conventional memory array is a two-dimensional (2D) structure disposed on a surface of a semiconductor substrate. To increase the memory capacity of a given area and reduce cost, the size of individual memory cells has been reduced. However, there are technical limitations to reducing the size of individual memory cells, and thus, there are technical limitations to the memory density of 2D memory arrays. In response, 3D memory structures, such as three-dimensional (3D) NAND architecture semiconductor memory devices, are being developed to further increase memory density and reduce memory cost.

Such 3D NAND devices often include strings of memory cells coupled in series, e.g., drain to source, between one or more source-side Select Gates (SGS) near the source and one or more drain-side Select Gates (SGD) near the bit line. In an example, the SGS or SGD may include one or more Field Effect Transistors (FETs) or Metal Oxide Semiconductor (MOS) structure devices, or the like. In some examples, the strings will extend vertically through a plurality of vertically spaced layers containing respective word lines. A semiconductor structure, such as a polysilicon structure, may extend adjacent to a string of memory cells to form a channel for the memory cells of the string. In the example of a vertical string, the polysilicon structures may be in the form of vertically extending pillars. In some examples, the string may be "folded" and thus arranged relative to the U-shaped post. In other examples, multiple vertical structures may be stacked on top of each other to form a stacked array of strings of storage cells.

The memory arrays or devices may be combined together to form a storage volume of a memory system, such as a Solid State Drive (SSD), Universal Flash Storage (UFS)^TM) Device, multi-media card (MMC) solid state memory device, embedded MMC device (eMMC)^TM) And so on. SSDs may be used, among other things, as the main storage device for computers, which may have advantages over traditional hard disk drives with moving parts, such as performance, size, weight, robustness, operating temperature range, and power consumption. For example, SSDs may reduce seek time, latency, or other delays associated with disk drives (e.g., electromechanical, etc.). SSDs use non-volatile memory cells, such as flash memory cells, to eliminate internal battery supply requirements, thus making the drive more versatile and compact.

An SSD may contain multiple memory devices, including multiple die or logic units (e.g., logic unit numbers or LUNs), and may contain one or more processors or other controllers that perform the logical functions needed to operate the memory devices or interface with external systems. Such SSDs may include one or more flash memory dies including a plurality of memory arrays and peripheral circuitry thereon. A flash memory array may contain a plurality of blocks of memory cells organized into a plurality of physical pages. In many examples, an SSD will also contain DRAM or SRAM (or other form of memory chip or other memory structure). The SSD may receive commands from the host associated with memory operations, such as read or write operations for transferring data (e.g., user data and associated integrity data, such as error data and address data, etc.) between the memory device and the host, or erase operations for erasing data from the memory device.

Disclosure of Invention

One aspect of the present invention provides a memory device for host adaptive memory device optimization, wherein the memory device comprises: a storage to maintain a host model of interactions with a host; and processing circuitry to: evaluating a set of commands from the host to create a profile of the set of commands; comparing the configuration file to the host model to determine an inconsistency between the configuration file and the host model; and modifying operation of the memory device based on the inconsistency.

Another aspect of the invention provides a method for host adaptive memory device optimization, wherein the method comprises: maintaining, by a memory device, a host model of interactions with a host; evaluating a set of commands from the host to create a profile of the set of commands; comparing the configuration file to the host model to determine an inconsistency between the configuration file and the host model; and modifying operation of the memory device based on the inconsistency.

Another aspect of the invention provides a machine-readable medium, wherein the machine-readable medium includes instructions that when executed by processing circuitry cause the processing circuitry to perform a method for host adaptive memory device optimization, wherein the method comprises: maintaining, by a memory device, a host model of interactions with a host; evaluating a set of commands from the host to create a profile of the set of commands; comparing the configuration file to the host model to determine an inconsistency between the configuration file and the host model; and modifying operation of the memory device based on the inconsistency.

Another aspect of the invention provides a system comprising means for performing a method for host adaptive memory device optimization, wherein the method comprises: maintaining, by a memory device, a host model of interactions with a host; evaluating a set of commands from the host to create a profile of the set of commands; comparing the configuration file to the host model to determine an inconsistency between the configuration file and the host model; and modifying operation of the memory device based on the inconsistency.

Drawings

In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals having different letter suffixes may represent different instances of similar components. The drawings generally depict various embodiments discussed in this document by way of example and not limitation.

FIG. 1 depicts an example of an environment containing a memory device in which one or more embodiments may be implemented.

Fig. 2 shows an example of a host model database.

FIG. 3 is a flow chart of an example of a method for host adaptive memory device optimization.

FIG. 4 is a block diagram depicting an example of a machine in which one or more embodiments may be implemented.

Detailed Description

Memory devices, such as NAND flash devices, may include various operating parameters that affect the performance of the memory device in various circumstances. The operating profile may be installed in the memory device based on expected operating conditions of the host. For example, an energy-constrained mobile phone may exhibit a short period of intense write and read activity, followed by a long period of inactivity. In such examples, a write cache may be added to enable faster writes, with periods of inactivity being used to copy the write cache to more compact storage (e.g., SLC cache to TLC storage). However, such configuration files may not be suitable for server applications that involve conventional high-volume writes or reads.

A problem that may arise when selecting and implementing a configuration file in a memory device to meet a particular operational scenario is alteration. Although the configuration file may be manually updated, performance degradation often becomes severe to prompt for such actions. Furthermore, merely switching between profiles may be futile if the change in behavior is temporary, or if the available profiles do not fully satisfy the operational behavior of the host.

To address these issues, host adaptive memory device optimization may be used. Here, a host model is used to quantify expected host behavior. Current host command activity is measured and compared to this host model to determine deviations from expected behavior. The memory device may then update the operating parameter based on this deviation. Such an arrangement enables highly customized and automated modification of memory devices to meet changing host behaviors. Further, over time, the host model may be updated to make memory device operation more consistent with host activity.

Dynamically adjusting control parameters of a memory device based on changes in host behavior improves memory device performance and enables the memory device to complete memory device commands faster and more efficiently. This reduces the latency experienced by different applications running on the host and provides a significant technical improvement over typical memory devices. Additional details and examples are provided below.

FIG. 1 depicts an example of an environment 100, the environment 100 including a host 105 and a memory device 110 configured to communicate via a communication interface 111. The host 105 and the memory device 110 may be included in various products 150, such as IoT devices (e.g., refrigerators or other appliances, sensors, motors or actuators, mobile communication devices, automobiles, mobile phones, drones, etc.) to support processing, communication, or control of a given one of the products 150.

One or more communication interfaces 111 may be used to transfer data between memory device 110 and host 105. The communication interface 111 may include a Serial Advanced Technology Attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, a Universal Serial Bus (USB) interface, a Universal Flash Storage (UFS) interface, an eMMC^TMAn interface, or one or more other connectors or interfaces. Host 105 may comprise a host system, an electronic device, a processor, a CPU, a memory card reader, or one or more other electronic devices. In some examples, the masterMachine 105 may be some portion having the components discussed with reference to machine 400 of fig. 4.

Memory device 110 includes a memory controller 115 and a memory array 120, memory array 120 including, for example, one or more individual memory dies, such as a stack of three-dimensional (3D) NAND dies. In 3D architecture semiconductor memory technology, vertical structures are stacked into multiple layers and coupled to form physical pages to increase the storage density of memory devices (e.g., memory devices) in a given footprint (i.e., form factor).

The memory controller 115 may receive instructions from the host 105 via the communication interface 111 and may communicate with the memory array 120, e.g., to transfer data to (e.g., write or erase) or from (e.g., read) one or more of the memory cells, planes, sub-blocks, or pages of the memory array 120. Memory controller 115 may include, among other things, circuitry or firmware including one or more components or integrated circuits. For example, memory controller 115 may include one or more memory control units, circuits, control circuitry, or components configured to control access across memory array 120 and provide a translation layer between host 105 and memory device 110. Memory controller 115 may contain one or more I/O circuits, lines, or interfaces for transferring data to or from memory array 120. Memory controller 115 may include a memory manager 125 and an array controller 135.

The memory controller 115 may also implement host adaptive optimization. To this end, memory controller 115 is configured to maintain a host model of host interactions with memory devices 110. Maintaining the host model may include storing the host model (e.g., in management table 130), and may also include modifying or updating the host model. An example host model is depicted in FIG. 2. In general, a host model is a set of metrics that describe the possible behavior of a host. This may be used to customize various memory device 110 operations to meet this behavior. For example, if the host has small coherent writes, the memory controller 115 may schedule maintenance operations, such as garbage collection, outside of these write periods.

While the host model enables a degree of customization, it does not address changes to the host 105 by itself. Such changes may include new workloads (e.g., applications, entities serviced by host 105, etc.), new operating software, new hardware, new firmware, etc. To accommodate these changes, the memory controller 115 is configured to analyze a set of memory device commands, such as those in the command queue of the memory controller 115, to determine whether those commands are consistent with the host model. If the set of commands is not consistent with the host model, memory controller 115 is configured to modify an operating parameter of memory device 110.

In an example, the memory controller 115 is configured to generate or update the host model by calculating an average or other statistical metric related to commands after a given time interval (e.g., every 30 seconds) or after a predetermined number of commands (e.g., every 1000 commands). Such updates enable the memory controller 115 to adapt its operating parameters to the behavior of the host, using host adaptation techniques during transitions or temporary deviations from the general host behavior loaded in the host model.

In an example, the calculated average or other statistical metric represents the average behavior of the command queue across all commands for a command type (e.g., single block write, single block read, multi-block write, or multi-block read). In an example, an average depth of the command queue, an average data size of the commands in the command queue, an average time between command receptions in the command queue, or an average command pending duration of the commands in the command queue may be calculated and stored as a corresponding entry in the host model.

In an example, to calculate the average depth of the command queue, the memory controller 115 is configured to count the number of commands pending in the command queue after each given time interval has elapsed. This number is then averaged together with the average previously stored in the corresponding host model entry. In an example, to calculate the average data size of the commands in the command queue, the memory controller 115 is configured to obtain command status information-e.g., command size (e.g., how many pages or blocks to write/read) -for each command pending in the command queue. In one example, command status information collection is limited to different time intervals. Memory controller 115 may then calculate an average of the obtained command sizes. At the end of a given time interval, the calculated average data size is stored in the host model.

In an example, an average time between command receptions in the command queue is calculated based on timestamps of the received commands-e.g., during each given time interval. Here, the memory controller 115 may calculate a difference between timestamps of pairs of sequentially received commands and an average value of the differences. At the end of a given time interval, the results are stored in the host model. In an example, the average command pending duration may be calculated as the difference between each timestamp and the current time and an average of the determined differences.

Memory controller 115 is configured to determine whether a received command, e.g., a command in a command queue, is consistent with the host model. In an example, the memory controller 115 is configured to obtain current command queue information (e.g., average depth of the command queue, average data size of commands in the command queue, average time between command receptions in the command queue, average command pending duration, status information for a particular type of command in the command queue, etc.) and compare it to any combination of one or more entries of the host model.

In an example, if the difference between the current depth of the command queue and the average depth of the command queue exceeds a threshold (e.g., the difference is greater than or less than the threshold by an absolute number or a given percentage amount), then a group of commands in the command queue is inconsistent with the host model. In an example, memory controller 115 is configured to limit analysis to a given set of commands from the command queue that correspond to a particular type of command.

When the observations about the current command received from the host 105 are not consistent with the host model, the memory controller 115 is configured to adjust the operating parameters of the memory device 110. For example, memory controller 115 may restore the adaptive timer to a default value or another predetermined value, increase or decrease write cache size, increase or decrease write cache flush frequency, align more or fewer blocks corresponding to commands in the command queue, increase or decrease garbage collection frequency, or change wear leveling from static to dynamic, or vice versa, to modify the operation of memory device 110.

The array controller 135 may include, among other things, circuitry or components configured to control memory operations associated with: writing data to one or more memory cells of memory device 110, reading data from one or more memory cells of memory device 110, or erasing one or more memory cells of memory device 110. The memory operation may be based on, for example, a host command received from the host 105 or generated internally by the memory manager 125 (e.g., associated with wear leveling, error detection or correction, etc.).

Each flash memory cell in a NOR or NAND architecture semiconductor memory array can be programmed individually or collectively to one or more program states. For example, a Single Level Cell (SLC) may represent one of two program states (e.g., 1 or 0), representing one bit of data. However, flash memory cells can also represent one of more than two program states, allowing higher density memories to be fabricated without increasing the number of memory cells, since each cell can represent more than one binary digit (e.g., more than one bit). Such cells may be referred to as multi-state memory cells, multi-digit cells, or multi-level cells (MLCs). In some examples, MLC may refer to a memory cell that may store two bits of data per cell (e.g., one of four programmed states), a tertiary cell (TLC) may refer to a memory cell that may store three bits of data per cell (e.g., one of eight programmed states), and a quaternary cell (QLC) may store four bits of data per cell. MLC is used herein in its broader context to refer to any memory cell that can store more than one bit of data per cell (i.e., can represent more than two programmed states).

Memory array 120 may include a plurality of memory cells arranged in, for example, a plurality of devices, planes, sub-blocks, or pages. As one example, a 48GB TLC NAND memory device may contain 18,592 bytes of data per page (16,384+2208 bytes), 1536 pages per block, 548 blocks per plane, and 4 or more planes per device. As another example, a 32GB MLC memory device, storing two bits of data per cell (i.e., 4 programmable states), may contain 18,592 bytes of data (B) per page (16,384+2208 bytes), 1024 pages per block, 548 blocks per plane, and 4 planes per device, but the required write time is reduced by half, while the program/erase (P/E) period of the corresponding TLC memory device is increased by two times. Other examples may include other numbers or arrangements. In some examples, the memory device or portions thereof may be selectively operated in SLC mode or in a desired MLC mode (e.g., TLC, QLC, etc.).

In operation, data is typically written to or read from memory device 110 in pages and erased in blocks. However, one or more memory operations (e.g., read, write, erase, etc.) may be performed on larger or smaller groups of memory cells, as desired. The data transfer size of the memory device 110 is commonly referred to as a page, while the data transfer size of the host is commonly referred to as a sector.

Different types of memory cells or memory arrays 120 may provide different page sizes, or may require different amounts of metadata associated therewith. For example, different memory device types may have different error rates, which may result in different amounts of metadata being necessary to ensure data page integrity (e.g., a memory device with a higher error rate may require more bytes of error correction code data than a memory device with a lower error rate). As an example, MLC NAND flash devices may have a higher bit error rate than corresponding single-level cell (SLC) NAND flash devices. Thus, MLC devices may require more bytes of metadata for error data than corresponding SLC devices.

Array controller 135 may include an Error Correction Code (ECC) component 140, and Error Correction Code (ECC) component 140 may include, among other things, an ECC engine or other circuitry configured to detect or correct errors associated with writing data to or reading data from one or more memory cells of memory device 110 coupled to memory controller 115. For example, the ECC component 140 may detect or calculate a Bit Error Rate (BER) associated with performing a plurality of memory operations. The BER may correspond to a bit error occurring in a latch of the I/O bus, an internal error of the controller 115, an error occurring in one or more NAND arrays, or an error occurring in one or more Multi-level cells (MLCs) of the memory device 110. Memory controller 115 may be configured to proactively detect and recover from error occurrences (e.g., bit errors, operational errors, crash conditions, stalls, hangs, etc.) associated with various operations or storage of data, while maintaining the integrity of data transferred between host 105 and memory device 110, or maintaining the integrity of stored data (e.g., using redundant RAID storage devices, etc.), and may remove (e.g., log out) failed memory resources (e.g., memory units, memory arrays, pages, blocks, etc.) to prevent future errors. Memory controller 115 may include a command queue (not shown) that tracks memory commands received from a host. The commands in the queue may be executed by the controller 115 in a first-in-first-out (FIFO) manner, a stacked manner, out of order, according to priority, or in any other suitable order. The command queue contains state information associated with each command in the queue. Such status information may include the BER of the given command, the number of remaining blocks associated with the given command, and a timestamp representing the time interval since the given command was received by memory device 110.

Memory manager 125 may include, among other things, circuitry or firmware, such as a plurality of components or integrated circuits associated with various memory management functions. For the purposes of this description, example memory operations and management functions will be described in the context of a NAND memory. Those skilled in the art will recognize that other forms of non-volatile memory may have similar memory operation or management functions. Such NAND management functions include wear leveling (e.g., garbage collection or reclamation), error detection (e.g., BER monitoring) or correction, block logging, or one or more other memory management functions. The memory manager 125 may parse or format host commands (e.g., commands received from a host) into device commands (e.g., commands associated with operation of a memory array, etc.), or generate device commands for the array controller 135 or one or more other components of the memory device 110 (e.g., to accomplish various memory management functions).

Memory manager 125 may contain a set of management tables 130, the set of management tables 130 configured to maintain various information associated with one or more components of memory device 110 (e.g., various information associated with a memory array or one or more memory cells coupled to memory controller 115). For example, the management table 130 may contain information regarding block lifetimes, block erase counts, error histories, error parameter information, or one or more error counts (e.g., write operation error counts, read bit error counts, read operation error counts, erase error counts, etc.) of one or more blocks of memory cells coupled to the memory controller 115. In some examples, a bit error may be referred to as an uncorrectable bit error if the number of errors detected for one or more error counts (e.g., error parameters) is above a threshold (e.g., an allowable error threshold). Management table 130 may maintain a count of bit errors that may or may not be correctable, and so forth.

Memory array 120 may include a plurality of memory cells arranged in, for example, a plurality of devices, planes, sub-blocks, or pages. As one example, a 48GB TLC NAND memory device may contain 18,592 bytes of data per page (16,384+2208 bytes), 1536 pages per block, 548 blocks per plane, and 4 or more planes per device. As another example, a 32GB MLC memory device, storing two bits of data per cell (i.e., 4 programmable states), may contain 18,592 bytes of data (B) per page (16,384+2208 bytes), 1024 pages per block, 548 blocks per plane, and 4 planes per device, but the required write time is reduced by half, while the program/erase (P/E) period of the corresponding TLC memory device is increased by two times. Other examples may include other numbers or arrangements. In some examples, the memory device or portions thereof may be selectively operated in SLC mode or in a desired MLC mode (e.g., TLC, QLC, etc.).

In operation, data is typically written to or read from memory device 110 in pages and erased in blocks. However, one or more memory operations (e.g., read, write, erase, etc.) may be performed on larger or smaller groups of memory cells, as desired. The data transfer size of the memory device 110 is commonly referred to as a page, while the data transfer size of the host is commonly referred to as a sector.

Different types of memory cells or memory arrays 120 may provide different page sizes, or may require different amounts of metadata associated therewith. For example, different memory device types may have different error rates, which may result in different amounts of metadata being necessary to ensure data page integrity (e.g., a memory device with a higher error rate may require more bytes of error correction code data than a memory device with a lower error rate). As an example, MLC NAND flash devices may have a higher bit error rate than corresponding single-level cell (SLC) NAND flash devices. Thus, MLC devices may require more bytes of metadata for error data than corresponding SLC devices.

Fig. 2 depicts an example of a host model database 200. The host model database 200 contains multiple entries 212, 214, 216, 218 for different command types and specifies average parameters for each command type. Each entry contains a memory device command type field 210, an average data size field 220, an average pending interval field 230, a relationship to other memory device commands field 240, and an average arrival rate field 250.

The memory device command type field 210 contains values representing different types of commands. Examples of command types include single block write, single block read, multi-block write, and multi-block read commands, among others. When commands, such as those obtained from a command queue of the memory device, are encountered, the command type of each command may be determined and entered into the memory device command type field 210. In an example, this entry may affect the possible values of the other fields (e.g., fields 220 through 250).

For example, if it is determined that a given set of commands stored in the command queue received during a given time interval are single block write commands, the average data size of each of these single block write commands may be calculated and stored in the average data size field 220 of the entry 212. In an example, after each single block write command on the memory device is successfully completed, for each single block write command, a difference between a timestamp corresponding to when the respective single block write command completed and a timestamp corresponding to when the respective single block write command was received from the host may be calculated and input into the average pending interval 203 of entries 212. The host model module 160 averages these calculated differences for each monolithic block write command and stores the calculated differences in the average pending interval field 230 corresponding to the entry 212 associated with the monolithic block write command field 210. The host model module 160 may also calculate the difference between the timestamps indicating when pairs of monolithic block write commands were received in sequence, calculate an average of these differences across all monolithic block write commands received during a given time interval, and store this average of the differences in the average arrival rate field 250 of the entries 212 associated with the monolithic block write command field 210.

For the inter-command relationship field 240, relationships between different types of commands may be determined and stored. For example, it is determined that each single block write command is received at all times or after receiving three multi-block read commands from the host more than a threshold number of times. Here, the command queue may be analyzed to determine that the multi-block write commands are separated from each other by three sequential multi-block read commands. In this case, a single block write command is stored in field 240 of entry 212 following the indication of three sequential multi-block read commands.

In an example, the number of non-single block write commands received between each received single block write command, e.g., commands of a type other than or different from the command type specified in the command type field 210 of the single block write command entry 212, may be counted. This count may be stored as the average arrival rate field 250 of the single block write command entry 212.

Operations similar to those mentioned above may be performed to populate the average data size field 220, average pending interval field 230, relationship to other memory device commands field 240, and average arrival rate field 250 of the database 200 corresponding to the remaining memory device command type field 210 of entries 214, 216, and 218.

FIG. 3 is a flow chart of an example of a method 300 for host adaptive memory device optimization. The operations of method 300 are implemented in computer hardware, such as described above (e.g., a memory controller) or described below (e.g., processing circuitry).

At operation 305, the memory device maintains a host model of interactions with the host. The host model is a data structure used to identify the mode in which the memory device interacts with the host. The data structure may take several forms, such as a database as depicted in FIG. 2, an Artificial Neural Network (ANN), one or more parameterized functions, and so forth. In an example, the host model is one of several host models provided to the memory device at the time of manufacture. These host models may be instantiated in view of cognitive types of hosts (e.g., mobile phone host models, battery-powered sensor host models, utility-enabled server host models, etc.). In an example, a memory device creates a host model via taking observations of a host.

At operation 310, a set of commands from a host is evaluated to create a configuration file for the set of commands. This set of commands may be a current set of commands (e.g., within a time window that includes the current time), commands in a command queue of the memory device, or a series of previous commands received by the memory device. In an example, to evaluate the set of commands, characteristics of commands in the set of commands are measured. In an example, the characteristic is one of a data size, a pending interval, a command interval, a relationship to other types of memory device operations, an arrival rate, a depth of a command queue. Thus, a profile is a result of a certain value from a command measurement. Numerical results may include additional processing such as calculating averages, medians, modes, regression analysis, or other metrics that may be used for comparison.

At operation 315, the configuration file is compared to the host model to determine inconsistencies between the configuration file and the host model. Here, the inconsistency is a deviation from the profile value predicted by the host model and the profile actual value. In an example, the configuration file is created via a different calculation than the corresponding values in the host model. For example, the host model value may be a single value combination (e.g., average) of several data elements, while the profile value is a single data element value. In an example, to compare a configuration file to a host model, representations of characteristics of individual commands are retrieved from the host model, and corresponding characteristics of a subset of commands from a set of commands are compared to the representations of characteristics. After comparing the subset of commands to the host model, it is determined that the corresponding characteristic is greater than or less than the representation of the characteristic by more than a threshold. The determined values (e.g., sizes) are inconsistent.

In an example, the subset of commands corresponds to a single type of command. In an example, the type of command is one of read, write, clear, erase, move, or garbage collection. Thus, here, similar commands are compared to similar commands. In one example, the representation of the characteristic is an average. As mentioned above, other statistical measures may be used. For example, an ANN may be trained to produce a certain output when exposed to a characteristic. The output of the ANN (e.g., the classification of the characteristic produced by the ANN) may be a representation of the characteristic. Other techniques, such as the result of a function, may also be used. However, a uniform theme among these technologies is the ability to compare representations of characteristics with corresponding values stored in the host model.

In an example, the number of subsets of commands exceeds a second threshold to produce an inconsistency. This example limits the sensitivity of the comparison to deviations. Thus, if the subset of commands are not valid (e.g., exceed a threshold), they are considered outliers and will not affect the operation of the memory device.

In an example, a set of commands are commands in a command queue of a memory device. Here, the inconsistency is the difference between the depth of the command queue and the average depth of the command queue stored in the host model. This is a form of integrated analysis whereby the command stream characteristics are compared, and not necessarily the commands themselves. Such analysis may be used to determine burst patterns, sleep-wake cycles, etc. of the host. In an example, the unified analysis may be combined with the specific command analysis. Thus, for example, the command queue depth of write commands may be compared.

At operation 320, the operation of the memory device is modified based on the inconsistency determined in operation 315. In an example, modifying the operation of the memory device includes altering at least one of a host timeout interval, a watchdog timer, a write cache size, a flush frequency, a block alignment parameter, a garbage collection frequency, or a wear leveling parameter. Modifying these operations may have different effects on the actual or perceived operation of the memory device relative to the host. For example, if the host is operating in a bursty nature, i.e., a long period of inactivity following a short period of high activity, then increasing the write cache may increase the write throughput of the host; data is written from the cache during the inactive period.

In an example, at least one of the host time-out interval or the watchdog timer is altered based on a time metric relative to receipt of the given command and receipt of a subsequent reset signal from the host for the given command. Such adjustments keep the timers of the memory device consistent with legacy host behavior. Thus, if, for example, the intra-command and reset times are reduced, then shortening the timeout will recover sooner after a possible failed operation.

In an example, the method 300 may be extended to include operations for updating a host model to resolve an inconsistency. This enables the host model to track changes in the host over time. These changes may occur due to software or firmware changes on the host, different peripheral device accessories, or simply changing the workload. Updating the host model enables a dynamic host behavior configuration process to ensure that the memory device has better operation with respect to host operation. In one example, to update the host model, entries for the mean characteristic of a group of commands are modified to contain inconsistencies in the mean characteristic. Thus, the average is modified to also average new values for the properties from a set of commands. In an example, the average characteristic is one of a data size, a pending interval, a relationship to other types of memory device operations, or an arrival rate.

Fig. 4 depicts a block diagram of an example machine 400 that may be used to perform any one or more of the techniques (e.g., methods) discussed herein. In alternative embodiments, the machine 400 may operate as a standalone device or may be connected (e.g., networked) to other machines. In a networked deployment, the machine 400 may operate in the capacity of a server machine, a client machine, or both, in server-client network environments. In an example, the machine 400 may act as a peer machine in a peer-to-peer (P2P) (or other distributed) network environment. The machine 400 may be a Personal Computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a mobile telephone, a web appliance, an IoT device, an automotive system, or any machine capable of executing instructions (sequential or otherwise) that specify operations to be performed by that machine. Further, while only a single machine is depicted, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein, such as cloud computing, software as a service (SaaS), other computer cluster configurations.

Examples as described herein may include, or be operable by, logic, components, devices, packages, or mechanisms. A circuit system is a collection (e.g., a group) of circuits implemented in a tangible entity that contains hardware (e.g., simple circuits, gates, logic, and so on). The circuitry membership may be flexible over time and underlying hardware variability. The circuitry includes members that may perform particular tasks in operation, either individually or in combination. In an example, the hardware of the circuitry may be designed unchanged to perform a particular operation (e.g., hardwired). In an example, the hardware of the circuitry may include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.), computer readable media containing instructions that are physically modified (e.g., magnetically, electrically, movably placing a constant mass of particles, etc.) to encode a particular operation. When physical components are connected, the underlying electrical properties of the hardware components change, for example, from an insulator to a conductor, and vice versa. The instructions enable participating hardware (e.g., execution units or loading mechanisms) to create members of circuitry in the hardware via variable connections to perform portions of specific tasks when operating. Thus, when the device operates, the computer-readable medium is communicatively coupled to other components of the circuitry. In an example, any physical component may be used in more than one member of more than one circuitry. For example, under operation, an execution unit may be used in a first circuit of a first circuitry at one point in time and reused by a second circuit in the first circuitry or by a third circuit in the second circuitry at a different time.

A machine (e.g., computer system) 400 (e.g., host device 105, memory device 110, etc.) may include a hardware processor 402 (e.g., a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a hardware processor core, or any combination thereof, such as memory controller 115, etc.), a main memory 404, and a static memory 406, some or all of which may communicate with each other via an interconnect (e.g., bus) 430. The machine 400 may further include a display unit 410, an alphanumeric input device 412 (e.g., a keyboard), and a User Interface (UI) navigation device 414 (e.g., a mouse). In an example, the display unit 410, the input device 412 and the UI navigation device 414 may be a touch screen display. The machine 400 may additionally include a storage device (e.g., drive unit) 408, a signal generation device 418 (e.g., a speaker), a network interface device 420, and one or more sensors 416, such as a Global Positioning System (GPS) sensor, compass, accelerometer, or other sensor. The machine 400 may include an output controller 428, such as a serial (e.g., Universal Serial Bus (USB), parallel, or other wired or wireless (e.g., Infrared (IR), Near Field Communication (NFC), etc.) connection to communicate with or control one or more peripheral devices (e.g., a printer, card reader, etc.).

Storage 408 may include a machine-readable medium 422, on which is stored one or more sets of data structures or instructions 424 (e.g., software) embodying or utilized by any one or more of the techniques or functions described herein. The instructions 424 may also reside, completely or at least partially, within the main memory 404, within static memory 406, or within the hardware processor 402 during execution thereof by the machine 400. In an example, one or any combination of the hardware processor 402, the main memory 404, the static memory 406, or the storage device 408 may constitute the machine-readable medium 422

While the machine-readable medium 422 is depicted as a single medium, the term "machine-readable medium" may include a single medium or multiple media (e.g., a centralized or distributed database, or associated caches and servers) that are configured to store the one or more instructions 424.

The term "machine-readable medium" may include any medium that is capable of storing, encoding or carrying instructions for execution by the machine 400 and that cause the machine 400 to perform any one or more of the techniques of the present invention or that is capable of storing, encoding or carrying data structures used by or associated with such instructions. Non-limiting examples of machine-readable media may include solid-state memory, as well as optical and magnetic media. In an example, the number of machine-readable media includes a machine-readable medium having a plurality of particles with an invariant (e.g., static) mass. Thus, a number of machine-readable media are not transitory propagating signals. Specific examples of a number of machine-readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

Instructions 424 (e.g., software, programs, an Operating System (OS), etc.) or other data are stored on the storage device 421 and may be accessed by the memory 404 for use by the processor 402. The memory 404, such as DRAM, is typically fast, but volatile, and thus is a different type of storage device than the storage device 421 (such as SSD) that is suitable for long-term storage, including when in an "off condition. Instructions 424 or data used by a user or the machine 400 are typically loaded into memory 404 for use by the processor 402. When memory 404 is full, virtual space from storage 421 may be allocated to supplement memory 404; however, because storage 421 is typically slower than memory 404, and write speeds are typically at least twice slower than read speeds, the use of virtual memory can greatly reduce user experience (in contrast to memory 404 (e.g., DRAM)) due to storage latency. Furthermore, using storage 421 for virtual memory can greatly reduce the lifetime of storage 421.

Virtual memory compression (e.g., virtual memory compression) as opposed to virtual memoryKernel feature "ZRAM") uses portions of memory as compressed block memory to avoid paging to storage 421. Paging is performed in compressed blocks until it is necessary to write such data to storage 421. Virtual memory compression increases the available size of memory 404 while reducing wear on storage device 421.

Storage devices optimized for mobile electronic devices, or mobile storage devices, traditionally include MMC solid state storage devices (e.g. micro secure digital (microSD)^TM) Cards, etc.). MMC devices include multiple parallel interfaces (e.g., 8-bit parallel interfaces) that interface with a host device, and are often components that are removable and separate from the host device. In contrast, eMMC^TMThe device is attached to a circuit board and considered as a component of a host device with a read speed comparable to that of a serial ATA based device^TM(Serial AT (advanced technology) Accessories or SATsA) The SSD device of (1). However, there is an ever increasing demand for mobile device performance, such as fully enabling virtual devices or augmented reality devices, utilizing ever increasing network speeds, and so forth. In response to this demand, the storage device has been shifted from a parallel communication interface to a serial communication interface. A Universal Flash Storage (UFS) device, including a controller and firmware, communicates with a host device using a Low Voltage Differential Signaling (LVDS) serial interface with a dedicated read/write path, further improving read/write speed.

The instructions 424 may further be transmitted or received over a communication network 426 using a transmission medium via the network interface device 420 utilizing any of a variety of transmission protocols (e.g., frame relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), hypertext transfer protocol (HTTP), etc.). An example communication network may include: a Local Area Network (LAN); a Wide Area Network (WAN); packet data networks (e.g., the internet); mobile telephony networks (e.g., cellular networks), such as those defined by the third generation partnership project (3GPP) series of standards (e.g., 3G, 4G, 5G, Long Term Evolution (LTE), etc.); plain Old Telephone (POTS) networks; and wireless data networks (e.g., Institute of Electrical and Electronics Engineers (IEEE)802.11 family of standards (referred to as) IEEE 802.15.4 series of standards, peer-to-peer (P2P) networks, and so on. In an example, the network interface device 420 may contain one or more physical jacks (e.g., ethernet, coaxial, or telephone jacks) or one or more antennas to connect to the communication network 426. In an example, the network interface device 420 may include multiple antennas to wirelessly communicate using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) techniques. The term "transmission medium" shall be taken to include any intangible medium that may store, encode, or carry instructions for execution by the machine 400, and includes digital or analog communications signals or other intangible medium to facilitate communication of such software.

Additional examples:

example 1 is a memory device for host adaptive memory device optimization, the memory device comprising: a storage to maintain a host model of interactions with a host; and processing circuitry to: evaluating a set of commands from the host to create a profile of the set of commands; comparing the configuration file to the host model to determine an inconsistency between the configuration file and the host model; and modifying operation of the memory device based on the inconsistency.

In example 2, the subject matter of example 1, wherein, to evaluate the set of commands, the processing circuitry is configured to measure a characteristic of a command of the set of commands.

In example 3, the subject matter of example 2, wherein the characteristic is one of a data size, a pending interval, a command interval, a relationship to other types of memory device operations, an arrival rate, a depth of a command queue.

In example 4, the subject matter of any of examples 2 to 3, wherein, to compare the configuration file to the host model, the processing circuitry is configured to: retrieving a representation of the characteristics of a single command from the host model; comparing respective characteristics of a subset of commands from the set of commands to the representation of the characteristics; and determining that the corresponding characteristic is greater than or less than the representation of the characteristic by a threshold amount to produce the inconsistency.

In example 5, the subject matter of example 4, wherein the representation of the characteristic is an average.

In example 6, the subject matter of any one of examples 4 to 5, wherein the number of subsets of commands exceeds a second threshold to produce the inconsistency.

In example 7, the subject matter of any one of examples 2 to 6, wherein the subset of commands corresponds to a single type of command.

In example 8, the subject matter of example 7, wherein the type of command is one of read, write, clear, erase, move, or garbage collection.

In example 9, the subject matter of any of examples 1 to 8, wherein the set of commands are commands in a command queue of the memory device, and wherein the inconsistency is a difference between a depth of the command queue and an average depth of the command queue stored in the host model.

In example 10, the subject matter of any of examples 1 to 9, wherein, to modify the operation of the memory device, the processing circuitry is configured to alter at least one of a host timeout interval, a watchdog timer, a write cache size, a flush frequency, a block alignment parameter, a garbage collection frequency, or a wear leveling parameter.

In example 11, the subject matter of example 10, wherein at least one of the host timeout interval or the watchdog timer is altered based on a measure of time relative to receipt of a given command and receipt of a subsequent reset signal from the host for the given command.

In example 12, the subject matter of any of examples 1 to 11, wherein the processing circuitry is configured to update the host model to resolve the inconsistency.

In example 13, the subject matter of example 12, wherein, to update the host model, the processing circuitry is configured to modify an entry of a mean characteristic of the set of commands to include the inconsistency in the mean characteristic.

In example 14, the subject matter of any of examples 12 to 13, wherein the average characteristic is one of a data size, a pending interval, a relationship to other types of memory device operations, or an arrival rate.

Example 15 is a method for host adaptive memory device optimization, the method comprising: maintaining, by a memory device, a host model of interactions with a host; evaluating a set of commands from the host to create a profile of the set of commands; comparing the configuration file to the host model to determine an inconsistency between the configuration file and the host model; and modifying operation of the memory device based on the inconsistency.

In example 16, the subject matter of example 15, wherein evaluating the set of commands comprises measuring a characteristic of a command in the set of commands.

In example 17, the subject matter of example 16, wherein the characteristic is one of a data size, a pending interval, a command interval, a relationship to other types of memory device operations, an arrival rate, a depth of a command queue.

In example 18, the subject matter of any of examples 16 to 17, wherein comparing the configuration file to the host model comprises: retrieving a representation of the characteristics of a single command from the host model; comparing respective characteristics of a subset of commands from the set of commands to the representation of the characteristics; and determining that the corresponding characteristic is greater than or less than the representation of the characteristic by a threshold amount to produce the inconsistency.

In example 19, the subject matter of example 18, wherein the representation of the characteristic is an average.

In example 20, the subject matter of any of examples 18 to 19, wherein the number of subsets of commands exceeds a second threshold to produce the inconsistency.

In example 21, the subject matter of any of examples 16 to 20, wherein the subset of commands corresponds to a single type of command.

In example 22, the subject matter of example 21, wherein the type of command is one of read, write, clear, erase, move, or garbage collection.

In example 23, the subject matter of any of examples 15 to 22, wherein the set of commands are commands in a command queue of the memory device, and wherein the inconsistency is a difference between a depth of the command queue and an average depth of the command queue stored in the host model.

In example 24, the subject matter of any of examples 15 to 23, wherein modifying the operation of the memory device includes altering at least one of a host timeout interval, a watchdog timer, a write cache size, a flush frequency, a block alignment parameter, a garbage collection frequency, or a wear leveling parameter.

In example 25, the subject matter of example 24, wherein at least one of the host timeout interval or the watchdog timer is altered based on a measure of time relative to receipt of a given command and receipt of a subsequent reset signal from the host for the given command.

In example 26, the subject matter of any of examples 15 to 25, comprising updating the host model to resolve the inconsistency.

In example 27, the subject matter of example 26, wherein updating the host model includes modifying an entry of a mean characteristic of the set of commands to include the inconsistency in the mean characteristic.

In example 28, the subject matter of any of examples 26 to 27, wherein the average characteristic is one of a data size, a pending interval, a relationship to other types of memory device operations, or an arrival rate.

Example 29 is a machine-readable medium comprising instructions for host adaptive memory device optimization, which when executed by processing circuitry causes the processing circuitry to perform operations comprising: maintaining, by a memory device, a host model of interactions with a host; evaluating a set of commands from the host to create a profile of the set of commands; comparing the configuration file to the host model to determine an inconsistency between the configuration file and the host model; and modifying operation of the memory device based on the inconsistency.

In example 30, the subject matter of example 29, wherein evaluating the set of commands comprises measuring a characteristic of a command in the set of commands.

In example 31, the subject matter of example 30, wherein the characteristic is one of a data size, a pending interval, a command interval, a relationship to other types of memory device operations, an arrival rate, a depth of a command queue.

In example 32, the subject matter of any of examples 30 to 31, wherein comparing the configuration file to the host model comprises: retrieving a representation of the characteristics of a single command from the host model; comparing respective characteristics of a subset of commands from the set of commands to the representation of the characteristics; and determining that the corresponding characteristic is greater than or less than the representation of the characteristic by a threshold amount to produce the inconsistency.

In example 33, the subject matter of example 32, wherein the representation of the characteristic is an average.

In example 34, the subject matter of any of examples 32 to 33, wherein the number of subsets of commands exceeds a second threshold to produce the inconsistency.

In example 35, the subject matter of any of examples 30 to 34, wherein the subset of commands corresponds to a single type of command.

In example 36, the subject matter of example 35, wherein the type of command is one of read, write, clear, erase, move, or garbage collection.

In example 37, the subject matter of any of examples 29 to 36, wherein the set of commands are commands in a command queue of the memory device, and wherein the inconsistency is a difference between a depth of the command queue and an average depth of the command queue stored in the host model.

In example 38, the subject matter of any of examples 29 to 37, wherein modifying the operation of the memory device includes altering at least one of a host timeout interval, a watchdog timer, a write cache size, a flush frequency, a block alignment parameter, a garbage collection frequency, or a wear leveling parameter.

In example 39, the subject matter of example 38, wherein at least one of the host timeout interval or the watchdog timer is altered based on a measure of time relative to receipt of a given command and receipt of a subsequent reset signal from the host for the given command.

In example 40, the subject matter of any of examples 29 to 39, wherein the operations comprise updating the host model to resolve the inconsistency.

In example 41, the subject matter of example 40, wherein updating the host model comprises modifying an entry of a mean characteristic of the set of commands to include the inconsistency in the mean characteristic.

In example 42, the subject matter of any of examples 40 to 41, wherein the average characteristic is one of a data size, a pending interval, a relationship to other types of memory device operations, or an arrival rate.

Example 43 is a system for host adaptive memory device optimization, the system comprising: means for maintaining, by a memory device, a host model of interactions with a host; means for evaluating a set of commands from the host to create a profile of the set of commands; means for comparing the configuration file to the host model to determine an inconsistency between the configuration file and the host model; and means for modifying an operation of the memory device based on the inconsistency.

In example 44, the subject matter of example 43, wherein the means for evaluating the set of commands includes means for measuring a characteristic of a command in the set of commands.

In example 45, the subject matter of example 44, wherein the characteristic is one of a data size, a pending interval, a command interval, a relationship to other types of memory device operations, an arrival rate, a depth of a command queue.

In example 46, the subject matter of any of examples 44 to 45, wherein the means for comparing the configuration file to the host model comprises: means for retrieving a representation of the characteristic of a single command from the host model; means for comparing respective characteristics of a subset of commands from the set of commands to the representation of the characteristics; and means for determining that the corresponding characteristic is greater than or less than the representation of the characteristic by a threshold amount to produce the inconsistency.

In example 47, the subject matter of example 46, wherein the representation of the characteristic is an average.

In example 48, the subject matter of any one of examples 46 to 47, wherein the number of subsets of commands exceeds a second threshold to produce the inconsistency.

In example 49, the subject matter of any one of examples 44 to 48, wherein the subset of commands corresponds to a single type of command.

In example 50, the subject matter of example 49, wherein the type of command is one of read, write, clear, erase, move, or garbage collection.

In example 51, the subject matter of any of examples 43 to 50, wherein the set of commands are commands in a command queue of the memory device, and wherein the inconsistency is a difference between a depth of the command queue and an average depth of the command queue stored in the host model.

In example 52, the subject matter of any of examples 43 to 51, wherein the means for modifying the operation of the memory device includes means for altering at least one of a host timeout interval, a watchdog timer, a write cache size, a flush frequency, a block alignment parameter, a garbage collection frequency, or a wear leveling parameter.

In example 53, the subject matter of example 52, wherein at least one of the host timeout interval or the watchdog timer is altered based on a measure of time relative to receipt of a given command and receipt of a subsequent reset signal from the host for the given command.

In example 54, the subject matter of any of examples 43 to 53, comprising means for updating the host model to resolve the inconsistency.

In example 55, the subject matter of example 54, wherein the means for updating the host model includes means for modifying an entry of a mean characteristic of the set of commands to include the inconsistency in the mean characteristic.

In example 56, the subject matter of any of examples 54 to 55, wherein the average characteristic is one of a data size, a pending interval, a relationship to other types of memory device operations, or an arrival rate.

Example 57 is at least one machine readable medium comprising instructions that, when executed by processing circuitry, cause the processing circuitry to perform operations to implement any of examples 1-56.

Example 58 is an apparatus comprising means for implementing any of examples 1 to 56.

Example 59 is a system to implement any of examples 1 to 56.

Example 60 is a method for implementing any of examples 1 to 56.

The foregoing detailed description has included references to the accompanying drawings, which form a part hereof. The drawings show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as "examples. Such examples may also include elements other than those illustrated or described. However, the inventors also contemplate examples in which only those elements shown or described are provided. Moreover, the inventors also contemplate examples of any combination or permutation of those elements (or one or more aspects thereof) shown or described with respect to a particular example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) shown or described herein.

In this document, the terms "a" and "an" are used as they are common in patent documents to include one or more, independent of any other instances or usages of "at least one" or "one or more. In this document, unless otherwise indicated, the term "or" is used to refer to a non-exclusive or, such that "a or B" may include "a instead of B", "B instead of a", and "a and B". In the appended claims, the terms "including" and "in which" are used as the plain-english equivalents of the respective terms "comprising" and "in which". Furthermore, in the following claims, the terms "comprising" and "including" are open-ended, that is, a system, apparatus, article, or process that includes elements in addition to those listed in a claim after such term is still considered to be within the scope of the claims. Furthermore, in the appended claims, the terms "first," "second," and "third," etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.

In various examples, a component, controller, processor, unit, engine, or table described herein may contain, among other things, physical circuitry or firmware stored on a physical device. As used herein, "processor" refers to any type of computing circuit, such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a Digital Signal Processor (DSP), or any other type of processor or processing circuit, including a set of processors or multi-core devices.

The terms "wafer" and "substrate" are used herein to generally refer to any structure on which an integrated circuit is formed, and also to such structures during various stages of integrated circuit fabrication. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of various embodiments is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled.

Various embodiments in accordance with the present invention and described herein include memories that utilize a vertical structure of memory cells, such as NAND strings of memory cells. As used herein, the directional adjective will be considered relative to the substrate surface on which the memory cells are formed (i.e., the vertical structure will be considered to extend away from the substrate surface, the bottom end of the vertical structure will be considered to be the end closest to the substrate surface, and the top end of the vertical structure will be considered to be the end furthest from the substrate surface).

As used herein, operating a memory cell includes reading from, writing to, or erasing a memory cell. The operation of placing a memory cell in a desired state is referred to herein as "programming" and may include both writing to the memory cell or erasing from memory (e.g., the memory cell may be programmed to an erased state).

According to one or more embodiments of the invention, a memory controller (e.g., processor, controller, firmware, etc.) located inside or outside of a memory device is able to determine (e.g., select, set, adjust, calculate, alter, clear, communicate, adapt, derive, define, utilize, modify, apply, etc.) a number of wear cycles or wear states (e.g., record wear cycles, count operations of the memory device as they occur, track operations of the memory device it initiates, evaluate memory device characteristics corresponding to the wear states, etc.).

In accordance with one or more embodiments of the present invention, a memory access device may be configured to provide wear cycle information to the memory device on each memory operation. Memory device control circuitry (e.g., control logic) can be programmed to compensate for memory device performance variations corresponding to wear cycle information. The memory device may receive wear cycle information and determine one or more operating parameters (e.g., values, characteristics) in response to the wear cycle information.

The method examples described herein may be machine or computer-implemented, at least in part. Some examples may include a computer-readable or machine-readable medium encoded with instructions operable to configure an electronic device to perform a method as described in the above examples. Embodiments of such methods may comprise code, such as microcode, assembly language code, a high-level language code, and the like. Such code may contain computer readable instructions for performing various methods. The code may form part of a computer program product. Further, the code can be tangibly stored on one or more volatile or non-volatile tangible computer-readable media, e.g., during execution or at other times. Examples of such tangible computer-readable media may include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact disks and digital video disks), cartridge tapes, memory cards or sticks, Random Access Memories (RAMs), Read Only Memories (ROMs), Solid State Drives (SSDs), universal flash memory (UFS) devices, embedded mmc (emmc) devices, and so forth.

The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with each other. Upon reviewing the above description, other embodiments may be utilized, such as by one of ordinary skill in the art. This document is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Furthermore, in the foregoing detailed description, various features may be grouped together to simplify the present invention. This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment, and it is contemplated that such embodiments may be combined with each other in various combinations or permutations. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.