阅读说明：本技术 一种单片集成型平衡光电探测器芯片及制作方法 (Monolithic integrated balanced photoelectric detector chip and manufacturing method thereof ) 是由 崔大健 高新江 陈扬 王立 周浪 于 2019-11-21 设计创作，主要内容包括：本发明属半导体技术领域,具体涉及一种单片集成型平衡光电探测器芯片,所述芯片包括两个并行的光电探测器单元串联集成,光电探测器单元为正入光、台面型双异质PIN结构；光电探测器单元采用半绝缘衬底,半绝缘衬底上沉积有半导体材料结构外延层；芯片的台面上设置有P电极、N电极以及信号输出端,且P电极、N电极和信号输出端为同面引出；其中,P电极通过从P+区域的接触环电极引出,并经过台面延伸到半绝缘衬底表面；N电极从N+区域的半导体接触层引出到半绝缘衬底表面；信号输出端由两个探测器单元的串联连接处引出；本发明将两个并行InGaAs光电探测器串联单片集成,降低了单元间的间距和寄生参数,实现了高速率和集成化。(The invention belongs to the technical field of semiconductors, and particularly relates to a monolithic integrated balanced photoelectric detector chip which comprises two parallel photoelectric detector units which are integrated in series, wherein the photoelectric detector units are of a positive incidence light and mesa type double-heterogeneous PIN structure; the photoelectric detector unit adopts a semi-insulating substrate, and a semiconductor material structure epitaxial layer is deposited on the semi-insulating substrate; a P electrode, an N electrode and a signal output end are arranged on the table top of the chip, and the P electrode, the N electrode and the signal output end are led out from the same plane; the P electrode is led out from the contact ring electrode of the P + region and extends to the surface of the semi-insulating substrate through the table top; the N electrode is led out from the semiconductor contact layer of the N + region to the surface of the semi-insulating substrate; the signal output end is led out from the serial connection position of the two detector units; the invention integrates two parallel InGaAs photodetectors in series and a single chip, reduces the space between units and parasitic parameters, and realizes high speed and integration.)

1. A monolithic integration type balance photoelectric detector chip is characterized by comprising two parallel photoelectric detector units (1) which are integrated in series, wherein the photoelectric detector units (1) are of a positive incidence light and mesa type double-heterogeneous PIN structure; the photoelectric detector unit adopts a semi-insulating substrate (2), and an epitaxial layer of a semiconductor material structure is deposited on the semi-insulating substrate (2);

a P electrode (13), an N electrode (15) and a signal output end (14) are arranged on the table-board of the monolithic integrated balanced photoelectric detector chip, and the P electrode (13), the N electrode (15) and the signal output end (14) are led out in the same plane; the P electrode (13) is led out from a contact ring electrode (16) of the P + region and extends to the surface of the semi-insulating substrate through the mesa; the N electrode (15) is led out from the semiconductor contact layer of the N + region to the surface of the semi-insulating substrate; the signal output (14) is derived from the series connection of the two detector units.

2. The monolithically integrated balanced photodetector chip according to claim 1, characterized in that the semi-insulating substrate epitaxial layers are deposited with a first semiconductor contact layer (21), an intrinsic absorber layer (22), a semiconductor cap layer (23) and a second semiconductor contact layer (24) from bottom to top.

3. A monolithically integrated balanced photodetector chip according to claim 2, characterized in that the doping concentration of the first semiconductor contact layer (21) is larger than 5 x 10¹⁸cm^-3(ii) a The doping concentration of the semiconductor cap layer (23) is more than 1 multiplied by 10¹⁸cm^-3(ii) a The second semiconductor contact layer (24) has a doping concentration greater than 5 x 10¹⁸cm^-3。

4. The monolithic balanced photodetector chip as claimed in any one of claims 2 to 3, wherein the semiconductor comprises an InP semiconductor, a GaAs semiconductor, a Si semiconductor or a GaN semiconductor; the material of the intrinsic absorption layer (22) comprises: InGaAs semiconductor material, Ge semiconductor material, or GaAs semiconductor material.

5. The monolithic integrated balanced photodetector chip of claim 1, wherein there are two photosensitive regions, a first photosensitive region (11) and a second photosensitive region (12), and the diameter of the two photosensitive regions is adjusted by the operating bandwidth of the integrated balanced photodetector chip; because the two balanced photoelectric detector units are of a vertical normal incidence type, the central distance D of the two photosensitive areas in the monolithic integrated balanced photoelectric detector chip is adjusted according to the incident space light distance.

6. A method for manufacturing a monolithic integrated balanced photodetector chip is characterized by comprising the following steps:

s1: sequentially depositing a first semiconductor contact layer (21), an intrinsic absorption layer (22), a semiconductor cap layer (23) and a second semiconductor contact layer (24) on a semi-insulating substrate (2) through Metal Organic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy (MBE);

s2: defining a P-type mesa region by adopting a photoetching process, and etching the mesa to a first semiconductor contact layer (21) in an ICP (inductively coupled plasma) dry method or RIE (reactive ion etching) dry method; or the mesa is etched to the first semiconductor contact layer (21) in a wet manner; or the mesa is etched to the first semiconductor contact layer (21) by adopting a mode of combining a dry method and a wet method;

s3: defining an N-type mesa region by adopting a photoetching process, and etching the mesa to the semi-insulating substrate (2) in an ICP (inductively coupled plasma) dry method or RIE (reactive ion etching) dry method; or the mesa is etched to the semi-insulating substrate (2) in a wet method; or the mesa is etched to the semi-insulating substrate (2) by adopting a mode of combining a dry method and a wet method;

s4: passivating the appearance of each region to form a surface passivation film;

s5: SiO on mesa by photolithography₂Defining a photosensitive area pattern on the mask, and etching the photosensitive area by HF;

s6: manufacturing a P electrode (13) and an N electrode (15) by adopting a stripping method with glue;

s7: processing the metal layer of the electrode by adopting a rapid annealing method to ensure good ohmic contact between the P electrode (13) and the N electrode (15);

s8: thinning and polishing the epitaxial wafer to 100-200 μm by adopting a chemical mechanical polishing mode;

s9: and carrying out scribing and cleavage on the wafer to finish the chip manufacturing.

7. The method of claim 6, wherein the etching the P-type mesa region comprises:

s21: cleaning the wafer with boiling stripping liquid, and washing the wafer clean and removing surface moisture by using deionized water;

s22: etching the deposited material to a certain depth by adopting an ICP dry method;

s23: carrying out P mesa etching on the epitaxial layer by using wet etching liquid, wherein the P mesa etching needs to etch the first semiconductor contact layer (21);

s24: soaking the wafer in corrosive liquid for a set time, washing with deionized water, boiling stripping liquid and removing photoresist;

s25: after cleaning the wafer, a layer of SiO is grown again₂A mask for carrying out passivation protection on the etched table top;

the method for etching the N-type mesa region is the same as the method for etching the P-type mesa region.

8. The method of claim 6, wherein the passivation film is formed by depositing SiNx, SiO2 or SiNxOy dielectric film by PECVD, or by coating BCB or PI.

9. The method for fabricating a monolithic balanced photodetector chip according to claim 6, characterized in that the fabrication of the P-electrode (12) and the N-electrode (13) comprises:

s61: defining electrode holes on the surface of the silicon nitride antireflection film by using a photoetching method;

s62: etching the redundant film layer by using hydrofluoric acid to etch a P-type contact hole and an N-type contact hole;

s63: manufacturing a metal contact layer of the electrode by adopting a photoetching stripping method;

s64: processing the metal layer of the electrode by using a rapid annealing method to ensure good ohmic contact of the P-type metal layer and the N-type metal layer;

s65: coating a layer of benzocyclobutene BCB on the surface of the wafer in a spin coating mode;

s66: baking benzocyclobutene BCB for 18-22 min at the low temperature of 85-95 ℃ for precuring, and then completely curing the BCB at the high temperature of 270-290 ℃ in an annealing furnace;

s67: etching a pattern by using a photoetching method to expose the position of the metal layer to be thickened;

s68: defining an evaporation area of the CPW coplanar electrode on the BCB by adopting a photoetching stripping process mode, manufacturing a CPW extension electrode on the surface of the BCB by adopting an electroplating method, and contacting with the P area metal layer and the N area metal layer; and finishing the manufacture of the electrode.

Technical Field

The invention belongs to the technical field of semiconductors, and relates to a monolithic integrated balanced photoelectric detector chip and a manufacturing method thereof.

Background

The spatial coherent laser communication has become a technological means with great potential for interplanetary high-speed information transmission, and has become a research hotspot at home and abroad at present. The balance photoelectric detector is used as a core photoelectric component of a coherent laser communication receiving system, and the position of the balance photoelectric detector is more important. The balanced photoelectric detector is widely applied to civil optical fiber communication, and the technology is relatively mature. The balance photoelectric detector applied to the coherent receiving system of the space laser communication needs to have the characteristics of high sensitivity, high consistency of performance parameters, integration miniaturization and the like due to the particularity of the balance photoelectric detector, and is easy to integrate with a front-end optical mixer.

The existing balance photoelectric detector mainly adopts two unit photoelectric detectors to realize internal balance on a circuit board, has large unit spacing and large parasitic parameters, can not be integrated with a space optical mixer subsequently, and can not realize high speed and integration.

Disclosure of Invention

In order to solve the above-mentioned problems of the prior art, the invention provides a monolithic integrated balanced photodetector chip, comprising:

two parallel photoelectric detector units 1 are integrated in series, and the photoelectric detector units 1 are of a positive light incidence and mesa type double-heterogeneous PIN structure; the photoelectric detector unit adopts a semi-insulating substrate, and an epitaxial layer of a semiconductor material structure is deposited on the semi-insulating substrate 2;

a P electrode 13, an N electrode 15 and a signal output end 14 are arranged on the table top of the monolithic integrated balanced photoelectric detector chip, and the P electrode 13, the N electrode 15 and the signal output end 14 are led out from the same plane; the P electrode 13 is led out from a contact ring electrode 16 of the P + region and extends to the surface of the semi-insulating substrate through the mesa; the N electrode 15 is led out from the semiconductor contact layer of the N + region to the surface of the semi-insulating substrate; the signal output 14 is derived from the series connection of the two detector units.

Preferably, the semi-insulating substrate epitaxial layer is deposited with a first semiconductor contact layer 21, an intrinsic absorption layer 22, a semiconductor cap layer 23 and a second semiconductor contact layer 24 from bottom to top in sequence.

Preferably, the doping concentration of the first semiconductor contact layer 21 is greater than 5 × 10¹⁸cm^-3(ii) a The doping concentration of the semiconductor cap layer 23 is more than 1 × 10¹⁸cm^-3(ii) a The doping concentration of the second semiconductor contact layer 24 is greater than 5 x 10¹⁸cm^-3。

Further, the semiconductor includes an InP semiconductor material, a GaAs semiconductor material, a Si semiconductor material, or a GaN material; the material of the intrinsic absorption layer comprises: InGaAs semiconductor material, Ge semiconductor material, or GaAs semiconductor material.

Preferably, the flat monolithic integrated balanced photoelectric detector chip is provided with two photosensitive regions, namely a first photosensitive region 11 and a second photosensitive region 12, and the diameters of the two photosensitive regions are adjusted through the working bandwidth of the integrated balanced photoelectric detector chip; the two balanced photoelectric detector units are of a vertical normal incidence type, and the central distance D of the two photosensitive areas in the monolithic integrated balanced photoelectric detector chip is adjusted according to the incident space light distance.

A method for fabricating a monolithic integrated balanced photodetector chip, the method comprising the steps of:

s1: on the semi-insulating substrate 2, sequentially depositing a first semiconductor contact layer 21, an intrinsic absorber layer 22, a semiconductor cap layer 23 and a second semiconductor contact layer 24 by Metal Organic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy (MBE);

s2: defining a P-type mesa region by adopting a photoetching process, and etching the mesa to the first semiconductor contact layer 21 in an ICP (inductively coupled plasma) dry method or RIE (reactive ion etching) dry method; or the mesa is etched to the first semiconductor contact layer 21 in a wet manner; or the mesa is etched to the first semiconductor contact layer 21 by combining a dry method and a wet method;

s3: defining an N-type mesa region by adopting a photoetching process, and etching the mesa to the semi-insulating substrate 2 in an ICP (inductively coupled plasma) dry method or RIE (reactive ion etching) dry method; or the mesa is etched to the semi-insulating substrate 2 in a wet method; or the mesa is etched to the semi-insulating substrate 2 by adopting a mode of combining a dry method and a wet method;

s4: passivating the appearance of each region to form a surface passivation film;

s5: SiO on mesa by photolithography₂Defining a photosensitive surface pattern on the mask, and etching a photosensitive area by HF;

s6: manufacturing a P electrode 13 and an N electrode 15 by adopting a stripping method with glue;

s7: the metal layer of the electrode is processed by adopting a rapid annealing method, so that good ohmic contact between the P electrode 13 and the N electrode 15 is ensured;

s8: thinning and polishing the epitaxial wafer to 100-200 μm by adopting a chemical mechanical polishing mode;

s9: and carrying out scribing and cleavage on the wafer to finish the chip manufacturing.

Preferably, the passivation film is formed by depositing a SiNx, SiO2 or SiNxOy dielectric film by plasma enhanced chemical vapor deposition PECVD, or by coating benzocyclobutene BCB or polyimide PI.

The invention reduces the space and parasitic parameters between units by connecting two parallel photoelectric detectors in series and integrating a single chip, thereby realizing high speed and integration; the detector unit adopts a positive incidence light and mesa double heterojunction PIN structure, so that the chip has the advantages of small dark current, low bias voltage, high working speed and high impedance output; the quantum efficiency and the working rate can be adjusted by adjusting the thickness of the intrinsic absorption layer; the detector unit adopts the semi-insulating substrate, not only is isolated and protected, but also reduces the crosstalk of photoelectric signals, and most of metal leads and bonding pads are manufactured on the semi-insulating substrate, so that the parasitic capacitance of a chip is effectively reduced, and the response frequency of the chip is improved.

Drawings

FIG. 1 is a schematic diagram of a monolithic integrated balanced photodetector chip structure according to the present invention;

FIG. 2 is a schematic structural diagram of an epitaxial material of a monolithically integrated balanced photodetector chip of the present invention;

FIG. 3 is a top view of a monolithically integrated balanced photodetector chip of the present invention;

FIG. 4 is a flow chart of a process for fabricating a monolithic integrated balanced photodetector chip according to the present invention;

FIG. 5 is a structural diagram of a CPW electrode fabricated by mesa fabrication, passivation and hole opening of the monolithic integrated balanced photodetector chip of the present invention;

the photoelectric detector comprises a photoelectric detector unit 1, a photoelectric detector unit 11, a first photosensitive area 12, a second photosensitive area 13, a P electrode 14, a signal output end 15, an N electrode 16, a contact ring electrode 2, a semi-insulating substrate 21, a first semiconductor contact layer 22, an intrinsic absorption layer 23, a semiconductor cap layer 24 and a second semiconductor contact layer.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The invention relates to a monolithic integration type balance photoelectric detector chip, which comprises two parallel photoelectric detector units 1 which are integrated in series as shown in figure 1, wherein the photoelectric detector units 1 are of a positive incidence light and mesa type double-heterogeneous PIN structure; the photoelectric detector unit adopts a semi-insulating substrate 2, and an epitaxial layer of a semiconductor material structure is deposited on the semi-insulating substrate 2;

a P electrode 13, an N electrode 15 and a signal output end 14 are arranged on the table top of the monolithic integrated balanced photoelectric detector chip, and the P electrode 13, the N electrode 15 and the signal output end 14 are led out from the same plane; the P electrode 13 is led out from a contact ring electrode 16 in a P + region through a metal thickened electrode and extends to the surface of the semi-insulating substrate through the mesa; the N electrode 15 is led out from the semiconductor contact layer of the N + region to the surface of the semi-insulating substrate through a metal thickened electrode; the signal output 14 is derived from the series connection of the two detector units.

As shown in fig. 2, a first semiconductor contact layer 21, an intrinsic absorber layer 22, a semiconductor cap layer 23 and a second semiconductor contact layer 24 are deposited on the epitaxial layer of the semi-insulating substrate from bottom to top.

The doping concentration of the first semiconductor contact layer 21 is greater than 5 x 10¹⁸cm^-3(ii) a The doping concentration of the semiconductor cap layer 23 is more than 1 × 10¹⁸cm^-3(ii) a The doping concentration of the second semiconductor contact layer 24 is greater than 5 x 10¹⁸cm^-3。

The semiconductor includes an InP semiconductor material, a GaAs semiconductor material, a Si semiconductor material, or a GaN semiconductor material; the material of the intrinsic absorber layer 22 includes: GaAs semiconductor material, Ge semiconductor material, or InGaAs semiconductor material.

The monolithic integrated balanced photoelectric detector chip is provided with two photosensitive areas, namely a first photosensitive area 11 and a second photosensitive area 12, and the diameters of the two photosensitive areas are adjusted through the working bandwidth of the integrated balanced photoelectric detector chip; because the two balanced photoelectric detector units are of a vertical normal incidence type, the central distance D of the two photosensitive areas in the monolithic integrated balanced photoelectric detector chip is adjusted according to the incident space light distance.

Taking a 10Gb/s monolithic integrated balanced photodetector chip as an example, the materials of the semi-insulating substrate, the first semiconductor contact layer and the semiconductor cap layer are InP, and the materials of the intrinsic absorption layer and the second semiconductor contact layer are InGaAs.

As shown in fig. 3, the table-board structure is a cuboid structure, the length L of the cuboid structure is 0.45mm to 0.55mm, the width W of the cuboid is 0.30mm to 0.40mm, and the height H of the cuboid is 0.120mm to 0.170 mm; optimally, the length of the cuboid structure is 0.50mm, the width of the cuboid structure is 0.35mm, and the height of the cuboid structure is 0.150 mm.

The two photoelectric detector units are provided with photosensitive areas, and the diameters phi of the photosensitive areas are as follows: 0.065 mm-0.075 mm, the distance D of the photosensitive film in the two photoelectric detector units is as follows: 0.20 mm-0.30 mm; optimally, the diameter of the photosensitive area is 0.070mm, and the distance D between the photosensitive pieces in the two photoelectric detector units is as follows: 0.25 mm.

Depositing an N-type InP layer on the semi-insulating InP substrate by MOCVD method, wherein the thickness of the N-type InP layer is 1 μm, and the doping concentration is more than 1 × 10¹⁸cm^-3For N-type contacts; continuously depositing a non-doped InGaAs structure layer with the thickness of 3 mu m on the InP N-type contact layer to serve as an absorption layer; depositing a P-type InP cap layer with the thickness of 1 μm on the absorption layer, wherein the doping concentration is more than 1 × 10¹⁸cm^-3(ii) a Continuously growing a P-type InGaAs layer with thickness of 0.5 μm on the P-type InP layer and with doping concentration greater than 5 × 10¹⁸cm^-3The main function is P-type contact.

A method for manufacturing a monolithic integrated balanced photodetector chip, as shown in fig. 4, the method comprising the steps of:

s1: on the semi-insulating substrate 2, sequentially depositing a first semiconductor contact layer 21, an intrinsic absorber layer 22, a semiconductor cap layer 23 and a second semiconductor contact layer 24 by Metal Organic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy (MBE);

s2: defining a P-type mesa region by adopting a photoetching process, and etching the mesa to the first semiconductor contact layer 21 in an ICP (inductively coupled plasma) dry method or RIE (reactive ion etching) dry method; or the mesa is etched to the first semiconductor contact layer 21 in a wet manner; or the mesa is etched to the first semiconductor contact layer 21 by combining a dry method and a wet method;

s3: defining an N-type mesa region by adopting a photoetching process, and etching the mesa to the semi-insulating substrate 2 in an ICP (inductively coupled plasma) dry method or RIE (reactive ion etching) dry method; or the mesa is etched to the semi-insulating substrate 2 in a wet method; or the mesa is etched to the semi-insulating substrate 2 by adopting a mode of combining a dry method and a wet method;

s4: passivating the appearance of each region to form a surface passivation film;

s5: SiO on mesa by photolithography₂Defining a photosensitive surface pattern on the mask, and etching a photosensitive area by HF;

s6: manufacturing a P electrode 13 and an N electrode 15 by adopting a stripping method with glue;

s7: the metal layer of the electrode is processed by adopting a rapid annealing method, so that good ohmic contact between the P electrode 13 and the N electrode 15 is ensured;

s8: thinning and polishing the epitaxial wafer to 100-200 μm by adopting a chemical mechanical polishing mode;

s9: and carrying out scribing and cleavage on the wafer to finish the chip manufacturing.

The Fe-doped semi-insulating InP material is selected as an epitaxial substrate material and used for preparing a mesa chip, so that series resistance and stray capacitance of the two photoelectric detectors can be reduced.

The etching of the P-type mesa region includes:

s21: cleaning the wafer with boiling stripping liquid, and washing the wafer clean and removing surface moisture by using deionized water;

s22: etching the deposited material to a certain depth by adopting an ICP dry method;

s23: carrying out P mesa etching on the epitaxial layer by using wet etching liquid, wherein the P mesa etching needs to etch the first semiconductor contact layer;

s24: soaking the wafer in corrosive liquid for a set time, washing with deionized water, boiling stripping liquid and removing photoresist;

s25: after cleaning the wafer, a layer of SiO is grown again₂A mask for carrying out passivation protection on the etched table top;

the method for etching the N-type mesa region is the same as the method for etching the P-type mesa region.

The corrosive liquid is HBr and Br₂、H₂Etching the mixed solution of O in water bath at normal temperature.

As shown in fig. 5, electrode hole fabrication: defining the pattern of the electrode hole on the surface of the silicon nitride antireflection film by using a photoetching method, corroding the redundant film layer by using hydrofluoric acid, etching an P, N-type contact hole, and removing the photoresist by using a stripping solution.

The formation mode of the passivation film comprises the steps of depositing a SiNx, SiO2 or SiNxOy dielectric film by adopting plasma enhanced chemical vapor deposition PECVD, or coating benzocyclobutene BCB or polyimide PI.

The P electrode and the N electrode are CPW electrodes, and the manufacturing method of the CPW electrodes comprises the following steps:

step 1: manufacturing a metal contact layer of gold-germanium-nickel/gold (Ti/Pt/Au or CrAu) by using a photoetching stripping method, wherein the thickness of the metal layer is about 300 nm; the metal layer is used for N-type ohmic contact;

step 2: after the metal contact layer is manufactured, the metal layer of the electrode is processed by adopting a rapid annealing method, so that good ohmic contact between the P-type metal layer and the N-type metal layer is ensured;

and step 3: coating a layer of benzocyclobutene (BCB) on the surface of the wafer in a spin coating mode, wherein the thickness of the BCB is about 4 mu m, and the step is completely covered;

and 4, step 4: firstly, baking for 20 minutes at the low temperature of 90 ℃ to pre-cure BCB, and then, completely curing the BCB at the high temperature of 280 ℃ in an annealing furnace;

and 5: and etching a pattern by using a photoetching method to expose the position of the metal layer to be thickened, continuously adopting a photoetching stripping process to define an evaporation area of the CPW coplanar electrode on the BCB, and manufacturing a CPW extension electrode on the surface of the BCB by adopting an electroplating method to be in contact with the metal layer in the P, N area.

The electroplating mode can ensure that the CPW gold layer uniformly climbs to the surface of the BCB from the P, N electrode contact layer below the BCB along the opening of the BCB, and the problem of height difference of the P, N table top can be well solved.

The top InGaAs ohmic contact layer is subjected to Zn doping, so that the p-type doping concentration of the top layer is improved, and the ohmic contact series resistance is reduced; the mesa planarization process is performed by adopting polyimide or BCB material, so that parasitic capacitance caused by non-coplanarity of electrode climbing and electrode is reduced.

The monolithic integrated balanced photoelectric detector chip can change the appearance structure of a tube core by changing the P electrode layout, the N electrode layout, the diameter of a photosensitive area, the space size and the like of the chip; similar other metal film layers (such as Ti/Au, Ti/Al/Pt/Au) can be adopted to replace CrAu and Ti/Pt/Au to be used as the metal film layers.

When the electrode is manufactured, other chemical materials such as polyimide can replace BCB materials to carry out a mesa planarization process; manufacturing an electrode by adopting a wet etching mode to replace a metal stripping process; when the electrode is electroplated, other metal film process modes such as multiple times of evaporation or sputtering and the like can be adopted to replace the electroplating process to thicken the metal layer.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.