阅读说明：本技术 高频电平转换器 (High frequency level shifter ) 是由 梁超 殷鹏 于 2019-11-27 设计创作，主要内容包括：本发明公开了一种高频电平转换器,所述高频电平转换器包括第一PMOS管、第二PMOS管以及高压输入端,所述高压输入端连接所述第一PMOS管的源极和所述第二PMOS管的源极,所述高频电平转换器还包括第三开关和第四开关；所述第三开关设置在所述第一PMOS管所在的通路中,所述第四开关设置在所述第二PMOS管所在的通路中。本发明提供的高频电平转换器,通过在静态电流通路中加入开关,可以阻断静态电流通路,消除静态电流,从而降低高频电平转换器的功耗。(The invention discloses a high-frequency level shifter, which comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube and a high-voltage input end, wherein the high-voltage input end is connected with a source electrode of the first PMOS tube and a source electrode of the second PMOS tube, and the high-frequency level shifter also comprises a third switch and a fourth switch; the third switch is arranged in a passage where the first PMOS tube is located, and the fourth switch is arranged in a passage where the second PMOS tube is located. According to the high-frequency level shifter provided by the invention, the switch is added in the static current path, so that the static current path can be blocked, the static current is eliminated, and the power consumption of the high-frequency level shifter is reduced.)

1. A high-frequency level shifter comprises a first PMOS (P-channel metal oxide semiconductor) transistor, a second PMOS transistor and a high-voltage input end, wherein the high-voltage input end is connected with a source electrode of the first PMOS transistor and a source electrode of the second PMOS transistor;

the third switch is arranged in a passage where the first PMOS tube is located, and the fourth switch is arranged in a passage where the second PMOS tube is located.

2. The high frequency level shifter of claim 1, wherein the third switch is disposed in a source path of the first PMOS transistor or a drain path of the first PMOS transistor.

3. The high frequency level shifter of claim 1, wherein the fourth switch is disposed in a source path of the second PMOS transistor or a drain path of the second PMOS transistor.

4. The high-frequency level shifter according to any one of claims 1 to 3, further comprising a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first switch, a second switch, a first input terminal, a second input terminal, a first output terminal, a second output terminal, and a ground terminal;

the first input end is connected with the grid electrode of the second PMOS tube and the drain electrode of the third NMOS tube, and the second input end is connected with the grid electrode of the first PMOS tube and the drain electrode of the fourth NMOS tube;

the first output end is connected with the drain electrode of the first PMOS tube, one end of the first switch, the source electrode of the third NMOS tube, the grid electrode of the second NMOS tube and the drain electrode of the first NMOS tube, and the second output end is connected with the drain electrode of the second PMOS tube, one end of the second switch, the source electrode of the fourth NMOS tube, the grid electrode of the first NMOS tube and the drain electrode of the second NMOS tube;

the high-voltage input end is further connected with the other end of the first switch, the other end of the second switch, a grid electrode of the third NMOS tube and a grid electrode of the fourth NMOS tube, and the grounding end is connected with a source electrode of the first NMOS tube and a source electrode of the second NMOS tube.

5. The high frequency level shifter according to claim 4, wherein the first switch and the second switch are NMOS transistors, one end of the first switch and one end of the second switch are source electrodes of the NMOS transistors, the other end of the first switch and the other end of the second switch are drain electrodes of the NMOS transistors, and the control end of the first switch and the control end of the second switch are gate electrodes of the NMOS transistors.

6. The high frequency level shifter according to claim 5, wherein a control terminal of the first switch is connected to the first input terminal, and a control terminal of the second switch is connected to the second input terminal.

7. The high frequency level shifter of claim 4, further comprising a first resistor through which the substrate of the first PMOS transistor is connected to the high voltage input terminal and a second resistor through which the substrate of the second PMOS transistor is connected to the high voltage input terminal.

8. The high frequency level shifter according to claim 4, further comprising a third resistor and a fourth resistor, wherein the other end of the first switch and the substrate of the first PMOS transistor are connected to the high voltage input terminal through the third resistor, and the other end of the second switch and the substrate of the second PMOS transistor are connected to the high voltage input terminal through the fourth resistor.

9. The high frequency level shifter of claim 4, further comprising a first inverter and a second inverter;

the input end of the first phase inverter is suitable for receiving input signals, the output end of the first phase inverter is connected with the input end of the second phase inverter and serves as the second input end, and the output end of the second phase inverter serves as the first input end.

10. The high frequency level shifter according to claim 4, wherein the third switch and the fourth switch are PMOS transistors, one end of the third switch and one end of the fourth switch are drains of the PMOS transistors, the other end of the third switch and the other end of the fourth switch are sources of the PMOS transistors, and a control terminal of the third switch and a control terminal of the fourth switch are gates of the PMOS transistors.

Technical Field

The invention relates to the technical field of level conversion, in particular to a high-frequency level converter.

Background

The multi-voltage domain design is a common design means for reducing the power consumption of the chip. The voltage values of different voltage domains are different, so that when signals are transmitted between different voltage domains, a level shifter is needed to ensure the quality of signal transmission. A level shifter is a conversion circuit that converts a signal from one voltage domain to another, and as shown in fig. 1, a level shifter may convert a signal from a lower level VL to a higher level VH.

Fig. 2 is a widely used level shifter, when the first input terminal Vinp receives a high level signal and the second input terminal Vinn receives a low level signal, the NMOS transistor N22 and the PMOS transistor P21 are turned on, the NMOS transistor N21 and the PMOS transistor P22 are turned off, the first output terminal Voutp outputs a high level signal, and the second output terminal Voutn outputs a low level signal; on the contrary, when the first input terminal Vinp receives a low level signal and the second input terminal Vinn receives a high level signal, the NMOS transistor N22 and the PMOS transistor P21 are turned off, the NMOS transistor N21 and the PMOS transistor P22 are turned on, the first output terminal Voutp outputs a low level signal, and the second output terminal Voutn outputs a high level signal. When the first input end Vinp receives a high level signal and the second input end Vinn receives a low level signal, the PMOS transistor P21 needs to be turned on after the NMOS transistor N22 is turned on, and the PMOS transistor P22 needs to be turned off after the PMOS transistor P21 is turned on; when the first input terminal Vinp receives a low level signal and the second input terminal Vinn receives a high level signal, the PMOS transistor P22 needs to be turned on after the NMOS transistor N21 is turned on, and the PMOS transistor P21 needs to be turned off after the PMOS transistor P22 is turned on, so that the level shifter shown in fig. 2 cannot convert a high frequency signal.

Fig. 3 is a high frequency level shifter, when the first input terminal Vinp receives a high level signal and the second input terminal Vinn receives a low level signal, the NMOS transistor N32, the NMOS transistor N34, the PMOS transistor P31, and the NMOS transistor N35 are turned on, the NMOS transistor N31, the NMOS transistor N33, the PMOS transistor P32, and the NMOS transistor N36 are turned off, the first output terminal Voutp outputs a high level signal, and the second output terminal Voutn outputs a low level signal; on the contrary, when the first input terminal Vinp receives a low level signal and the second input terminal Vinn receives a high level signal, the NMOS transistor N32, the NMOS transistor N34, the PMOS transistor P31 and the NMOS transistor N35 are turned off, the NMOS transistor N31, the NMOS transistor N33, the PMOS transistor P32 and the NMOS transistor N36 are turned on, the first output terminal Voutp outputs a low level signal, and the second output terminal Voutn outputs a high level signal. When the first input end Vinp receives a high level signal and the second input end Vinn receives a low level signal, the NMOS transistor N34 is turned on, so that the NMOS transistor N31 can be turned off quickly, and meanwhile, the NMOS transistor N35 is turned on, so that the voltage output by the first output end Voutp can be raised quickly; when the first input terminal Vinp receives a low level signal and the second input terminal Vinn receives a high level signal, the NMOS transistor N33 is turned on, so that the NMOS transistor N32 can be turned off quickly, and at the same time, the NMOS transistor N36 is turned on, so that the voltage output by the second output terminal Voutn can be raised quickly, and thus the level shifter shown in fig. 3 can convert a high frequency signal.

However, the high frequency level shifter shown in fig. 3 has a static current path, and still consumes a large current even when the signal is not inverted, resulting in power loss. For example, when the first input terminal Vinp receives a high level signal and the second input terminal Vinn receives a low level signal, the gate voltage of the PMOS transistor P32 is the voltage received by the first input terminal Vinp, the source voltage of the PMOS transistor P32 is the voltage received by the high voltage input terminal HV, and since the voltage received by the first input terminal Vinp is the lower level VL shown in fig. 1 and the voltage received by the high voltage input terminal HV is the higher level VH shown in fig. 1, the voltage difference between the gate and the source of the PMOS transistor P32 is less than zero, and a static current flows along the direction shown by the dashed line 31; similarly, when the first input terminal Vinp receives a low signal and the second input terminal Vinn receives a high signal, a static current flows along the direction indicated by the dashed line 32.

Disclosure of Invention

The invention aims to solve the problem of power consumption loss caused by quiescent current of the conventional high-frequency level converter.

The invention is realized by the following technical scheme:

a high-frequency level shifter comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a high-voltage input end, a third switch and a fourth switch, wherein the high-voltage input end is connected with a source electrode of the first PMOS tube and a source electrode of the second PMOS tube;

the third switch is arranged in a passage where the first PMOS tube is located, and the fourth switch is arranged in a passage where the second PMOS tube is located.

Optionally, the third switch is disposed in a source path of the first PMOS transistor or a drain path of the first PMOS transistor.

Optionally, the fourth switch is disposed in a source path of the second PMOS transistor or a drain path of the second PMOS transistor.

Optionally, the high-frequency level shifter further includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first switch, a second switch, a first input terminal, a second input terminal, a first output terminal, a second output terminal, and a ground terminal;

the first input end is connected with the grid electrode of the second PMOS tube and the drain electrode of the third NMOS tube, and the second input end is connected with the grid electrode of the first PMOS tube and the drain electrode of the fourth NMOS tube;

the first output end is connected with the drain electrode of the first PMOS tube, one end of the first switch, the source electrode of the third NMOS tube, the grid electrode of the second NMOS tube and the drain electrode of the first NMOS tube, and the second output end is connected with the drain electrode of the second PMOS tube, one end of the second switch, the source electrode of the fourth NMOS tube, the grid electrode of the first NMOS tube and the drain electrode of the second NMOS tube;

the high-voltage input end is further connected with the other end of the first switch, the other end of the second switch, a grid electrode of the third NMOS tube and a grid electrode of the fourth NMOS tube, and the grounding end is connected with a source electrode of the first NMOS tube and a source electrode of the second NMOS tube.

Optionally, the first switch and the second switch are NMOS transistors, one end of the first switch and one end of the second switch are source electrodes of the NMOS transistors, the other end of the first switch and the other end of the second switch are drain electrodes of the NMOS transistors, and a control end of the first switch and a control end of the second switch are gates of the NMOS transistors.

Optionally, the control end of the first switch is connected to the first input end, and the control end of the second switch is connected to the second input end.

Optionally, the high-frequency level shifter further includes a first resistor and a second resistor, the substrate of the first PMOS transistor is connected to the high-voltage input terminal through the first resistor, and the substrate of the second PMOS transistor is connected to the high-voltage input terminal through the second resistor.

Optionally, the high-frequency level shifter further includes a third resistor and a fourth resistor, the other end of the first switch and the substrate of the first PMOS transistor are connected to the high-voltage input terminal through the third resistor, and the other end of the second switch and the substrate of the second PMOS transistor are connected to the high-voltage input terminal through the fourth resistor.

Optionally, the high frequency level shifter further includes a first inverter and a second inverter;

the input end of the first phase inverter is suitable for receiving input signals, the output end of the first phase inverter is connected with the input end of the second phase inverter and serves as the second input end, and the output end of the second phase inverter serves as the first input end.

Optionally, the third switch and the fourth switch are PMOS transistors, one end of the third switch and one end of the fourth switch are drain electrodes of the PMOS transistors, the other end of the third switch and the other end of the fourth switch are source electrodes of the PMOS transistors, and a control end of the third switch and a control end of the fourth switch are gates of the PMOS transistors.

Optionally, a control end of the third switch is connected to the second output end, and a control end of the fourth switch is connected to the first output end.

Optionally, the high-frequency level shifter further includes a third PMOS transistor, a fourth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor;

the control end of the third switch is connected with the grid electrode of the third PMOS tube, the drain electrode of the third PMOS tube and the drain electrode of the fifth NMOS tube, and the control end of the fourth switch is connected with the grid electrode of the fourth PMOS tube, the drain electrode of the fourth PMOS tube and the drain electrode of the seventh NMOS tube;

the source electrode of the third PMOS tube and the source electrode of the fourth PMOS tube are connected with the high-voltage input end;

the grid electrode of the fifth NMOS tube is connected with the first input end, the source electrode of the fifth NMOS tube is connected with the drain electrode of the sixth NMOS tube, and the grid electrode of the sixth NMOS tube is connected with the second output end;

the grid electrode of the seventh NMOS tube is connected with the second input end, the source electrode of the seventh NMOS tube is connected with the drain electrode of the eighth NMOS tube, and the grid electrode of the eighth NMOS tube is connected with the first output end;

and the source electrode of the sixth NMOS tube and the source electrode of the eighth NMOS tube are connected with the grounding terminal.

Optionally, the third switch and the fourth switch are NMOS transistors, one end of the third switch and one end of the fourth switch are source electrodes of the NMOS transistors, the other end of the third switch and the other end of the fourth switch are drain electrodes of the NMOS transistors, and a control end of the third switch and a control end of the fourth switch are gates of the NMOS transistors.

Optionally, a control end of the third switch is connected to the first output end, and a control end of the fourth switch is connected to the second output end.

Compared with the prior art, the invention has the following advantages and beneficial effects:

according to the high-frequency level shifter provided by the invention, the third switch is arranged in the path of the first PMOS tube connected with the high-voltage input end, the fourth switch is arranged in the path of the second PMOS tube connected with the high-voltage input end, and the third switch and the fourth switch can block the static current path, so that the static current is eliminated, and the power consumption of the high-frequency level shifter is reduced.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:

FIG. 1 is a timing diagram of different voltage domains;

FIG. 2 is a circuit diagram of a conventional level shifter;

FIG. 3 is a circuit diagram of another prior art level shifter;

FIG. 4 is a circuit diagram of a high frequency level shifter according to an embodiment of the present invention;

FIG. 5 is a circuit diagram of the high frequency level shifter of FIG. 4 receiving an input signal;

FIG. 6 is a circuit diagram of a high frequency level shifter in accordance with another embodiment of the present invention;

FIG. 7 is a circuit diagram of a high frequency level shifter in accordance with another embodiment of the present invention;

FIG. 8 is a circuit diagram of a high frequency level shifter in accordance with another embodiment of the present invention;

FIG. 9 is a circuit diagram of a high frequency level shifter in accordance with another embodiment of the present invention;

FIG. 10 is a circuit diagram of a high frequency level shifter in accordance with another embodiment of the present invention;

fig. 11 is a circuit diagram of a high frequency level shifter according to another embodiment of the invention.

Detailed Description

Embodiments of the present disclosure provide a high frequency level shifter, which can eliminate a quiescent current by providing a switch in a quiescent current path of an existing level shifter circuit structure, thereby reducing power consumption of the high frequency level shifter. In the embodiments of the present disclosure, the conventional level shift circuit structure is taken as an example of the circuit shown in fig. 3, but it should be noted that the solutions provided in the embodiments of the present disclosure are also applicable to a circuit structure similar to that shown in fig. 3, that is, the circuit structure also has a quiescent current path, and two PMOS transistors connected to the high voltage input terminal are located in the quiescent current path. Specifically, the high-frequency level shifter includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a first switch, a second switch, a third switch, a fourth switch, a first input terminal, a second input terminal, a first output terminal, a second output terminal, a high-voltage input terminal, and a ground terminal.

The first input end is connected with the grid electrode of the second PMOS tube and the drain electrode of the third NMOS tube, and the second input end is connected with the grid electrode of the first PMOS tube and the drain electrode of the fourth NMOS tube; the first output end is connected with the drain electrode of the first PMOS tube, one end of the first switch, the source electrode of the third NMOS tube, the grid electrode of the second NMOS tube and the drain electrode of the first NMOS tube, and the second output end is connected with the drain electrode of the second PMOS tube, one end of the second switch, the source electrode of the fourth NMOS tube, the grid electrode of the first NMOS tube and the drain electrode of the second NMOS tube; the high-voltage input end is connected with the other end of the first switch, the other end of the second switch, the source electrode of the first PMOS tube, the source electrode of the second PMOS tube, the grid electrode of the third NMOS tube and the grid electrode of the fourth NMOS tube, and the grounding end is connected with the source electrode of the first NMOS tube and the source electrode of the second NMOS tube; the third switch is arranged in a passage where the first PMOS tube is located, and the fourth switch is arranged in a passage where the second PMOS tube is located.

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not meant to limit the present invention.