阅读说明：本技术 异质结双极晶体管和半导体装置 (Heterojunction bipolar transistor and semiconductor device ) 是由 大部功 梅本康成 筒井孝幸 田中聪 于 2019-07-22 设计创作，主要内容包括：本发明提供了HBT,其不会导致芯片尺寸的增大而能够抑制基于雪崩倍增的破坏。第1子集电极层成为在异质结双极晶体管的集电极层中流动的集电极电流的流入路径。在集电极层与第1子集电极层之间配置有掺杂浓度比第1子集电极层的掺杂浓度低的集电极镇流电阻层。(The present invention provides an HBT capable of suppressing damage by avalanche multiplication without causing an increase in chip size. The 1 st sub-collector layer serves as an inflow path of a collector current flowing in the collector layer of the heterojunction bipolar transistor. A collector ballast resistance layer having a lower doping concentration than the 1 st sub-collector layer is disposed between the collector layer and the 1 st sub-collector layer.)

1. A heterojunction bipolar transistor having:

a collector layer, a base layer, and an emitter layer;

a 1 st sub-collector layer serving as an inflow path of a collector current flowing through the collector layer; and

and a collector ballast resistor layer disposed between the collector layer and the 1 st sub-collector layer and having a lower doping concentration than the 1 st sub-collector layer.

2. The heterojunction bipolar transistor of claim 1,

the heterojunction bipolar transistor has a 2 nd sub-collector layer, the 2 nd sub-collector layer being disposed between the collector ballast resistance layer and the collector layer, the 2 nd sub-collector layer having a higher doping concentration than both the collector layer and the collector ballast resistance layer.

3. The heterojunction bipolar transistor of claim 1 or 2,

the collector ballast resistor layer includes a semiconductor layer containing AlGaAs or GaAs as a main component.

4. The heterojunction bipolar transistor of claim 3,

the collector layer is formed of GaAs,

the collector ballast resistance layer includes a 1 st collector ballast resistance layer and a 2 nd collector ballast resistance layer, the 2 nd collector ballast resistance layer is disposed between the 1 st collector ballast resistance layer and the 1 st sub-collector layer,

the 2 nd collector ballast resistor layer is formed of AlGaAs,

the composition of the 1 st collector ballast resistor layer is changed from AlGaAs to GaAs from the 2 nd collector ballast resistor layer to the collector layer.

5. The heterojunction bipolar transistor of any of claims 1 to 4,

the heterojunction bipolar transistor further includes an emitter ballast resistance layer disposed on the opposite side of the base layer when viewed from the emitter layer, and the emitter ballast resistance layer includes a semiconductor layer containing AlGaAs as a main component.

6. The heterojunction bipolar transistor of any of claims 1 to 5,

the 1 st sub-collector layer, the collector layer, and the base layer are formed of a semiconductor containing GaAs as a main component, and the emitter layer is formed of a semiconductor containing InGaP as a main component.

7. A kind of semiconductor device is provided, in which,

the semiconductor device comprises a 1 st sub-collector layer, a collector ballast resistor layer having a lower doping concentration than the 1 st sub-collector layer, a 2 nd sub-collector layer having a higher doping concentration than the collector ballast resistor layer, a collector layer, a base layer, and an emitter layer, which are sequentially arranged on a substrate,

the 1 st sub-collector layer, the collector ballast resistance layer, the 2 nd sub-collector layer, the base layer, and the emitter layer of the 1 st region in the plane of the substrate constitute a 1 st heterojunction bipolar transistor,

a collector electrode of the 1 st heterojunction bipolar transistor is connected to the 1 st subcollector layer,

at least the 2 nd sub-collector layer, the base layer, and the emitter layer of the 2 nd region different from the 1 st region constitute a 2 nd heterojunction bipolar transistor,

the semiconductor device further includes interconnection wiring connecting the collector layer of the 2 nd heterojunction bipolar transistor and the emitter layer of the 1 st heterojunction bipolar transistor.

8. The semiconductor device according to claim 7,

a collector electrode of the 2 nd heterojunction bipolar transistor is connected to the 2 nd sub-collector layer of the 2 nd heterojunction bipolar transistor, and the interconnection wiring is connected to a collector electrode of the 2 nd heterojunction bipolar transistor.

9. The semiconductor device according to claim 7,

the 2 nd heterojunction bipolar transistor further includes the 1 st sub-collector layer and the collector ballast resistance layer of the 2 nd region, a collector electrode of the 2 nd heterojunction bipolar transistor is connected to the 1 st sub-collector layer of the 2 nd heterojunction bipolar transistor, and the interconnection wiring is connected to a collector electrode of the 2 nd heterojunction bipolar transistor.

10. The semiconductor device according to any one of claims 7 to 9,

the collector ballast resistor layer includes a semiconductor layer containing AlGaAs or GaAs as a main component.

11. The semiconductor device according to claim 10,

the collector layer is formed of GaAs,

the collector ballast resistance layer includes a 1 st collector ballast resistance layer and a 2 nd collector ballast resistance layer, the 2 nd collector ballast resistance layer is disposed between the 1 st collector ballast resistance layer and the 1 st sub-collector layer,

the 2 nd collector ballast resistor layer is formed of AlGaAs,

the composition of the 1 st collector ballast resistor layer is changed from AlGaAs to GaAs from the 2 nd collector ballast resistor layer to the collector layer.

12. The semiconductor device according to any one of claims 7 to 11,

the semiconductor device further includes an emitter ballast resistor layer disposed on the opposite side of the base layer as viewed from the emitter layer, and the emitter ballast resistor layer includes a semiconductor layer containing AlGaAs as a main component.

13. The semiconductor device according to any one of claims 7 to 12,

the 1 st sub-collector layer, the 2 nd sub-collector layer, the collector layer, and the base layer are formed of a semiconductor containing GaAs as a main component, and the emitter layer is formed of a semiconductor containing InGaP as a main component.

Technical Field

The invention relates to a heterojunction bipolar transistor and a semiconductor device.

Background

A mobile communication system used by a portable telephone terminal or the like is shifted from the fourth generation (4G) to the fifth generation (5G). In the fifth generation mobile communication system, a frequency band (band) having a higher frequency is also used as compared with the fourth generation mobile communication system. Since the power loss in the high-frequency circuit increases as the frequency increases, a demand for higher output is strong for a high-frequency power amplifier, which is one of main components of a mobile phone terminal for a fifth-generation mobile communication system.

As a transistor constituting the high-frequency power amplifier, a Heterojunction Bipolar Transistor (HBT) is generally used. As one method for achieving higher output of the high-frequency power amplifier, a method of performing a high-frequency operation by increasing the collector voltage of the HBT is considered. However, when the collector voltage is increased, the electric field intensity inside the semiconductor becomes strong in the collector layer, and the risk of the HBT being broken due to avalanche multiplication increases. In order to prevent the HBT from breaking, a protection circuit for preventing the HBT from breaking is provided so that the collector voltage does not become equal to or higher than a predetermined value (see patent document 1).

Prior art documents

Patent document

Patent document 1: japanese patent laid-open publication No. 2005-236259

The protection circuit disclosed in patent document 1 is configured by connecting a plurality of diodes in series. The protection circuit is connected between the emitter and collector of the HBT in the direction of forward bias. When a voltage equal to or higher than the on voltage of the diodes connected in multiple stages is applied between the collector and the emitter, the protection circuit is turned on, and the HBT is prevented from being broken.

In order to use a plurality of diodes connected in multiple stages as a protection circuit, it is necessary to secure a region for forming the plurality of diodes in addition to the HBT forming region on the substrate. The method of forming the protection circuit using the diode leads to an increase in chip size, and thus it is difficult to reduce chip cost.

Disclosure of Invention

The purpose of the present invention is to provide an HBT capable of suppressing breakdown due to avalanche multiplication without increasing the chip size. Another object of the present invention is to provide a semiconductor device including the HBT.

According to an aspect of the present invention, there is provided a heterojunction bipolar transistor having: a collector layer, a base layer, and an emitter layer; a 1 st sub-collector layer serving as an inflow path of a collector current flowing through the collector layer; and a collector ballast resistance layer disposed between the collector layer and the 1 st sub-collector layer, and having a lower doping concentration than the 1 st sub-collector layer.

According to another aspect of the present invention, there is provided a semiconductor device having a 1 st sub-electrode layer, a collector ballast resistance layer having a lower doping concentration than the 1 st sub-electrode layer, a 2 nd sub-electrode layer having a higher doping concentration than the collector ballast resistance layer, a collector layer, a base layer, and an emitter layer, which are sequentially arranged on a substrate, wherein the 1 st sub-electrode layer, the collector ballast resistance layer, the 2 nd sub-electrode layer, the collector layer, the base layer, and the emitter layer in a 1 st region in a plane of the substrate constitute a 1 st heterojunction bipolar transistor, wherein a collector electrode of the 1 st heterojunction bipolar transistor is connected to the 1 st sub-electrode layer, and at least the 2 nd sub-electrode layer, the collector layer, the emitter layer, and the emitter layer in a 2 nd region different from the 1 st region, The base layer and the emitter layer constitute a 2 nd heterojunction bipolar transistor, and the semiconductor device further includes interconnection wiring connecting the collector layer of the 2 nd heterojunction bipolar transistor and the emitter layer of the 1 st heterojunction bipolar transistor.

Effects of the invention

When the collector current increases, the collector ballast resistance layer acts in a direction to lower the collector voltage. As a result, a rapid increase in the collector current due to avalanche multiplication can be suppressed. As a result, breakdown of the HBT by avalanche multiplication can be suppressed.

Drawings

Fig. 1 is a block diagram of a high-frequency power amplifier circuit using the HBT of embodiment 1.

Fig. 2 is an equivalent circuit diagram of the output stage amplification circuit (fig. 1).

Fig. 3 is a sectional view of one HBT used in the high-frequency power amplifier circuit of embodiment 1.

Fig. 4A is an equivalent circuit diagram for explaining the operation of the HBT not provided with the collector ballast resistor, and fig. 4B is an equivalent circuit diagram for explaining the operation of avalanche multiplication with respect to one HBT of embodiment 1.

Fig. 5 is an equivalent circuit diagram of an output stage amplifier circuit (fig. 1) using the HBT of embodiment 2.

Figure 6 is a cross-sectional view of the HBT of embodiment 2.

Fig. 7A is an equivalent circuit diagram for explaining the operation of the HBT circuit provided with the base ballast resistor and the collector ballast resistor, and fig. 7B is an equivalent circuit diagram for explaining the operation of avalanche multiplication with respect to the HBT of embodiment 2.

Fig. 8 is a sectional view of the HBT of embodiment 3.

Fig. 9 is a sectional view of the HBT of embodiment 4.

Fig. 10 is a block diagram of a high-frequency power amplifying circuit of embodiment 5.

Fig. 11 is an equivalent circuit diagram of an output stage amplification circuit (fig. 10) included in the high-frequency power amplification circuit of embodiment 5.

Fig. 12 is a sectional view of a semiconductor device constituting one cascode circuit included in the high-frequency power amplifying circuit of embodiment 5.

Fig. 13 is an equivalent circuit diagram of an output stage amplification circuit (fig. 10) included in the high-frequency power amplification circuit of embodiment 6.

Fig. 14 is an equivalent circuit diagram of an output stage amplification circuit (fig. 10) included in the high-frequency power amplification circuit of embodiment 7.

Fig. 15 is a sectional view of a semiconductor device constituting one cascode circuit included in the high-frequency power amplifying circuit of embodiment 7.

Fig. 16 is an equivalent circuit diagram of an output stage amplification circuit (fig. 10) included in the high-frequency power amplification circuit of embodiment 8.

Fig. 17 is a sectional view of a semiconductor device constituting one cascode circuit included in the high-frequency power amplifying circuit of embodiment 9.

Fig. 18 is a sectional view of the semiconductor device of embodiment 9 at an intermediate stage of its manufacture.

Fig. 19 is a sectional view of the semiconductor device of embodiment 9 at an intermediate stage of its manufacture.

Fig. 20 is a sectional view of the semiconductor device of example 9 at an intermediate stage of its manufacture.

Fig. 21 is a sectional view of the semiconductor device according to the embodiment 9 at an intermediate stage of the manufacturing.

Fig. 22 is a sectional view of the semiconductor device of example 9 at an intermediate stage of its manufacture.

Fig. 23 is a sectional view of the semiconductor device of example 9 at an intermediate stage of its manufacture.

Fig. 24 is a sectional view at an intermediate stage in the manufacture of the semiconductor device according to embodiment 9.

Fig. 25 is a sectional view at an intermediate stage in the manufacture of the semiconductor device according to embodiment 9.

Fig. 26 is a sectional view at an intermediate stage in the manufacture of the semiconductor device according to embodiment 9.

Fig. 27 is a sectional view of the HBT of embodiment 10.

Fig. 28 is a sectional view of an HBT according to a modification of embodiment 10.

Fig. 29 is a sectional view of the semiconductor device of embodiment 11.

Fig. 30 is a cross-sectional view of a semiconductor device according to a modification of embodiment 11.

Fig. 31 is an equivalent circuit diagram of an output stage amplification circuit included in the high-frequency power amplification circuit of embodiment 12.

Fig. 32 is an equivalent circuit diagram of an output stage amplification circuit included in the high-frequency power amplification circuit of embodiment 13.

Detailed Description