阅读说明：本技术 存储器单元、存储器器件及其形成方法 (Memory cell, memory device and forming method thereof ) 是由 蒋国璋 孙宏彰 赖昇志 杨子庆 江昱维 于 2021-05-11 设计创作，主要内容包括：存储器单元包括位于半导体衬底上方的薄膜晶体管,该薄膜晶体管包括：接触字线的存储器膜；以及接触源极线和位线的氧化物半导体(OS)层,其中,存储器膜设置在OS层和字线之间,其中,源极线和位线均包括接触OS层的第一导电材料,以及其中第一导电材料具有小于4.6的功函数。存储器单元还包括将源极线和位线隔开的电介质材料。本发明的实施例还公开了存储器器件及其形成方法。(The memory cell includes a thin film transistor over a semiconductor substrate, the thin film transistor including: a memory film contacting the word line; and an Oxide Semiconductor (OS) layer contacting the source line and the bit line, wherein the memory film is disposed between the OS layer and the word line, wherein the source line and the bit line each include a first conductive material contacting the OS layer, and wherein the first conductive material has a work function of less than 4.6. The memory cell also includes a dielectric material separating the source line and the bit line. Embodiments of the invention also disclose memory devices and methods of forming the same.)

1. A memory cell, comprising:

a thin film transistor over a semiconductor substrate, the thin film transistor comprising:

a memory film in contact with the word line; and

an OS (oxide semiconductor) layer in contact with a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line, wherein the source line and the bit line each comprise a first conductive material in contact with the OS layer, and wherein the first conductive material has a work function of less than 4.6; and

a dielectric material separating the source line and the bit line.

2. The memory cell of claim 1, wherein the first conductive material comprises LaNiO, InSnO, InZnO, CdSnO, Al-doped ZnO, or F-SnO.

3. The memory cell of claim 1, the source line and the bit line each comprising a second conductive material on an opposite side of the first conductive material from the oxide semiconductor layer, wherein the second conductive material is different from the first conductive material.

4. The memory cell of claim 3, the second conductive material comprising TiN, W, Ti, MoTi, CuMgAl, Ru, Al, Ta, TaN, CuMn, or CuAlZn.

5. The memory cell of claim 1, wherein the OS layer comprises:

a first poly region at an interface between the OS layer and the source line; and

a second poly region located at an interface between the OS layer and the bit line.

6. The memory cell of claim 5, wherein the first polycrystalline region comprises a metal oxide, and wherein a metal element of the first polycrystalline region is the same as a metal element of the first conductive material.

7. The memory cell of claim 5, wherein a thickness of the first poly region is in a range of 1nm to 10 nm.

8. The memory cell of claim 1, wherein the first conductive material extends continuously from the oxide semiconductor layer to a second oxide semiconductor layer, the second oxide semiconductor layer being on an opposite side of the first conductive material from the oxide semiconductor layer.

9. A memory device, comprising:

a semiconductor substrate;

a first memory cell over the semiconductor substrate, the first memory cell comprising a first thin film transistor, wherein the first thin film transistor comprises:

a gate electrode including a portion of the first word line;

a first portion of ferroelectric material located on sidewalls of the first word line; and

a first channel region on a sidewall of the ferroelectric material;

a source line, wherein a first portion of the source line provides a first source/drain electrode of the first thin film transistor, wherein the source line comprises a copper alloy, and wherein the copper alloy comprises a first metal different from copper;

a bit line, wherein a first portion of the bit line provides a second source/drain electrode of the first thin film transistor, and wherein the bit line comprises the copper alloy; and

a second memory cell located above the first memory cell.

10. A method of forming a memory device, comprising:

patterning a first trench extending through the first conductive line;

depositing a memory film along sidewalls and bottom surfaces of the first trench;

depositing an OS (oxide semiconductor) layer over the memory film, the OS layer extending along the sidewalls and the bottom surface of the first trench;

depositing a first dielectric material over the OS layer that contacts the OS layer;

patterning a second trench extending through the first dielectric material;

depositing a first conductive material in the second trench; and

annealing the first conductive material and the OS layer to form a polycrystalline region at an interface between the OS layer and the first conductive material.

Technical Field

Embodiments of the invention relate to memory cells, memory devices, and methods of forming the same.

Background

Semiconductor memory is used in integrated circuits for electronic applications including, by way of example, radios, televisions, cell phones, and personal computing devices. Semiconductor memories include two main categories. One is a volatile memory; the other is a non-volatile memory. Volatile memory includes Random Access Memory (RAM), which can be further divided into two subcategories: static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM). Both SRAM and DRAM are volatile because they lose their stored information when not powered.

On the other hand, nonvolatile memory may hold data stored thereon. One type of non-volatile semiconductor memory is ferroelectric random access memory (FeRAM or FRAM). Advantages of FeRAM include its fast write/read speed and small size.

Disclosure of Invention

According to an aspect of an embodiment of the present invention, there is provided a memory cell including: and the thin film transistor is positioned above the semiconductor substrate. The thin film transistor includes: a memory film in contact with the word line; and an OS (oxide semiconductor) layer in contact with the source line and the bit line, wherein the memory film is disposed between the OS layer and the word line, wherein the source line and the bit line each include a first conductive material contacting the OS layer, and wherein the first conductive material has a work function of less than 4.6. The memory cell further includes: a dielectric material separating the source lines and the bit lines.

According to another aspect of an embodiment of the present invention, there is provided a memory device including: a semiconductor substrate; the first memory cell is located above the semiconductor substrate and comprises a first thin film transistor. Wherein the first thin film transistor includes: a gate electrode including a portion of the first word line; a first portion of ferroelectric material located on sidewalls of the first word line; and a first channel region on a sidewall of the ferroelectric material. The memory device further includes: a source line, wherein a first portion of the source line provides a first source/drain electrode of the first thin film transistor, wherein the source line comprises a copper alloy, and wherein the copper alloy comprises a first metal different from copper; a bit line, wherein a first portion of the bit line provides a second source/drain electrode of the first thin film transistor, and wherein the bit line comprises a copper alloy; and a second memory cell located above the first memory cell.

According to yet another aspect of embodiments of the present invention, there is provided a method of forming a memory device, including: patterning a first trench extending through the first conductive line; depositing a memory film along sidewalls and bottom surfaces of the first trench; depositing an OS (oxide semiconductor) layer over the memory film, the OS layer extending along sidewalls and a bottom surface of the first trench; depositing a first dielectric material over the OS layer that contacts the OS layer; patterning a second trench extending through the first dielectric material; depositing a first conductive material in the second trench; and annealing the first conductive material and the OS layer to form a polycrystalline region at an interface between the OS layer and the first conductive material.

Drawings

Various aspects of the invention are better understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1A, 1B, and 1C illustrate perspective, circuit, and top views of a memory array according to some embodiments.

Fig. 2, 3A, 3B, 4, 5, 6, 7, 8, 9, 10, 11, 12A, 12B, 13, 14, 15, 16, 17A, 17B, 18A, 18B, 19A, 19B, 20, 21, 22, 23A, 23B, 23C, 24A, 24B, 25A, 25B, 26A, 26B, 27A, 27B, 28, 29A, 29B, 30A, 30B, 30C, and 30D illustrate various views of fabricating a memory array according to some embodiments.

Fig. 27C illustrates characteristics of a device, according to some embodiments.

31A, 31B, 31C illustrate various views of a memory array, according to some embodiments.

Fig. 32A, 32B, 32C, 33A, 33B, 33C, 34A, 34B, 34C, 35A, 35B, and 35C illustrate a memory array according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, this is merely an example and is not intended to limit the present invention. Also, in the following description, the formation of a first feature over or on a second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which an additional feature is interposed between the first and second features, such that the first and second features are not in direct contact. Also, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, for ease of description, spatially relative positional terms such as "below …," "below …," "below," "above …," "above," and the like may be used herein to describe one element or component's relationship to another (or other) element or component as illustrated in the figures. It will be understood that these spatially relative positional terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Various embodiments provide a 3D memory array having a plurality of vertically stacked memory cells. Each memory cell includes a Thin Film Transistor (TFT) having a word line region serving as a gate electrode, a bit line region serving as a first source/drain electrode, and a source line region serving as a second source/drain electrode. Each TFT also includes an insulating storage film (e.g., as a gate dielectric) and an Oxide Semiconductor (OS) channel region.

1A, 1B, and 1C illustrate examples of memory arrays according to some embodiments. FIG. 1A illustrates an example of a portion of a memory array 200 in a three-dimensional view; FIG. 1B shows a circuit diagram of memory array 200; FIG. 1C illustrates a top view of the memory array 200 according to some embodiments. The memory array 200 includes a plurality of memory cells 202 that may be arranged in a grid of rows and columns. Memory cells 202 may further be vertically stacked to provide a three-dimensional memory array, thereby increasing device density. The memory array 200 may be disposed in a back end of line (BEOL) of a semiconductor die. For example, the memory array may be disposed in an interconnect layer of a semiconductor die, such as above one or more active devices (e.g., transistors) formed on a semiconductor substrate. In some embodiments, the memory array may be disposed in a top metal layer of an interconnect layer, such as above all other interconnect layers in a semiconductor die. In other embodiments, the memory array may be disposed in an intermediate metal layer of the interconnect layer, and the semiconductor die may include, for example, additional interconnect layers above and below the memory array.

In some embodiments, memory array 200 is a flash memory array, such as a NOR flash memory array or the like. Each memory cell 202 may include a Thin Film Transistor (TFT)204 having the insulated memory film 90 as a gate dielectric. In some embodiments, the gate of each TFT204 is electrically coupled to a respective word line, the first source/drain region of each TFT204 is electrically coupled to a respective bit line, and the second source/drain region of each TFT204 is electrically coupled to a respective source line that electrically couples the second source/drain region to ground. Memory cells 202 in the same horizontal row of memory array 200 may share a common word line, while memory cells 202 in the same vertical column of memory array 200 may share a common source line and a common bit line.

The memory array 200 includes a plurality of vertically stacked conductive lines 72 (e.g., word lines), with the dielectric layer 52 disposed between adjacent ones of the conductive lines 72. The wires 72 extend in a direction parallel to the major surface of the underlying substrate (not explicitly shown in fig. 1A and 1B). The wires 72 may have a stepped configuration such that the lower wire 72 is longer than the higher wire 72 and the lower wire 72 extends laterally beyond the end of the higher wire 72. For example, in the multiple stacked layers of wires 72 shown in fig. 1A, the highest wire 72 is the shortest wire, and the lowest wire 72 is the longest wire. The respective lengths of the wires 72 may increase in a direction toward the underlying substrate. In this manner, a portion of each conductive line 72 may be accessible from above the memory array 200, and a conductive contact may be disposed to the exposed portion of each conductive line 72.

Memory array 200 also includes a plurality of conductive lines 106 (e.g., bit lines) and conductive lines 108 (e.g., source lines). Wires 106 and 108 may each extend in a direction perpendicular to wire 72. Dielectric material 98 is disposed between and isolates adjacent conductive lines 106 and 108.

The pair of conductive lines 106 and 108 and the intersecting conductive line 72 define the boundaries of each memory cell 202, and the dielectric material 102 is disposed between and isolates adjacent pairs of conductive lines 106 and 108. In some embodiments, the conductive line 108 is electrically coupled to ground. Although fig. 1A shows a particular arrangement of the wires 106 relative to the wires 108, it should be understood that in other embodiments, the arrangement of the wires 106 and 108 may be moved.

In some embodiments, conductive lines 106 and 108 may be formed of a material that reduces contact resistance in memory cell 202. For example, in some embodiments, the conductive lines 106 and 108 may include a low work function material (e.g., less than 4.6). As part of forming conductive lines 106 and 108, an annealing process may be performed to form a polycrystalline, metal-containing region in the channel region at the boundary between OS layer 92 and conductive lines 106, 108. Accordingly, the polycrystalline regions in contact with conductive lines 106 and 108 may be low resistivity regions regardless of the phase (e.g., crystalline or amorphous) of the remaining portion of OS layer 92, thereby reducing contact resistance in TFT 204. In some embodiments, wires 106 and 108 may comprise a copper-based alloy having a low resistivity, with a reduced tendency to oxidize (e.g., less susceptible to oxidation than pure copper). In embodiments where the conductive lines 106 and 108 comprise a copper-based alloy having a low resistivity, the current drive in the TFT204 may be further improved.

In some embodiments, conductive lines 106 and 108, which are at least partially in contact with OS layer 92, may be a low work function material capable of causing a surface metallization of OS layer 92 to reduce contact resistance at the interface between OS layer 92 and conductive line 106/108. In some embodiments, the wires 106 and 108 may include an alloy at the interface with the OS layer 92, and the alloy may have a low resistivity, have a reduced tendency to oxidize (e.g., less prone to oxidation than pure copper). Various embodiments may realize advantages. For example, as part of forming conductive line 106/108, an annealing process may be performed to form a polycrystalline metal oxide region in OS layer 92 at the boundary between OS layer 92 and conductive line 106/108. The poly region may be formed by interaction between the low work function material and the OS layer 92 triggered by the annealing process. Accordingly, the polycrystalline region in contact with conductive line 106/108 may be a low resistivity region regardless of the phase (e.g., crystalline or amorphous) of the remaining portion of OS layer 92, thereby reducing contact resistance. In embodiments where wires 106 and 108 comprise a copper-based alloy having a low resistivity, current drive may be further improved.

As described above, the memory array 200 may also include an Oxide Semiconductor (OS) layer 92. The OS layer 92 may provide a channel region for the TFT204 of the memory cell 202. For example, when an appropriate voltage is applied through a respective conductive line 72 (e.g., above a respective threshold voltage (Vth) of a corresponding TFT 204), the region of OS layer 92 that intersects conductive line 72 may allow current to flow from conductive line 106 to conductive line 108 (e.g., in the direction indicated by arrow 206). The OS layer 92 may have a relatively low hydrogen concentration, such as measured by time-of-flight secondary ion mass spectrometry (ToF-SIMS) analysis, per cubic meterCm about 10²⁰To about 10²²Within a range of one atom. Therefore, the stability of the TFT204 can be improved compared to a TFT having a higher hydrogen concentration in the OS layer.

Memory film 90 is disposed between conductive line 72 and OS layer 92, and memory film 90 may provide a gate dielectric for TFT 204. In some embodiments, memory film 90 comprises a ferroelectric material such as hafnium oxide, hafnium zirconium oxide, hafnium silicon doped oxide, and the like. Thus, memory array 200 may also be referred to as a ferroelectric random access memory (FERAM) array. Alternatively, the memory film 90 may be comprised of two SiO_xSiN between layers (e.g., ONO structure)_xA layer, a different ferroelectric material, a different type of memory layer (e.g., capable of storing bits), etc.

In embodiments where memory film 90 comprises a ferroelectric material, memory film 90 may be polarized in one of two different directions, and the polarization direction may be changed by applying an appropriate voltage difference across memory film 90 and generating an appropriate electric field. The polarization may be relatively local (e.g., typically contained within each boundary of the memory cell 202), and a continuous region of the memory film 90 may extend across multiple memory cells 202. According to the polarization direction of a specific region of the memory film 90, the threshold voltage of the corresponding TFT204 changes, and a digital value (e.g., 0 or 1) can be stored. For example, when a region of the memory film 90 has a first electrical polarization direction, the corresponding TFT204 may have a relatively low threshold voltage, and when a region of the memory film 90 has a second electrical polarization direction, the corresponding TFT204 may have a relatively high threshold voltage. The difference between the two threshold voltages may be referred to as a threshold voltage drift. The larger threshold voltage shift makes it easier (e.g., less prone to errors) to read the digital value stored in the respective memory cell 202.

In such an embodiment, to perform a write operation on the memory cell 202, a write voltage is applied to the portion of the memory film 90 corresponding to the memory cell 202. For example, a write voltage may be applied by applying appropriate voltages to respective conductive lines 72 (e.g., word lines) and respective conductive lines 106/108 (e.g., bit/source lines). By applying a write voltage on a portion of the memory film 90, the polarization direction of a region of the memory film 90 can be changed. Accordingly, the corresponding threshold voltage of the respective TFT204 may also be switched from a low threshold voltage to a high threshold voltage and vice versa, and a digital value may be stored in the memory cell 202. Because conductive line 72 intersects conductive lines 106 and 108, a separate memory cell 202 may be selected for the write operation.

To perform a read operation on memory cell 202, a read voltage is applied to the corresponding conductive line 72 (e.g., the word line/gate electrode of TFT 204) and a current is applied to the corresponding conductive line 106 (e.g., the bit line). The read voltage may be between the low threshold voltage and the high threshold voltage of the TFT 204. The TFT204 of the memory cell 202 may be conductive or non-conductive depending on the polarization direction of the corresponding region of the FE material 90. Accordingly, conductive line 106 may or may not discharge through conductive line 108 (e.g., a source line coupled to ground), and a digital value stored in memory cell 202 may be determined. Because conductive line 72 intersects conductive lines 106 and 108, an individual memory cell 202 may be selected for a read operation.

FIG. 1A further illustrates a reference cross section of a memory array 200 used in subsequent figures. The cross section B-B' is along the longitudinal axis of the conductive line 72 and in a direction, for example, parallel to the current flow direction of the TFT 204. Section C-C 'is perpendicular to section B-B' and parallel to the longitudinal axis of wire 72. Section C-C' extends through the wire 106. Section D-D 'is parallel to section C-C' and extends through dielectric material 102. For clarity, the subsequent figures refer to these reference sections.

In fig. 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, and may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulator layer may be, for example, a Buried Oxide (BOX) layer, a silicon oxide layer, or the like. An insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates such as multilayer substrates or gradient substrates may also be used. In some embodiments, the semiconductor material of substrate 50 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium phosphide and/or gallium indium arsenide phosphide; or a combination thereof.

Fig. 2 further illustrates circuitry that may be formed over substrate 50. The circuit includes active devices (e.g., transistors) at the top surface of the substrate 50. The transistor may include a gate dielectric layer 202 over the top surface of the substrate and a gate electrode 204 over the gate dielectric layer 202. Source/drain regions 206 are located in the substrate 50 on opposite sides of the gate dielectric layer 202 and the gate electrode 204. Gate spacers 208 are formed along sidewalls of the gate dielectric layer 202 and separate the source/drain regions 206 from the gate electrode 204 by an appropriate lateral distance. In some embodiments, the transistor may be a planar Field Effect Transistor (FET), a fin field effect transistor (finFET), a nano field effect transistor (nanoFET), or the like.

A first ILD 210 surrounds and isolates the source/drain regions 206, the gate dielectric layer 202, and the gate electrode 204, and a second ILD 212 is located over the first ILD 210. A source/drain contact 214 extends through the second ILD 212 and the first ILD 210 and is electrically coupled to the source/drain region 206, and a gate contact 216 extends through the second ILD 212 and is electrically coupled to the gate electrode 204. An interconnect structure 220, including one or more stacked dielectric layers 224 and conductive features 222 formed in the one or more dielectric layers 224, is located over the second ILD 212, source/drain contacts 214 and gate contacts 216. Although fig. 2 illustrates two stacked dielectric layers 224, it should be understood that the interconnect structure 220 may include any number of dielectric layers 224 having conductive features 222 disposed therein. The interconnect structure 220 may be electrically connected to the gate contact 216 and the source/drain contact 214 to form a functional circuit. In some embodiments, the functional circuitry formed by interconnect structure 220 may include logic circuitry, memory circuitry, sense amplifiers, controllers, input/output circuitry, image sensor circuitry, the like, or combinations thereof. Although fig. 2 discusses transistors formed on substrate 50, other active devices (e.g., diodes, etc.) and/or passive devices (e.g., capacitors, resistors, etc.) may also be formed as part of the functional circuitry.

In fig. 3A and 3B, a multi-layer stack 58 is formed over the structure of fig. 2. For simplicity and clarity, the substrate 50, transistors, ILD, and interconnect structure 120 may be omitted from subsequent figures. Although the multi-layer stack 58 is shown contacting the dielectric layer 224 of the interconnect structure 220, any number of intervening layers may be disposed between the substrate 50 and the multi-layer stack 58. For example, the multi-layer stack 58 may be located over the interconnect structure 220, and one or more additional interconnect layers including conductive features in insulating layers (e.g., low-k dielectric layers) may be disposed between the substrate 50 and the multi-layer stack 58. In some embodiments, the conductive features may be patterned to provide power, ground, and/or signal lines for active devices on the substrate 50 and/or the memory array 200 (see fig. 1A and 1B).

Multilayer stack 58 includes alternating layers of conductive lines 72A-D (collectively conductive layers 54) and dielectric layers 52A-C (collectively dielectric layers 52). The conductive layer 54 may be patterned in a subsequent step to define conductive lines 72 (e.g., word lines). Conductive layer 54 may comprise a conductive material such as copper, titanium nitride, tantalum nitride, tungsten, ruthenium, aluminum, combinations thereof, and the like, and dielectric layer 52 may comprise an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, and the like. Conductive layer 54 and dielectric layer 52 may each be formed using techniques such as Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), plasma enhanced CVD (pecvd), and the like. Although fig. 3A and 3B illustrate a particular number of conductive layers 54 and dielectric layers 52, other embodiments may include a different number of conductive layers 54 and dielectric layers 52.

Fig. 4-12B are views of intermediate stages in the fabrication of a staircase structure of memory array 200, according to some embodiments. Fig. 4 to 11 and 12B are shown along the reference section B-B' shown in fig. 1A. Fig. 12A is shown in a three-dimensional view.

In fig. 4, a photoresist 56 is formed over the multi-layer stack 58. As described above, the multi-layer stack 58 may include alternating layers of conductive layers 54 (labeled 54A, 54B, 54C, and 54D) and dielectric layers 52 (labeled 52A, 52B, and 52C). The photoresist 56 may be formed by using a spin coating technique.

In fig. 5, photoresist 56 is patterned to expose multilayer stack 58 in region 60 while masking the remaining portions of multilayer stack 58. For example, the topmost layer of multi-layer stack 58 (e.g., conductive layer 54D) may be exposed in region 60. The photoresist 56 may be patterned using acceptable photolithography techniques.

In fig. 6, the exposed portions of multilayer stack 58 in region 60 are etched using photoresist 56 as a mask. The etching may be any acceptable etching process such as by wet or dry etching, Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), and the like, or combinations thereof. The etching may be anisotropic. The etch may remove portions of conductive layer 54D and dielectric layer 52C in region 60 and define opening 61. Because conductive layer 54D and dielectric layer 52C have different material compositions, the etchant used to remove the exposed portions of these layers may be different. In some embodiments, dielectric layer 52C functions as an etch stop layer when etching conductive layer 54D, and conductive layer 54C functions as an etch stop layer when etching dielectric layer 52C. Accordingly, portions of conductive layer 54E and conductive layer 54D may be selectively removed without removing the remaining layers of multilayer stack 58, and opening 61 may extend to a desired depth. Alternatively, a timed etch process may be used to stop the etching of openings 61 after openings 61 reach a desired depth. In the resulting structure, conductive layer 54C is exposed in region 60.

In fig. 7, photoresist 56 is adjusted to expose additional portions of multilayer stack 58. The photoresist may be adjusted using acceptable photolithography techniques. As a result of the adjustment, the width of the photoresist 56 is reduced and portions of the multi-layer stack 58 in the regions 60 and 62 may be exposed. For example, a top surface of conductive layer 54C may be exposed in region 60, and a top surface of conductive layer 54D may be exposed in region 62.

In fig. 8, portions of conductive layer 54D, dielectric layer 52C, conductive layer 54C, and dielectric layer 52B in regions 60 and 62 are removed by an acceptable etch process using photoresist 56 as a mask. The etching may be any acceptable etching process such as by wet or dry etching, Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), and the like, or combinations thereof. The etching may be anisotropic. The etching may extend the opening 61 further into the multilayer stack 58. Since conductive layers 54D/54C and dielectric layers 52C/52B have different material compositions, the etchant used to remove the exposed portions of these layers may be different. In some embodiments, dielectric layer 52C functions as an etch stop layer when conductive layer 54D is etched; in etching dielectric layer 52C, conductive layer 54C serves as an etch stop layer; dielectric layer 52B acts as an etch stop layer when conductive layer 54C is etched; and conductive layer 54B acts as an etch stop layer when dielectric layer 52B is etched. Accordingly, portions of conductive layer 54D/54C and dielectric layer 52C/52B may be selectively removed without removing the remaining layers of multi-layer stack 58, and opening 61 may extend to a desired depth. In addition, the unetched portions of conductive layer 54 and dielectric layer 52 act as a mask for the underlying layers during the etching process, and thus, the previous pattern of conductive layer 54D and dielectric layer 52C (see fig. 7) may be transferred to the underlying conductive layer 54C and dielectric layer 52B. In the resulting structure, conductive layer 54B is exposed in region 60 and conductive layer 54C is exposed in region 62.

In fig. 9, photoresist 56 is adjusted to expose additional portions of multilayer stack 58. The photoresist may be adjusted using acceptable photolithography techniques. As a result of the adjustment, the width of the photoresist 56 is reduced and portions of the multi-layer stack 58 in the regions 60, 62, and 64 may be exposed. For example, the top surface of conductive layer 54B may be exposed in region 60; the top surface of conductive layer 54B may be exposed in region 60. The top surface of conductive layer 54C may be exposed in region 62. The top surface of conductive layer 54D may be exposed in region 64.

In fig. 10, portions of conductive layers 54D, 54C, and 54B in regions 60, 62, and 64 are removed by an acceptable etch process using photoresist 56 as a mask. The etching may be any acceptable etching process, such as by wet or dry etching, Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), and the like, or combinations thereof. The etching may be anisotropic. The etching may extend the opening 61 further into the multilayer stack 58. In some embodiments, dielectric layer 52C functions as an etch stop layer when conductive layer 54D is etched; dielectric layer 52B acts as an etch stop layer when conductive layer 54C is etched; and dielectric layer 52A serves as an etch stop for etching conductive layer 54B. Accordingly, portions of conductive layers 54D, 54C, and 54B may be selectively removed without removing the remaining layers of multilayer stack 58, and opening 61 may extend to a desired depth. Further, each dielectric layer 52 acts as a mask for the underlying layers during the etching process, and thus, the previous pattern of dielectric layer 52C/52B (see fig. 9) may be transferred to the underlying conductive layer 54C/54B. In the resulting structure, dielectric layer 52A is exposed in region 60; dielectric layer 52B is exposed in region 62 and dielectric layer 52C is exposed in region 64.

In fig. 11, the photoresist 56 may be removed, for example, by an acceptable ashing or wet strip process. Thus, the stepped structure 68 is formed. The stepped structure includes a stack of alternating conductive layers 54 and dielectric layers 52. The lower conductive layer 54 is wider and extends laterally beyond the upper conductive layer 54, and the width of each conductive layer 54 increases in a direction toward the substrate 50. For example, conductive layer 54A may be longer than conductive layer 54B; conductive layer 54B may be longer than conductive layer 54C; and conductive layer 54C may be longer than conductive layer 54D. Thus, in a subsequent process step, a conductive contact may be provided to each conductive layer 54 from above the stair-step structure 68.

In fig. 12, an inter-metal dielectric (IMD)70 is deposited over the multi-layer stack 58. IMD70 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma enhanced CVD (pecvd), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), Undoped Silicate Glass (USG), and the like. Other insulating materials formed by any acceptable process may be used. IMD70 extends along the sidewalls of conductive layer 54 and the sidewalls of dielectric layer 52. Further, IMD70 may contact a top surface of each dielectric layer 52.

As further shown in fig. 12, a removal process is then applied to IMD70 to remove excess dielectric material over multi-layer stack 58. In some embodiments, a planarization process such as Chemical Mechanical Polishing (CMP), an etch back process, a combination thereof, or the like may be employed. The planarization process exposes multilayer stack 58 such that the top surfaces of multilayer stack 58 and IMD70 are flush after the planarization process is complete.

Fig. 13-17B are views of intermediate stages in the manufacture of memory array 200 according to some embodiments. In fig. 13-17B, a multi-layer stack 58 is formed and a trench is formed in the multi-layer stack 58, thereby defining a conductive line 72. Conductive lines 72 may correspond to word lines in memory array 200, and conductive lines 72 may further provide gate electrodes for the resulting TFTs of memory array 200. Fig. 17A is shown in a three-dimensional view. Fig. 13 to 16 and 17B are shown along the reference section C-C' shown in fig. 1A.

In fig. 13, a hard mask 80 and photoresist 82 are deposited over the multi-layer stack 58. The hard mask layer 80 may comprise, for example, silicon nitride, silicon oxynitride, etc., which may be deposited by CVD, PVD, ALD, PECVD, etc. For example, the photoresist 82 may be formed by using a spin coating technique.

In fig. 14, photoresist 82 is patterned to form trenches 86. The photoresist may be patterned using acceptable photolithography techniques. For example, the photoresist 82 is exposed to light to be patterned. After the exposure process, the photoresist 82 may be developed to remove either the exposed or unexposed portions of the photoresist, depending on whether a negative or positive resist is used, to define the pattern of the shaping trenches 86.

In fig. 15, the pattern of photoresist 82 is transferred to hard mask 84 using an acceptable etch process, such as by wet or dry etching, Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), or the like, or combinations thereof. The etching may be anisotropic. Thus, trenches 86 are formed that extend through the hard mask 84. For example, the photoresist 82 may be removed by an ashing process.

In fig. 16, the pattern of hard mask 84 is transferred to multilayer stack 58 using one or more acceptable etching processes, such as by wet or dry etching, Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), or the like, or combinations thereof. The etching process may be anisotropic. Accordingly, trenches 86 and conductive lines 72 (e.g., word lines) extending through multilayer stack 58 are formed from conductive layer 54. Adjacent wires 72 may be separated from each other by etching trenches 86 through conductive layer 54. Subsequently, in fig. 17A and 17B, the hard mask 84 may then be removed by an acceptable process such as a wet etching process, a dry etching process, a planarization process, a combination thereof, and the like. Due to the stepped shape of the multilayer stack 58 (see, e.g., fig. 12), the wires 72 may have different lengths that increase in a direction toward the substrate 50. For example, wire 72A may be longer than wire 72B; wire 72B may be longer than wire 72C; and wire 72C may be longer than wire 72D.

Fig. 18A-23C illustrate the formation and patterning of the channel region for the TFT204 in the trench 86 (see fig. 1A). Fig. 18A, 19A and 23A are shown in three-dimensional views. In fig. 18B, 19B, 20, 21, 22 and 23B, a sectional view along line C-C' of fig. 1A is provided. Fig. 23C shows a top view of the corresponding TFT structure.

In fig. 18A and 18B, a memory film 90 is conformally deposited in the trench 86. The memory film 90 may be of a material capable of storing bits, for example, a material capable of switching between two different polarization directions by applying an appropriate voltage difference across the memory film 90. For example, the polarization of the memory film 90 may change due to an electric field created by applying a voltage difference.

For example, the memory film 90 may be a high-k dielectric material, such as a hafnium (Hf) based dielectric material, or the like. In some embodiments, memory film 90 comprises a ferroelectric material, such as hafnium oxide, hafnium zirconium oxide, hafnium silicon-doped oxide, and the like. In other embodiments, the memory 90 may be a single SiO cell_xSiN between layers (e.g., ONO structure)_xA multilayer structure of layers. In other embodiments, memory film 90 may include different ferroelectric materials or different types of memory materials. The memory film 90 may be deposited by CVD, PVD, ALD, PECVD, etc. to follow the sides of the trench 86The walls and bottom surface extend. After deposition of the memory film 90, an annealing step (e.g., at a temperature range of about 300 ℃ to about 600 ℃) may be performed to achieve a desired crystalline phase, improve film quality, and reduce film-related defects/impurities for the memory film 90. In some embodiments, the annealing step may also be below 400 ℃ to meet the BEOL thermal budget and reduce defects in other components due to the high temperature annealing process.

In fig. 19A and 19B, an OS layer 92 is conformally deposited in the trench 86 over the memory film 90. The OS layer 92 comprises a material suitable for providing a channel region for a TFT (e.g., TFT204, see fig. 1A). In some embodiments, OS layer 92 includes an indium-containing material, such as In_xGa_yZn_zMO, wherein M may be Ti, Al, Ag, Si, Sn, etc. X, Y and Z can be any value between 0 and 1, respectively. In other embodiments, different semiconductor materials may be used for the OS layer 92. The OS layer 92 may be deposited by CVD, PVD, ALD, PECVD, CVD, or the like. The OS layer 92 may extend along the sidewalls and bottom surface of the trench 86 above the FE layer 90. After deposition of the OS layer 92, an annealing step (e.g., at a temperature range of about 300 ℃ to about 450 ℃) may be performed in an oxygen-related ambient to activate charge carriers of the OS layer 92.

In fig. 20, a dielectric material 98A is deposited on the sidewalls and bottom surface of trench 86 and over OS layer 92. Dielectric material 98A may comprise, for example, silicon oxide, silicon nitride, silicon oxynitride, etc., which may be deposited by CVD, PVD, ALD, PECVD, etc.

In fig. 21, the bottom of dielectric material 98A in trench 86 is removed, for example, using a combination of lithography and etching. The etching may be any acceptable etching process, such as by wet or dry etching, Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), and the like, or combinations thereof. The etching may be anisotropic.

Subsequently, as also shown in fig. 21, the dielectric material 98A may be used as an etch mask to etch through the bottom of the OS layer 92 in the trench 86. The etching may be any acceptable etching process, such as by wet or dry etching, Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), and the like, or combinations thereof. The etching may be anisotropic. Etching the OS layer 92 may expose portions of the memory film 90 on the bottom surface of the trench 86. Accordingly, the portions of OS layer 92 on opposing sidewalls of trench 86 may be separated from each other, which improves the isolation between memory cells 202 of memory array 200 (see fig. 1A).

In fig. 22, additional dielectric material 98B may be deposited to fill the remaining portion of trench 86. Dielectric material 98B may comprise, for example, silicon oxide, silicon nitride, silicon oxynitride, etc., which may be deposited by CVD, PVD, ALD, PECVD, etc. In some embodiments, dielectric material 98B may have the same material composition as dielectric material 98A and may be formed using the same process as dielectric material 98A. Alternatively, dielectric material 98B may have a different material composition than dielectric material 98A and/or be formed by a different process than dielectric material 98A.

In fig. 23A-23C, a removal process is then applied to dielectric material 98, OS layer 92, and memory film 90 to remove excess material over multilayer stack 58. In some embodiments, processes such as Chemical Mechanical Polishing (CMP), etch back processes, combinations thereof, and the like may be used. The planarization process exposes the multi-layer stack 58 such that the top surface of the multi-layer stack 58 is planar after the planarization process is complete. Fig. 23C shows a corresponding top view of the structure shown in fig. 23A.

Fig. 24A-29B illustrate intermediate steps in fabricating conductive lines 106 and 108 (e.g., source lines and bit lines) in memory array 200. The conductive lines 106 and 108 may further provide source/drain electrodes for the TFTs 204 in the memory array (see fig. 1A-1C). The conductive lines 106 and 108 may comprise a material having a relatively low work function that is capable of causing surface metallization of the OS layer 92 to reduce contact resistance in the TFT 204. Conductive lines 106 and 108 may extend in a direction perpendicular to conductive line 72 so that individual cells of memory array 200 may be selected for read and write operations. FIG. 24A, FIG. 25A, FIG. 26A and FIG. 27A show cross-sectional views along section C-C' of FIG. 1A; fig. 24B, 25B, 26B, 27B, 28 and 29B show respective top views; and FIG. 29A shows a cross-sectional view along section D-D' of FIG. 1A.

In fig. 24A and 24B, trench 100 is patterned through dielectric material 98 (including dielectric material 98A and dielectric material 98B). For example, patterning the trench 100 may be performed by a combination of photolithography and etching. The trench 100 may be disposed between opposing sidewalls of the OS layer 92 and expose a top surface of the memory film 90 through the OS layer 92.

In fig. 25A and 25B, a conductive material 150 is formed in the trench 100 on the sidewalls of the OS layer 92. The conductive material 150 may have a relatively low work function, such as a work function of less than about 4.6. For example, the conductive material 150 may include titanium, iridium, ruthenium, conductive oxides (e.g., ceramics such as LaNiO, InSnO, InZnO, CdSnO, aluminum-doped ZnO, F — SnO, etc.). It has been observed that when the conductive material 150 has a low work function (e.g., within the ranges described above), the conductive material 150 can cause metallization of the surface of the OS layer 92 to reduce the contact resistance at the interface between the OS layer 92 and the conductive material 150. It is further observed that by providing the conductive material 150 with a low work function (e.g., less than 4.6), the barrier height between the conductive material 150 and the OS layer 92 may be reduced and the electron tunneling speed may be increased. The conductive material 150 may be deposited by CVD, PVD, ALD, PECVD, etc.

After depositing the conductive material 150, an annealing process may be performed to cause metallization of the surface of the OS layer 92 at the interface 152 between the OS layer 92 and the conductive material 150. In some embodiments, the annealing process may be a temperature of at least about 300 ℃ sufficient to cause metallization of the surface of the OS layer 92. As a result of the annealing process, a polycrystalline region 92' may be formed at an interface 152 between the OS layer 92 and the conductive material 150. For example, the polycrystalline region 92 'may be formed by a reaction between the InOa component of the OS layer 92 and a metal component (hereinafter, denoted as M') of the conductive material 150. The reaction can be expressed according to equations (1) and (2), where a and b are each integers between 0 and 1, and Vo represents defects generated by the film (e.g., oxygen vacancies and/or deficiencies in the film).

InO_a+M’→M’O_b+InO_a-b+Vo (1)

Vo→Vo²⁺+2e^- (2)

As described above, the polycrystalline region may include a metal oxide, and a metal element of the metal oxide may be the same as a metal element of the conductive material 150. In some embodiments, the thickness of poly region 92 '(e.g., the depth to which poly region 92' extends into OS layer 92) may be in the range of about 1nm to about 10nm, or in the range of about 1nm to about 5 nm. It has been observed that by having a relatively thin poly region (e.g., within the ranges described above), electrons may more readily tunnel through the boundary between the conductive material 150 and the OS layer 92. In other embodiments, the polycrystalline regions may have different thicknesses. The remaining portions of the OS layer 92 (e.g., outside of the polycrystalline region 92') may remain at the same crystalline stage as before the anneal process. For example, the remaining portions of the OS layer 92 may remain amorphous.

As also shown in fig. 25A and 25B, a removal process is then applied to the conductive material 150 to remove excess material over the multi-layer stack 58. In some embodiments, a planarization process such as CMP, an etch-back process, a combination thereof, or the like may be used. The planarization process exposes the multi-layer stack 58 such that the top surfaces of the multi-layer stack 58, the memory film 90, the OS layer 92, and the conductive material 150 are flush after the planarization process is completed.

Fig. 26A to 27B show manufacturing steps in which the central portion of the conductive material is replaced with a different conductive material. Thus, the wires 106 and 108 (see fig. 28) may include two different materials (e.g., conductive material 150 and conductive material 156 as described below). The steps shown in fig. 26A-27B are optional and may be omitted in some embodiments. In such embodiments, the wires 106 and 108 may include only the conductive material 150 shown in fig. 31A-31C.

In fig. 26A and 26B, trenches 154 are patterned through conductive material 150. For example, patterning the trench 154 may be performed by a combination of photolithography and etching. The trench 100 may be disposed between opposing sidewalls of the conductive material 150, and the remaining portion of the conductive material 150 may be disposed between the trench 100 and the OS layer 92. Trenches 154 extend through conductive material 150 and OS layer 92 to expose underlying memory film 90.

In fig. 27A and 27B, a conductive material 156 is deposited to fill the trench 154. Conductive material 156 may be disposed and conductive material 156 contacts opposing portions of conductive material 150. In some embodiments, the conductive material 156 may have a relatively low work function, for example, a work function of less than about 5 eV. For example, the conductive material 156 may include TiN, W, Ti, MoTi, CuMgAl, Ru, Al, Ta, TaN, CuMn, CuAlZn, combinations thereof, and the like. The conductive material 156 may be deposited by CVD, PVD, ALD, PECVD, and the like. It has been observed that by providing the conductive material 156 with a low work function (e.g., within the ranges described above), the barrier height between the conductive material 156 and the conductive material 150/OS layer 92 may be reduced and the electron tunneling speed may be increased. After deposition, a planarization process such as CMP, an etch-back process, combinations thereof, and the like may be utilized. The planarization process exposes the multi-layer stack 58 such that the top surfaces of the multi-layer stack 58, the memory film 90, the OS layer 92, the conductive material 150, and the conductive material 156 are flush after the planarization process is completed.

Due to the formation of the low work function (e.g., less than about 4.6) conductive material 150 and the formation of the poly region 92' in the OS layer 92, electrons may tunnel directly from the conductive material 156, through the material 150, and across the channel region of the OS layer 92. For example, as a result of forming the conductive material according to various embodiments, OS layer 92 may include a low resistivity region (e.g., polycrystalline region 92') regardless of the phase of OS layer 92 (e.g., crystalline or amorphous). Therefore, the contact resistance can be reduced. This reduced resistivity and improved electron tunneling are illustrated by bandgap diagram 300 of fig. 27C, which shows the conduction bands (E) of conductive material 156, conductive material 150, and OS layer 92_C) Valence band (E)_V) Fermi level (E)_F) And vacuum level (E)_VAC). The valence and conduction bands are the bands closest to the fermi level and determine the conductivity of the material. In addition, the valence band is the highest range of electron energies, where electrons typically exist at absolute zero temperature, while the conduction band is the lowest range of empty electronic states. Further, conductive material 150 and/or conductive material 156 may be, for example, pure copper as compared to pure copperLess susceptible to undesired oxidation. Therefore, device performance degradation due to oxidation can be avoided.

In fig. 28, trench 158 is patterned by conductive material 150, conductive material 156, and OS layer 92. Patterning the trench 158 may be performed by a combination of photolithography and etching, for example. The trench 158 may be disposed between opposing sidewalls of the memory film 90. Thus, conductive lines 106 and 108 are defined by conductive material 150 and the remaining portion of conductive material 156. Each conductor 106 is separated from an adjacent conductor 108 by a dielectric material 98 and pairs of conductors 106/108 are separated by trenches 158. Discrete portions of OS layer 92 extend continuously from respective conductive lines 106 to respective conductive lines 108. Conductive line 106 may correspond to a bit line in the memory array and conductive line 108 may correspond to a source line in the memory array 200. In addition, conductor 106/108 may provide source/drain electrodes for TFTs 204 (see fig. 29A and 29B) in memory array 200.

In fig. 29A and 29B, dielectric material 102 is deposited in trench 158 and fills trench 158. Fig. 29B shows a cross-sectional view of line D-D' in fig. 29A. The dielectric layer 102 may comprise, for example, silicon oxide, silicon nitride, silicon oxynitride, etc., which may be deposited by CVD, PVD, ALD, PECVD, etc. A dielectric layer 102 may extend over the memory film 90 along the sidewalls and bottom surface of the trench 86. After deposition, a planarization process (e.g., CMP, etchback, etc.) may be performed to remove excess portions of the dielectric material 102. In the resulting structure, the top surfaces of multilayer stack 58, memory film 90, OS layer 92, dielectric material 102, and conductive lines 106/108 may be substantially flush (e.g., within process variations).

Such stacked TFTs 204 may be formed in the memory array 200. Each TFT204 includes a gate electrode (e.g., a portion of a respective conductive line 72), a gate dielectric (e.g., a portion of a respective memory film 90), a channel region (e.g., a portion of a respective OS layer 92), and source and drain electrodes (e.g., portions of respective conductive lines 106 and 108). The dielectric material 102 isolates adjacent TFTs 204 in the same column and on the same vertical measurement line. The TFTs 204 may be arranged in an array of vertically stacked rows and columns.

In fig. 30A, 30B, 30C, and 30D, a contact 110 is formed onto the wire 72, the wire 106, and the wire 108. FIG. 30A shows a perspective view of memory array 200; and figure 30B shows a top view of memory array 200; FIG. 30C shows a cross-sectional view of the device and underlying substrate taken along line 30C '-30C' of FIG. 30A; and FIG. 30D shows a cross-sectional view of the device along line B-B' of FIG. 1A. In some embodiments, the stepped-shaped wires 72 may provide a surface on each wire 72 to land the conductive contact 110 thereon. For example, forming contacts 110 may include patterning openings in IMD70 and dielectric layer 52 to expose portions of conductive layer 54 using a combination of photolithography and etching. A liner (not shown) such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the opening. The liner may comprise titanium, titanium nitride, tantalum nitride, and the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, may be performed to remove excess material from the surface of IMD 70. The remaining pad and conductive material form a contact 110 in the opening.

As also shown in the perspective view of fig. 30A, conductive contacts 112 and 114 may also be made to the wires 106 and 108, respectively. Conductive contacts 110, 112, and 114 may be electrically connected to conductive lines 116A, 116B, and 116C, respectively, conductive contacts 110, 112, and 114 connecting the memory array to underlying/overlying circuitry (e.g., control circuitry) and/or signals, power, and ground in the semiconductor die. For example, conductive vias 118 may extend through IMD70 to electrically connect leads 116C to the underlying circuitry of interconnect structure 220 and the active devices on substrate 50 as shown in fig. 30C. Other conductive vias may be formed through IMD70 to electrically connect leads 116A and 116B to underlying circuitry of interconnect structure 220. In alternative embodiments, routing and/or power lines to and from the memory array may be provided by interconnect structures formed above the memory array 200 in addition to or in place of the interconnect structures 220. Thus, the memory array 200 may be completed.

Fig. 31A, 31B, and 31C illustrate cross-sectional views of a memory array 200 according to an alternative embodiment. Fig. 31A shows a cross-sectional view along section C-C' of fig. 1A and 31B. Fig. 31B shows a corresponding top view, and fig. 31C shows a cross-sectional view along the section D-D' of fig. 1A and 31B. Memory array 200 may be substantially similar to a memory array, wherein like reference numerals refer to like elements formed by like processes. However, in the memory array 200, the conductive material 156 (see fig. 29B) and the steps shown in fig. 26A to 27B are omitted. Thus, the conductive lines 106 and 108 are formed of a low work function conductive material 150. The conductive material 150 may be similar to that described above, having a low work function (e.g., less than 4.6) to reduce the resistivity between the conductive line 106/108 and the OS layer 92. Further, for example, the polycrystalline region 92' may be formed in the OS layer 92 at the boundary with the conductive material 150 by an annealing process.

Fig. 32A-35C illustrate intermediate steps in forming conductive lines 106 and 108 in memory array 200, according to some alternative embodiments. Memory array 200 may be similar to memory array 200, wherein like reference numerals refer to like elements formed by like processes unless otherwise specified. In fig. 32A to 35C, a 3D view is shown with a diagram ending with "a"; the figure ending with "B" shows a top view, while the figure ending with "C" shows a corresponding cross-sectional view parallel to the line C-C' of fig. 1A.

In fig. 32A, 32B, and 32C, trench 100 is patterned through OS layer 92 and dielectric material 98 (including dielectric material 98A and dielectric material 98B). Fig. 32C shows a cross-sectional view of line C-C' in fig. 32B. For example, the trench 100 may be patterned by a combination of photolithography and etching. The trench 100 may be disposed between opposing sidewalls of the memory film 90, and the trench 100 may physically separate adjacent stacked memory cells in a memory array 200 (see fig. 1A). Further, in a top view (see fig. 32B), the grooves 100 may have a staggered configuration. Alternatively, the trenches 100 may be aligned in a manner similar to that shown above for the memory array 200.

In fig. 33A, 33B, and 33C, a dielectric material 102 is deposited in the trench 100 and fills the trench 100. FIG. 33C shows a cross-sectional view of line C-C' in FIG. 33B. The dielectric layer 102 may comprise, for example, silicon oxide, silicon nitride, silicon oxynitride, etc., which may be deposited by CVD, PVD, ALD, PECVD, etc. Dielectric layer 102 may extend along the sidewalls and bottom surface of trench 86 over OS layer 92. After deposition, a planarization process (e.g., CMP, etchback, etc.) may be performed to remove excess portions of the dielectric material 102. In the resulting structure, the top surfaces of multilayer stack 58, memory film 90, OS layer 92, and dielectric material 102 may be substantially flush (e.g., within process variations). In some embodiments, the materials of dielectric materials 98 and 102 may be selected such that they may be selectively etched with respect to each other. For example, in some embodiments, dielectric material 98 is an oxide and dielectric material 102 is a nitride. In some embodiments, dielectric material 98 is a nitride and dielectric material 102 is an oxide. Other materials are also possible.

In fig. 34A, 34B, and 34C, the trench 104 is patterned for the conductive lines 106 and 108. Fig. 34C shows a cross-sectional view of line C-C' in fig. 34B. For example, the trench 104 is patterned by patterning the dielectric material 98 (including the dielectric material 98A and the dielectric material 98C) using a combination of photolithography and etching.

For example, photoresist 118 may be deposited over multilayer stack 58, dielectric material 98, dielectric material 102, OS layer 92, and memory film 90. For example, the photoresist 118 may be formed by using a spin coating technique. The photoresist 82 is patterned to define openings 120. Each opening 120 may overlap a corresponding region of dielectric material 102, and each opening 120 may further partially expose two separate regions of dielectric material 98. For example, each opening 120 may expose a region of dielectric material 102; partially exposing a first region of dielectric material 98; and partially exposing a second region of dielectric material 98 separated from the first region of dielectric material 98 by a region of dielectric material 102. In this manner, each opening 120 may define a pattern of conductive lines 106, as well as adjacent conductive lines 108 separated by dielectric material 102. Acceptable photolithography techniques can be used to pattern the photoresist. For example, the photoresist 82 is exposed to light for patterning. After the exposure process, the photoresist 82 may be developed to remove exposed or unexposed portions of the photoresist, depending on whether a negative or positive resist is used, to define the pattern that forms the opening 120.

Subsequently, portions of the dielectric material 98 exposed by the openings 120 may be removed, for example, by etching. The etching may be any acceptable etching process, such as by wet or dry etching, Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), and the like, or combinations thereof. The etching may be anisotropic. The etching process may use an etchant that etches the dielectric material 98 without significantly etching the dielectric material 102. Thus, even if the dielectric material 102 is exposed through the opening 120, the dielectric material 102 is not significantly removed. The pattern of the trench 104 may correspond to the conductive lines 106 and 108 (see fig. 35A, 35B, and 35C). For example, a portion of the dielectric material 98 may remain between each pair of trenches 104, and the dielectric material 102 may be disposed between adjacent pairs of trenches 104. After patterning the trench 104, the photoresist 118 may be removed, for example, by ashing.

In fig. 35A, 35B, and 35C, the trench 104 is filled with a conductive material to form conductive lines 106 and 108. FIG. 35C shows a cross-sectional view of line C-C' in FIG. 35B. The wires 106 and 108 may each include an electrically conductive material, such as a copper-based alloy or a copper aluminum-based alloy with a highly oxidizing secondary metal (e.g., Zn, Si, Mg, Ca, Ni, Co, Mo, Ti, W). For example, in some embodiments, the wires 106 and 108 may include an alloy of Cu (or CuAl) and Zn, Si, Mg, Ca, Ni, Co, Mo, Ti, W, and the like. The percentage of the secondary metal in wires 106 and 108 may be in a range of about 0.1 at% to about 10 at%. It has been observed that by including the secondary metal in the above amounts, the wires 106 and 108 can maintain low resistivity (e.g., less than about 10m Ω per cm) even after one hour of annealing in a nitrogen (N2) environment at a temperature of about 300 ℃ to about 500 ℃. As such, the wires 106 and 108 may be stronger and able to sustain subsequent processes because the material of the wires 106 and 108 is less susceptible to oxidation or copper diffusion than pure metals. The copper-based alloy can further improve current drive in the TFT 204.

After depositing conductive lines 106 and 108, planarization (e.g., CMP, etchback, etc.) may be performed to remove excess portions of the conductive material to form conductive lines 106 and 108. In the resulting structure, the top surfaces of multilayer stack 58, memory film 90, OS layer 92, conductive lines 106, and conductive lines 108 may be substantially flush (e.g., within process variations). Conductive line 106 may correspond to a bit line in the memory array and conductive line 108 may correspond to a source line in the memory array 200. Although fig. 35C shows a cross-sectional view showing only wire 106, the cross-sectional view of wire 108 may be similar.

Thus, stacked TFTs 204 may be formed in the memory array 200. Each TFT204 includes a gate electrode (e.g., a portion of a respective conductive line 72), a gate dielectric (e.g., a portion of a respective memory film 90), a channel region (e.g., a portion of a respective OS layer 92), and source and drain electrodes (e.g., portions of respective conductive lines 106 and 108). The dielectric material 102 isolates adjacent TFTs 204 in the same column and on the same vertical measurement line. The TFTs 204 may be arranged in an array of vertically stacked rows and columns. Subsequent processes similar to those described above may be performed to form interconnections from conductive lines 72, 106, and 108 to the underlying circuitry of the device and to arrive at a similar structure as described above in fig. 30A-30D.

Various embodiments provide a 3D memory array with vertically stacked memory cells. The memory cells each include a TFT having a memory film, a gate dielectric material, and an oxide semiconductor channel region. The TFT includes source/drain electrodes, which are also source lines and bit lines in the memory array. In some embodiments, the source lines and bit lines in a memory array may be formed of a material that reduces contact resistance in the memory cells.

For example, in some embodiments, the source and bit lines may include low work function materials (e.g., less than 4.6). As part of forming the source and bit lines, an annealing process may be performed to form a polycrystalline, metal-containing region at the boundary between the channel region and the source/bit lines. Accordingly, the poly-region contacting the source/bit lines may be a low resistivity region regardless of the phase (e.g., crystalline or amorphous) of the remainder of the channel region, thereby reducing contact resistance in the TFT. In some embodiments, the source/bit lines may comprise a copper-based alloy having a low resistivity, with a reduced tendency to oxidize (e.g., less susceptible to oxidation than pure copper). In embodiments where the source and bit lines comprise a copper-based alloy having a low resistivity, the current drive may be further improved.

In some embodiments, the memory cell includes a thin film transistor located over a semiconductor substrate, the thin film transistor including: a memory film contacting the word line; and an Oxide Semiconductor (OS) layer contacting the source line and the bit line, wherein the memory film is disposed between the OS layer and the word line, wherein the source line and the bit line each include a first conductive material contacting the OS layer, and wherein the first conductive material has a work function of less than 4.6. The memory cell also includes a dielectric material separating the source line and the bit line. Optionally, in some embodiments, the first conductive material comprises LaNiO, InSnO, InZnO, CdSnO, Al-doped ZnO, or F-SnO, and in some embodiments, the source and bit lines each comprise a second conductive material on an opposite side of the first conductive material as the OS layer, wherein the second conductive material is different from the first conductive material. Optionally, in some embodiments, the second conductive material comprises TiN, W, Ti, MoTi, CuMgAl, Ru, Al, Ta, TaN, CuMn, or CuAlZn, and in some embodiments, the OS layer comprises: a first poly region located at an interface between the OS layer and the source line; and a second poly region located at an interface between the OS layer and the bit line. Optionally, in some embodiments, the first polycrystalline region comprises a metal oxide, and wherein the metal element of the first polycrystalline region is the same as the metal element of the first conductive material. Optionally, in some embodiments, a thickness of the first polycrystalline region is in a range of 1nm to 10 nm. Optionally, in some embodiments, the first conductive material extends continuously from the OS layer to a second OS layer, the second OS layer being located on an opposite side of the first conductive material as the OS layer.

In some embodiments, a device includes a semiconductor substrate; a first memory cell over the semiconductor substrate, the first memory cell comprising a first thin film transistor. The first thin film transistor includes: a gate electrode including a portion of the first word line; a first portion of ferroelectric material located on sidewalls of the first word line; and a first channel region on a sidewall of the ferroelectric material, a source line, wherein a first portion of the source line provides a first source/drain electrode for the first thin film transistor, wherein the source line comprises a copper alloy, and wherein the copper alloy comprises a first metal different from copper; a bit line, wherein a first portion of the bit line provides a second source/drain electrode for the first thin film transistor, and wherein the bit line comprises a copper alloy; and the second memory cell is located above the first memory cell. Alternatively, in some embodiments, the first metal is Zn, Si, Mg, Ca, Ni, Co, Mo, Ti, or W. Optionally, in some embodiments, the amount of the first metal in the copper alloy is in a range of 0.1 at% to 10 at%. Optionally, in some embodiments, the copper alloy further comprises aluminum. Optionally, in some embodiments, the resistivity of the copper alloy is less than 10m Ω per cm.

In some embodiments, the method comprises: patterning a first trench extending through the first conductive line; depositing a memory film along sidewalls and bottom surfaces of the first trench; and depositing a memory film along the sidewalls and bottom surface of the first trench; depositing an Oxide Semiconductor (OS) layer over the memory film, the OS layer extending along sidewalls and a bottom surface of the first trench; depositing a first dielectric material over the OS layer that contacts the OS layer; patterning a second trench extending through the first dielectric material; depositing a first conductive material in the second trench; the first conductive material and the OS layer are annealed to form a polycrystalline region at an interface between the OS layer and the first conductive material. Optionally, in some embodiments, the first conductive material comprises TiN, W, Ti, MoTi, CuMgAl, Ru, Al, Ta, TaN, CuMn, or CuAlZn. In some embodiments, annealing the first conductive material and the OS layer comprises annealing the first conductive material and the OS layer at a temperature of at least 300 ℃. Optionally, in some embodiments, annealing the first conductive material and the OS layer causes a reaction between an indium oxide component of the OS layer and a metal component of the first conductive material, such that the polycrystalline region comprises a metal oxide. Optionally, in some embodiments, the method further comprises: patterning a third trench through the first conductive material after annealing the first conductive material, wherein remaining portions of the first conductive material are located on opposing sidewalls of the third trench; and filling the third trench with a second conductive material different from the first conductive material. Optionally, in some embodiments, the second conductive material comprises TiN, W, Ti, MoTi, CuMgAl, Ru, Al, Ta, TaN, CuMn, CuAlZn. Optionally, in some embodiments, the method further comprises: patterning a fourth trench through the first conductive material; and filling the fourth trench with a second dielectric material.

The components of the various embodiments are discussed above so that those of ordinary skill in the art may better understand the various aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.