阅读说明：本技术 半导体器件及其形成方法 (Semiconductor device and method of forming the same ) 是由 杨柏峰 杨世海 贾汉中 王圣祯 林佑明 于 2021-04-30 设计创作，主要内容包括：公开了用于3D存储器阵列的布线布置及其形成方法。在实施例中,半导体器件包括：存储器阵列,包括接触第一字线和第二字线的栅极介电层；以及氧化物半导体(OS)层,接触源极线和位线,栅极介电层设置在OS层和第一字线以及第二字线的每个之间；互连结构,位于存储器阵列上方,第二字线和互连结构之间的距离小于第一字线和互连结构之间的距离；以及集成电路管芯,接合至与存储器阵列相对的互连结构,集成电路管芯通过电介质至电介质接合和金属至金属接合而接合至互连结构。本申请的实施例还涉及半导体器件及其形成方法。(Wiring arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes: a memory array including a gate dielectric layer contacting a first word line and a second word line; and an Oxide Semiconductor (OS) layer contacting the source line and the bit line, a gate dielectric layer disposed between the OS layer and each of the first word line and the second word line; an interconnect structure located over the memory array, a distance between the second word line and the interconnect structure being less than a distance between the first word line and the interconnect structure; and an integrated circuit die bonded to the interconnect structure opposite the memory array, the integrated circuit die bonded to the interconnect structure by dielectric-to-dielectric bonding and metal-to-metal bonding. Embodiments of the present application also relate to semiconductor devices and methods of forming the same.)

1. A semiconductor device, comprising:

a memory array, comprising:

a gate dielectric layer contacting the first word line and the second word line; and

an Oxide Semiconductor (OS) layer contacting a source line and a bit line, wherein the gate dielectric layer is disposed between the oxide semiconductor layer and each of the first and second word lines;

an interconnect structure over the memory array, wherein a distance between the second word line and the interconnect structure is less than a distance between the first word line and the interconnect structure; and

an integrated circuit die bonded to the interconnect structure opposite the memory array, wherein the integrated circuit die is bonded to the interconnect structure by dielectric-to-dielectric bonding and metal-to-metal bonding.

2. The semiconductor device of claim 1, wherein a length of the first word line is greater than a length of the second word line.

3. The semiconductor device of claim 1, wherein a front-side interconnect structure of the integrated circuit die is bonded to the interconnect structure.

4. The semiconductor device of claim 1, wherein a backside of the integrated circuit die is bonded to the interconnect structure.

5. The semiconductor device of claim 4, wherein the integrated circuit die comprises a substrate via extending through a semiconductor substrate, the substrate via electrically coupling a source/drain region of the integrated circuit die to the interconnect structure.

6. The semiconductor device of claim 1, wherein the interconnect structure includes a first contact electrically coupling the first wordline to the integrated circuit die, the first contact extending from the first wordline to the integrated circuit die.

7. The semiconductor device of claim 1, further comprising: a second integrated circuit die hybrid bonded to the interconnect structure adjacent to the integrated circuit die.

8. A semiconductor device, comprising:

a logic die comprising a semiconductor substrate;

an interconnect structure located over the logic die; and

a memory array located over the interconnect structure, the memory array comprising:

a first memory cell including a first portion of a gate dielectric layer contacting a first word line; and

a second memory cell comprising a second portion of the gate dielectric layer contacting a second word line, wherein the second memory cell is disposed farther from the interconnect structure than the first memory cell in a first direction perpendicular to a major surface of the semiconductor substrate, wherein the second word line has a length in a second direction perpendicular to the first direction that is greater than a length of the first word line in the second direction, and wherein the logic die comprises circuitry configured to perform read and write operations in the memory array.

9. The semiconductor device of claim 8, wherein the logic die is bonded to the interconnect structure by dielectric-to-dielectric bonding and metal-to-metal bonding.

10. A method of forming a semiconductor device, comprising:

forming a memory array, the forming the memory array comprising:

forming a multilayer stack over a substrate, the multilayer stack comprising alternating conductive and dielectric layers;

patterning a first trench extending through the multilayer stack;

depositing a gate dielectric layer along sidewalls and a bottom surface of the first trench; and

depositing an Oxide Semiconductor (OS) layer over the gate dielectric layer;

forming a first interconnect structure over the memory array; and

an integrated circuit device is bonded to the first interconnect structure using dielectric-to-dielectric bonding and metal-to-metal bonding.

Technical Field

Embodiments of the present application relate to semiconductor devices and methods of forming the same.

Background

As an example, semiconductor memory is used in integrated circuits for electronic applications including radios, televisions, cell phones, and personal computing devices. Semiconductor memories include two main categories. One type is volatile memory; the other type is nonvolatile memory. Volatile memory includes Random Access Memory (RAM), which can be further divided into two subcategories: static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM). Both SRAM and DRAM are volatile because they lose their stored information when not powered.

On the other hand, nonvolatile memories may store data on them. One type of non-volatile semiconductor memory is ferroelectric random access memory (FERAM or FRAM). Advantages of FeRAM include its fast write/read speed and small size.

Disclosure of Invention

Some embodiments of the present application provide a semiconductor device, including: a memory array, comprising: a gate dielectric layer contacting the first word line and the second word line; and an Oxide Semiconductor (OS) layer contacting the source line and the bit line, wherein the gate dielectric layer is disposed between the oxide semiconductor layer and each of the first word line and the second word line; an interconnect structure over the memory array, wherein a distance between the second word line and the interconnect structure is less than a distance between the first word line and the interconnect structure; and an integrated circuit die bonded to the interconnect structure opposite the memory array, wherein the integrated circuit die is bonded to the interconnect structure by dielectric-to-dielectric bonding and metal-to-metal bonding.

Other embodiments of the present application provide a semiconductor device, including: a logic die comprising a semiconductor substrate; an interconnect structure located over the logic die; and a memory array located over the interconnect structure, the memory array comprising: a first memory cell including a first portion of a gate dielectric layer contacting a first word line; and a second memory cell including a second portion of the gate dielectric layer contacting a second word line, wherein the second memory cell is disposed farther from the interconnect structure than the first memory cell in a first direction perpendicular to a major surface of the semiconductor substrate, wherein the second word line has a length in a second direction perpendicular to the first direction that is greater than a length of the first word line in the second direction, and wherein the logic die includes circuitry configured to perform read and write operations in the memory array.

Still further embodiments of the present application provide a method of forming a semiconductor device, comprising: forming a memory array, the forming the memory array comprising: forming a multilayer stack over a substrate, the multilayer stack comprising alternating conductive and dielectric layers; patterning a first trench extending through the multilayer stack; depositing a gate dielectric layer along sidewalls and a bottom surface of the first trench; and depositing an Oxide Semiconductor (OS) layer over the gate dielectric layer; forming a first interconnect structure over the memory array; and bonding an integrated circuit device to the first interconnect structure using a dielectric-to-dielectric bond and a metal-to-metal bond.

Drawings

Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1A and 1B illustrate perspective and circuit diagrams of a memory array according to some embodiments.

Fig. 2, 3, 4, 5, 6, 7A, 7B, 8A, 8B, 9, 10A, 10B, 11A, 11B, 12A, 12B, 13A, 13B, 14A, 14B, 15A, 15B, 16A, 16B, 17A, 17B, 18A, 18B, 19A, 19B, 19C, 20A, 20B, 20C, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30A, 30B, 30C, 30D, 31A, 31B, 31C, 32, 33, 34, 35, 36 and 37 illustrate variations in the fabrication of semiconductor devices including memory arrays according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Also, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another (or other) element or component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Various embodiments provide methods for bonding a semiconductor die to a 3D memory array and packages formed therefrom. The 3D memory array may include a plurality of vertically stacked memory cells. The semiconductor die may include a logic die, a peripheral die (e.g., an input/output die, etc.), combinations thereof, and the like. An interconnect structure may be formed over the 3D memory array, and a semiconductor die may be bonded to the interconnect structure. In some embodiments, the semiconductor die may include Through Substrate Vias (TSVs), and the backside of the semiconductor die (including the TSVs) may be bonded to the interconnect structure. In some embodiments, the front-side interconnect structure of the semiconductor die may be bonded to an interconnect structure formed over the 3D memory array. In some embodiments, the front or back sides of the logic die and the peripheral die may each be bonded to an interconnect structure formed over the 3D memory array. Bonding a semiconductor die to a 3D memory array through an interconnect structure formed over the 3D memory simplifies routing between the 3D memory array and the semiconductor die, shortens the length of contacts and wires used to route connections between the 3D memory array and the semiconductor die, reduces contact resistance, and improves device performance.

Fig. 1A and 1B illustrate examples of a memory array 200 according to some embodiments. Fig. 1A illustrates an example of a portion of a memory array 200 in a perspective view, and fig. 1B illustrates a circuit diagram of the memory array 200, according to some embodiments. The memory array 200 includes a plurality of memory cells 202, which may be arranged in a grid of rows and columns. Memory cells 202 may be further vertically stacked to provide a three-dimensional memory array, thereby increasing device density. The memory array 200 may be disposed in a back end of line (BEOL) of a semiconductor die. For example, the memory array 200 may be disposed in an interconnect layer of a semiconductor die, such as over one or more active devices (e.g., transistors, etc.) formed on a semiconductor substrate.

In some embodiments, the memory array 200 is a flash memory array, such as a NOR flash memory array or the like. Each of the memory cells 202 may include a transistor 204 having a memory film 90. The memory film 90 may serve as a gate dielectric. In some embodiments, the gate of each transistor 204 is electrically coupled to a corresponding word line (e.g., conductive line 72), the first source/drain region of each transistor 204 is electrically coupled to a corresponding bit line (e.g., conductive line 106), and the second source/drain region of each transistor 204 is electrically coupled to a corresponding source line (e.g., conductive line 108) that couples the second source/drain region to ground. Memory cells 202 in the same horizontal row of memory array 200 may share a common word line, while memory cells 202 in the same vertical column of memory array 200 may share a common source line and a common bit line.

The memory array 200 includes a plurality of vertically stacked conductive lines 72 (e.g., word lines) with a dielectric layer 52 disposed between adjacent conductive lines 72. The wires 72 extend in a direction parallel to the main surface of the underlying substrate (not separately shown in fig. 1A and 1B). The wires 72 may have a stepped configuration such that the lower wire 72 is longer than the upper wire 72 and extends laterally beyond the end points of the upper wire 72. For example, in fig. 1A, multiple stacked layers of wires 72 are shown, with the topmost wire 72 being the shortest and the bottommost wire 72 being the longest. The respective lengths of the wires 72 may increase in a direction toward the underlying substrate. In this manner, portions of each of the conductive lines 72 may be accessed from above the memory array 200, and conductive contacts to exposed portions of each of the conductive lines 72 may be made.

Memory array 200 also includes a plurality of conductive lines 106 (e.g., bit lines) and a plurality of conductive lines 108 (e.g., source lines). Wires 106 and 108 may each extend in a direction perpendicular to wire 72. Dielectric material 102 is disposed between and isolates adjacent conductive lines 106 and 108. The pairs of conductive lines 106 and 108 and the intersecting conductive line 72 define the boundaries of each memory cell 202, and a dielectric material 98 is disposed between and isolates adjacent pairs of conductive lines 106 and 108. In some embodiments, the wire 108 is electrically coupled to ground. Although fig. 1A shows a particular placement of the wires 106 relative to the wires 108, it should be understood that the placement of the wires 106 and 108 may be reversed.

Memory array 200 may also include an Oxide Semiconductor (OS) layer 92. OS layer 92 may provide a channel region for transistor 204 of memory cell 202. For example, when an appropriate voltage (e.g., higher than the respective threshold voltage (V) of the corresponding transistor 204) is applied through the corresponding conductor 72_th) The region of OS layer 92 that intersects conductive line 72 may allow current to flow from conductive line 106 to conductive line 108 (e.g., in the direction indicated by arrow 206).

Memory film 90 is disposed between conductive line 72 and OS layer 92, and memory film 90 may provide a gate dielectric for transistor 204. In some embodiments, memory film 90 comprises a Ferroelectric (FE) material such as hafnium oxide, hafnium zirconium oxide, silicon doped hafnium oxide, and the like. Thus, memory array 200 may also be referred to as a ferroelectric random access memory (FERAM) array. Alternatively, the memory film 90 may be a film including two SiO_xSiN between layers_xA multi-layer structure of layers (e.g., an ONO structure), different ferroelectric materials, different types of memory layers (e.g., capable of storing bits), etc.

The memory film 90 can be polarized in one of two different directions, and the polarization direction can be changed by applying an appropriate voltage difference across the memory film 90 and generating an appropriate electric field. The polarization may be relatively local (e.g., typically contained within each boundary of the memory cell 202), and a continuous region of the memory film 90 may extend across multiple memory cells 202. Depending on the polarization direction of a specific region of the memory film 90, the threshold voltage of the corresponding transistor 204 changes, and a digital value (e.g., 0 or 1) can be stored. For example, when a region of the memory film 90 has a first electrical polarization direction, the corresponding transistor 204 may have a relatively low threshold voltage, and when a region of the memory film 90 has a second electrical polarization direction, the corresponding transistor 204 may have a relatively high threshold voltage. The difference between the two threshold voltages may be referred to as a threshold voltage drift. The larger threshold voltage drift makes it easier (e.g., less prone to errors) to read the digital value stored in the corresponding memory cell 202.

To perform a write operation on the memory cell 202, a write voltage is applied across a portion of the memory film 90 corresponding to the memory cell 202. The write voltages may be applied, for example, by applying appropriate voltages to corresponding conductive lines 72 (e.g., corresponding word lines) and corresponding conductive lines 106 and 108 (e.g., corresponding bit lines and source lines). By applying a write voltage across a portion of the memory film 90, the polarization direction of a region of the memory film 90 can be changed. Thus, the corresponding threshold voltage of the corresponding transistor 204 may be switched from a low threshold voltage to a high threshold voltage, or vice versa, and a digital value may be stored in the memory cell 202. Because conductive line 72 intersects conductive line 106 and conductive line 108, individual memory cells 202 may be selected for write operations.

To perform a read operation on memory cell 202, a read voltage (e.g., a voltage between a low threshold voltage and a high threshold voltage) is applied to a corresponding conductive line 72 (e.g., a corresponding word line). Depending on the polarization direction of the corresponding region of memory film 90, transistor 204 of memory cell 202 may or may not be conductive. Accordingly, corresponding conductive line 106 may or may not discharge through corresponding conductive line 108 (e.g., a corresponding source line coupled to ground), and a digital value stored in memory cell 202 may be determined. Because conductive line 72 intersects conductive line 106 and conductive line 108, individual memory cells 202 may be selected for read operations.

Fig. 1A also shows a reference cross section of a memory array 200 used in subsequent figures. Cross section a-a' is along the longitudinal axis of wire 72 and in a direction, for example, parallel to the direction of current flow through OS layer 92 of transistor 204. Section B-B 'is perpendicular to section A-A' and the longitudinal axis of wire 72. Section B-B' extends through dielectric material 98 and dielectric material 102. Section C-C 'is parallel to section B-B' and extends through wire 106. For clarity, the figures that follow refer to these reference sections.

Fig. 2-7A, 8A, and 8B are cross-sectional views of intermediate stages in the manufacture of semiconductor device 300 and semiconductor device 400, which may then be bonded to memory array 200 to form a packaged semiconductor device. Fig. 7B is a perspective view of an intermediate stage in the manufacture of the semiconductor device 300. Fig. 9-37 are views of intermediate stages in the manufacture of memory array 200 and a semiconductor device including memory array 200, according to some embodiments. Fig. 9, 21 to 29, 30A, 31B, and 32 to 37 are shown along a reference section a-a' shown in fig. 1A. Fig. 10B, 11B, 12B, 13B, 14B, 15B, 16B, 17B, 18B, 19B, 20B, and 30B are shown along a reference section B-B' shown in fig. 1A. Fig. 19C, 20C, 30C and 31C are shown along a reference section C-C' shown in fig. 1A. Fig. 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, and 20A show top views. Fig. 30D shows a perspective view.

In fig. 2 to 8A, a semiconductor device 300 is formed, and in fig. 8B, a semiconductor device 400 is formed. Semiconductor device 300 and semiconductor device 400 may include logic dies (e.g., a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a system on a chip (SoC), an Application Processor (AP), a Field Programmable Gate Array (FPGA), a microcontroller, etc.), peripheral dies (e.g., an input/output die, etc.), memory dies (e.g., a Dynamic Random Access Memory (DRAM) die, a Static Random Access Memory (SRAM) die, etc.), power management dies (e.g., a Power Management Integrated Circuit (PMIC) die), Radio Frequency (RF) dies, sensor dies, micro-electro-mechanical systems (MEMS) dies, signal processing dies (e.g., a Digital Signal Processing (DSP) die), front-end dies (e.g., analog front-end (AFE) dies), etc., or combinations thereof. As will be discussed below, semiconductor device 300 and semiconductor device 400 may be bonded to memory array 200 and may be used to perform read/write operations, etc., on memory array 200.

In fig. 2, a substrate 350 is provided. The substrate 350 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with p-type or n-type dopants) or undoped. Substrate 350 may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a Buried Oxide (BOX) layer, a silicon oxide layer, or the like. An insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of substrate 350 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or a combination thereof.

In fig. 3, circuitry is formed over a substrate 350. The circuit includes transistors at the top surface of the substrate 350. The transistor may include a gate dielectric layer 302 over the top surface of the substrate 350 and a gate electrode 304 over the gate dielectric layer 302. Source/drain regions 306 are disposed in the substrate 350 on opposite sides of the gate dielectric layer 302 and the gate electrode 304. Gate spacers 308 are formed along sidewalls of the gate dielectric layer 302 that separate the source/drain regions 306 from the gate electrode 304 by an appropriate lateral distance. The transistors may include fin field effect transistors (finfets), nano-structured (e.g., nano-sheets, nano-wires, all-around gates, etc.) FETs (nano-FETs), planar FETs, etc., or combinations thereof, and may be formed by a gate-first process or a gate-last process.

A first ILD 310 surrounds and isolates the source/drain regions 306, the gate dielectric layer 302, and the gate electrode 304, and a second ILD 312 is positioned over the first ILD 310. A source/drain contact 314 extends through the second ILD 312 and the first ILD 310 and is electrically coupled to the source/drain region 306, and a gate contact 316 extends through the second ILD 312 and is electrically coupled to the gate electrode 304. An interconnect structure 320 (comprising one or more stacked dielectric layers 324 and conductive features 322 formed in the one or more dielectric layers 324) is located over the second ILD 312, the source/drain contacts 314 and the gate contacts 316. The interconnect structure 320 may be electrically coupled to the gate contact 316 and the source/drain contact 314 to form a functional circuit. In some embodiments, the functional circuitry formed by interconnect structure 320 may include logic circuitry, memory circuitry, sense amplifiers, controllers, input/output circuitry, image sensor circuitry, and the like, or combinations thereof. In some embodiments, the functional circuitry may include decoders, processors, multiplexers, controllers, sense amplifiers, etc., and may be used to provide read/write operations and otherwise control the memory array 200 which is then coupled to the interconnect structure 320. Although fig. 3 discusses transistors formed over substrate 350, other active devices (e.g., diodes, etc.) and/or passive devices (e.g., capacitors, resistors, etc.) may also be formed as part of the functional circuitry. The interconnect structure 320 may be formed over the front side of the substrate 350 and may therefore be referred to as a front side interconnect structure.

In fig. 4, the device of fig. 3 is flipped over and a carrier substrate 352 is bonded to the interconnect structure 320. The device may be flipped so that the backside of the substrate 350 is facing up. The backside of substrate 350 may refer to the opposite side from the front side of substrate 350 on which active devices are formed. The carrier substrate 352 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 352 may be a wafer such that multiple devices (such as the device shown in fig. 3) may be bonded to the carrier substrate 352 at the same time.

The carrier substrate 352 may be bonded to the interconnect structure 320 through a release layer 354. The release layer 354 may be formed of a polymer-based material that may be removed with the carrier substrate 352 from overlying structures to be formed in a subsequent step. In some embodiments, the release layer 354 is an epoxy-based thermal release material that loses its tackiness when heated, such as a light-to-heat conversion (LTHC) release coating. In other embodiments, the release layer 354 may be an Ultraviolet (UV) glue that loses its tackiness when exposed to UV light. The release layer 354 may be dispensed as a liquid and cured, may be a laminate film laminated onto the carrier substrate 352, or the like. The top surface of the release layer 354 may be flush and may have a high degree of planarity.

In fig. 5, a thinning process is applied to the backside of the substrate 350. The thinning process may include a planarization process (e.g., mechanical grinding, Chemical Mechanical Polishing (CMP), etc.), an etch-back process, combinations thereof, and the like. Substrate 350 may be thinned to shorten the length of subsequently formed Through Substrate Vias (TSVs).

In fig. 6, a trench 330 is formed in a substrate 350. The trench 330 may be patterned in the substrate 350 by a combination of lithography and etching. The etch may be any acceptable etch process such as a wet or dry etch, Reactive Ion Etch (RIE), Neutral Beam Etch (NBE), or the like, or combinations thereof. The etching may be anisotropic. The trenches 330 may extend through the substrate 350 to expose the surface of the source/drain regions 306.

In fig. 7A and 7B, a TSV332 is formed in the trench 330. TSV332 may include one or more layers such as a barrier layer, a diffusion layer, and a filler material. The TSV332 may be electrically coupled to the source/drain region 306. In some embodiments, silicide regions (not separately shown) may be formed in the trenches 330 adjacent to the source/drain regions 306, and the TSVs 332 may be coupled to the source/drain regions 306 through the silicide regions. The TSV332 may include tungsten (W), ruthenium (Ru), cobalt (Co), copper (Cu), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), nickel (Ni), combinations thereof, and the like. After depositing the material of TSV332, a planarization process such as CMP may be performed to remove excess material from the surface of substrate 350.

Fig. 7B illustrates a perspective view of the structure of fig. 7A in an embodiment in which the transistor includes a FinFET. The view shown in fig. 7B has been flipped vertically from that shown in fig. 7A for clarity and ease of illustration. As shown in fig. 7B, a fin 372 is formed to extend over the substrate 350. Although fin 372 and substrate 350 are shown as a single, continuous material, fin 372 and/or substrate 350 may comprise a single material or multiple materials. Shallow Trench Isolation (STI) regions 370 are disposed in the substrate 350, and fins 372 are over adjacent STI regions 370 and protrude from between adjacent STI regions 370. Fin 372 may refer to a portion extending between adjacent STI regions 370. TSV332 may replace portions of fin 372 to extend through substrate 350 between STI regions 370 to physically contact and electrically couple to source/drain regions 306.

In fig. 8A, carrier substrate lift-off is performed to separate (lift-off) the carrier substrate 352 from the interconnect structure 320, thereby forming the semiconductor device 300. According to some embodiments, peeling includes projecting light, such as laser or UV light, onto the release layer 354 such that the release layer 354 decomposes under the heat of the light and the carrier substrate 352 may be removed. The device of fig. 7A may also be flipped so that the front side of substrate 350 is facing up. In some embodiments, the semiconductor device 300 may be further subjected to a dicing process to form individual semiconductor dies. The cutting process may include sawing, laser ablation methods, etching processes, combinations thereof, and the like. In some embodiments, a dicing process may be performed prior to bonding the semiconductor device 300 to the memory array 200, thereby enabling a single semiconductor die to be bonded to the memory array 200. In some embodiments, the semiconductor device 300 and the memory array 200 may be cut after bonding the semiconductor device 300 to the memory array 200.

Fig. 8B illustrates an embodiment in which carrier substrate lift-off is performed to separate (lift-off) carrier substrate 352 from interconnect structure 320 after thinning substrate 350 (see, e.g., fig. 5) and before forming trenches 330 through substrate 350 (see, e.g., fig. 6), thereby forming semiconductor device 400. Peeling may include projecting light, such as laser or UV light, onto the release layer 354 such that the release layer 354 decomposes under the heat of the light and the carrier substrate 352 may be removed. The semiconductor device 400 may be cut before or after bonding the semiconductor device 400 to the memory array 200.

In fig. 9, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with p-type or n-type dopants) or undoped. Substrate 50 may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a Buried Oxide (BOX) layer, a silicon oxide layer, or the like. An insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of substrate 50 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or a combination thereof. In some embodiments, active devices (e.g., transistors, diodes, etc.) and/or passive devices (e.g., capacitors, resistors, etc.) may be formed on the top surface of the substrate 50. In some embodiments, the transistor may be a planar Field Effect Transistor (FET), a fin field effect transistor (FinFET), a nano field effect transistor (nano FET), or the like.

Further in fig. 9, a multilayer stack 58 is formed over the substrate 50. Although the multilayer stack 58 is shown contacting the substrate 50, any number of intermediate layers may be disposed between the substrate 50 and the multilayer stack 58. For example, one or more interconnect layers including conductive features in insulating layers (e.g., low-k dielectric layers) may be disposed between the substrate 50 and the multilayer stack 58. In some embodiments, the conductive features may be patterned to provide power, ground, and/or signal lines for active devices on the substrate 50 and/or the memory array 200 (see fig. 1A and 1B).

Multilayer stack 58 includes alternating layers of conductive layers 54A-54G (collectively referred to as conductive layers 54) and dielectric layers 52A-52G (collectively referred to as dielectric layers 52). The conductive layer 54 may be patterned in a subsequent step to define conductive lines 72 (e.g., word lines). Conductive layer 54 may include a conductive material such as copper, titanium nitride, tantalum nitride, tungsten, ruthenium, aluminum, cobalt, silver, gold, nickel, chromium, hafnium, platinum, combinations thereof, and the like. The dielectric layer 52 may comprise an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, and the like. Conductive layer 54 and dielectric layer 52 may each be formed using, for example, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), plasma enhanced CVD (pecvd), or the like. Although fig. 9 shows a particular number of conductive layers 54 and dielectric layers 52, other embodiments may include a different number of conductive layers 54 and dielectric layers 52.

In some embodiments, the substrate 50 may be a carrier substrate. In embodiments where the substrate 50 is a carrier substrate, a release layer (not separately shown) may be formed over the substrate 50 prior to forming the multilayer stack 58 over the substrate 50. The substrate 50 may be a glass carrier substrate, a ceramic carrier substrate, or the like. Substrate 50 may be a wafer such that multiple memory arrays 200 may be processed simultaneously on substrate 50. The release layer may be formed of a polymer-based material that may be subsequently removed from the overlying memory array 200 along with the substrate 50. In some embodiments, the release layer is an epoxy-based thermal release material that loses its tackiness when heated, such as a light-to-heat conversion (LTHC) release coating. In other embodiments, the release layer may be an Ultraviolet (UV) glue that loses its tackiness when exposed to UV light. The release layer may be dispensed as a liquid and cured, may be a laminated film laminated onto the substrate 50, or the like. The top surface of the release layer may be flush and may have a high degree of planarity.

In fig. 10A-12B, a trench 86 is formed in the multilayer stack 58, thereby defining the wire 72. Conductive lines 72 may correspond to word lines in memory array 200, and conductive lines 72 may provide gate electrodes for the resulting transistors 204 of memory array 200 (see fig. 1A and 1B). In fig. 10A to 12B, the figures ending with "a" show top views and the figures ending with "B" show cross-sectional views along the reference section B-B' of fig. 1A.

In fig. 10A and 10B, a hard mask 80 is deposited over multilayer stack 58. The hard mask 80 may comprise, for example, silicon nitride, silicon oxynitride, etc., which may be deposited by CVD, PVD, ALD, PECVD, etc. The hard mask 80 may be formed by using spin-on techniques and may be patterned using acceptable photolithographic techniques. A photoresist 82 is formed and patterned over the hard mask 80. Photoresist 82 may be patterned to form trenches 86 that expose portions of the top surface of hard mask 80.

In fig. 11A and 11B, the pattern of photoresist 82 is transferred to hard mask 80 using an acceptable etch process such as wet or dry etching, RIE, NBE, or the like, or combinations thereof. The etching may be anisotropic. Thus, trench 86 is transferred to hard mask 80. Further in fig. 11A and 11B, the pattern of hard mask 80 is transferred to multilayer stack 58 using one or more acceptable etching processes such as wet or dry etching, RIE, NBE, or the like, or combinations thereof. The etching process may be anisotropic. Thus, the grooves 86 extend through the multilayer stack 58. Conductive lines 72A-72G (e.g., word lines, collectively referred to as conductive lines 72) are formed from conductive layers 54A-54D by etching trenches 86. More specifically, adjacent wires 72 may be separated from each other by a trench 86 etched through conductive layer 54. In fig. 12A and 12B, the hard mask 80 may be removed by an acceptable process such as a wet etching process, a dry etching process, a planarization process, a combination thereof, and the like.

Fig. 13A-16B illustrate the formation and patterning of a channel region for transistor 204 (see fig. 1A and 1B) in trench 86. In fig. 13A and 13B, memory film 90, OS layer 92, and first dielectric layer 98A are deposited in trench 86. Memory film 90 may be conformally deposited in trenches 86 along the sidewalls of conductive lines 72 and dielectric layer 52 and along the top surfaces of conductive lines 72G and substrate 50. The memory film 90 may be deposited by CVD, PVD, ALD, PECVD, etc.

The memory film 90 may provide a gate dielectric for the transistors 204 formed in the memory array 200. Memory film 90 may comprise a material that is capable of being switched between two different polarization directions by applying an appropriate voltage difference across memory film 90. The memory film 90 may be a high-k dielectric material, such as a hafnium (Hf) based dielectric material. In some embodiments, memory film 90 comprises a ferroelectric material, such as hafnium oxide, hafnium zirconium oxide, silicon doped hafnium oxide, and the like. In some embodiments, memory film 90 may include different ferroelectric materials or different types of memory materials. In some embodiments, the memory film 90 may be a film comprising two SiO_xSiN between layers_xA multi-layer memory structure of layers (e.g., an ONO structure).

An OS layer 92 is conformally deposited in trench 86 over memory film 90. OS layer 92 comprises a material suitable for providing a channel region for transistor 204 (see fig. 1A and 1B). For example, the OS layer 92 may include zinc oxide (ZnO), indium tungsten oxide (InWO), indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), Indium Tin Oxide (ITO), polycrystalline silicon (poly-Si), amorphous silicon (a-Si), combinations thereof, and the like. The OS layer 92 may be deposited by CVD, PVD, ALD, PECVD, etc. OS layer 92 may extend along the sidewalls and bottom surface of trench 86 above memory film 90.

A first dielectric layer 98A is deposited in trench 86 over OS layer 92. The first dielectric layer 98A may comprise, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like, which may be deposited by CVD, PVD, ALD, PECVD, or the like. The first dielectric layer 98A may extend along sidewalls and a bottom surface of the trench 86 above the OS layer 92.

In fig. 14A and 14B, the bottom of the first dielectric layer 98A and the OS layer 92 are removed in the trench 86. The bottom of the first dielectric layer 98A may be removed using a combination of photolithography and etching. The etch may be any acceptable etch process such as wet or dry etch, RIE, NBE, etc., or combinations thereof. The etching may be anisotropic.

The first dielectric layer 98A may then be used as an etch mask to etch through the bottom of the OS layer 92 in the trench 86. The etch may be any acceptable etch process such as wet or dry etch, RIE, NBE, etc., or combinations thereof. The etching may be anisotropic. Etching the OS layer 92 may expose a portion of the memory film 90 on the bottom surface of the trench 86. Accordingly, portions of OS layer 92 on opposing sidewalls of trench 86 may be separated from each other, which improves isolation between memory cells 202 of memory array 200 (see fig. 1A and 1B).

In fig. 15A and 15B, additional dielectric material 98B is deposited to fill the remaining portions of the trenches 86. The additional dielectric material 98B may be formed of the same or similar materials and by the same or similar processes as those of the first dielectric layer 98A. The additional dielectric material 98B and the first dielectric layer 98A may be collectively referred to as dielectric material 98.

In fig. 16A and 16B, a removal process is applied to dielectric material 98, OS layer 92, and memory film 90 to remove excess material over multilayer stack 58. In some embodiments, a planarization process, such as CMP, an etch-back process, combinations thereof, and the like, may be utilized. The planarization process exposes the multilayer stack 58 such that the top surfaces of the multilayer stack 58 (e.g., conductive line 72G), memory film 90, OS layer 92, and dielectric material 98 are flush after the planarization process is complete.

Fig. 17A-20C illustrate intermediate steps in fabricating dielectric material 102, conductive lines 106 (e.g., bit lines), and conductive lines 108 (e.g., source lines) in memory array 200. Conductive lines 106 and conductive lines 108 may extend in a direction perpendicular to conductive lines 72, thereby enabling individual memory cells 202 of memory array 200 to be selected for read and write operations.

In fig. 17A and 17B, trench 100 is patterned through dielectric material 98 and OS layer 92. A trench 100 may be patterned in the dielectric material 98 and OS layer 92 by a combination of lithography and etching. The etch may be any acceptable etch process such as wet or dry etch, RIE, NBE, etc., or combinations thereof. The etching may be anisotropic. The trench 100 may be disposed between opposing sidewalls of the memory film 90, and the trench 100 may physically separate adjacent stacks of memory cells 202 in the memory array 200 (see fig. 1A).

In fig. 18A and 18B, a dielectric material 102 is deposited in the trench 100 filling the trench 100. The dielectric material 102 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, etc., which may be deposited by CVD, PVD, ALD, PECVD, etc. Dielectric material 102 may extend along sidewalls and a bottom surface of trench 100 above OS layer 92. After deposition, a planarization process (e.g., CMP, etchback, etc.) may be performed to remove excess portions of the dielectric material 102. In the resulting structure, the top surfaces of multilayer stack 58, memory film 90, OS layer 92, dielectric material 98, and dielectric material 102 may be substantially flush with each other (e.g., within process variations).

In some embodiments, the materials of dielectric material 98 and dielectric material 102 may be selected such that they may be selectively etched with respect to each other. For example, in some embodiments, the dielectric material 98 is an oxide and the dielectric material 102 is a nitride. In some embodiments, the dielectric material 98 is a nitride and the dielectric material 102 is an oxide. Other materials are also possible.

In fig. 19A and 19B, the trench 104 is patterned by the dielectric material 98. The trench 104 may then be used to form a conductive line. A combination of lithography and etching may be used to pattern the trench 104 through the dielectric material 98. The etch may be any acceptable etch process such as wet or dry etch, RIE, NBE, etc., or combinations thereof. The etching may be anisotropic. The etch may use an etchant that etches the dielectric material 98 without significantly etching the dielectric material 102. The pattern of trenches 104 may correspond to the pattern of subsequently formed conductive lines, such as conductive lines 106 and 108 discussed below with respect to fig. 20A-20C. Portions of the dielectric material 98 may remain between each pair of trenches 104, and the dielectric material 102 may be disposed between adjacent pairs of trenches 104.

In fig. 20A to 20C, the trench 104 is filled with a conductive material to form a wire 106 and a wire 108. Wire 106 and wire 108 may each comprise a conductive material such as copper, titanium nitride, tantalum nitride, tungsten, ruthenium, aluminum, combinations thereof, and the like. The conductive lines 106 and 108 may be formed using, for example, CVD, ALD, PVD, PECVD, etc. After depositing the conductive material, planarization (e.g., CMP, etchback, etc.) may be performed to remove excess portions of the conductive material, thereby forming conductive lines 106 and 108. In the resulting structure, the top surfaces of multilayer stack 58, memory film 90, OS layer 92, dielectric material 98, dielectric material 102, conductive lines 106, and conductive lines 108 may be substantially flush with each other (e.g., within process variations).

Conductive line 106 may correspond to a bit line in memory array 200 and conductive line 108 may correspond to a source line in memory array 200. In addition, conductive lines 106 and 108 may provide source/drain electrodes for transistors 204 in memory array 200. Although fig. 20C shows a cross-sectional view showing only wire 106, the cross-sectional view of wire 108 may be similar.

Fig. 21-28 illustrate patterning the multilayer stack 58 to form a stair-step structure 68 (shown in fig. 28). Although stair-step structure 68 is discussed as being formed after forming channel regions for transistor 204, conductive line 106, and conductive line 108, in some embodiments stair-step structure 68 may be formed prior to forming channel regions for transistor 204, conductive line 106, and conductive line 108. For example, the fabrication steps shown and described with respect to fig. 21-28 may be performed prior to the fabrication steps shown and described with respect to fig. 10A-20C to form the stair-step structure 68. The same or similar process may be used in the stair-first and stair-last embodiments.

In fig. 21, a photoresist 56 is formed over the multilayer stack 58. The photoresist 56 may be formed using spin-on techniques and may be patterned using acceptable photolithographic techniques. Patterned photoresist 56 may expose multilayer stack 58 in region 60 while masking the remaining portions of multilayer stack 58. For example, the topmost layer of the multilayer stack 58 (e.g., the wires 72G) may be exposed in the region 60.

Further in fig. 21, the exposed portions of multilayer stack 58 in regions 60 are etched using photoresist 56 as a mask. The etch may be any acceptable etch process such as wet or dry etch, RIE, NBE, etc., or combinations thereof. The etching may be anisotropic. The etch may remove portions of conductive line 72G and dielectric layer 52G in region 60 and define opening 61. Because conductive line 72G and dielectric layer 52G have different material compositions, the etchant used to remove the exposed portions of these layers may be different. In some embodiments, dielectric layer 52G serves as an etch stop during the etching of conductive line 72G, and conductive line 72F serves as an etch stop during the etching of dielectric layer 52G. Accordingly, portions of conductive lines 72G and dielectric layer 52G may be selectively removed without removing the remaining layers of multilayer stack 58, and opening 61 may extend to a desired depth. Alternatively, a timed etch process may be used to stop etching openings 61 after openings 61 reach a desired depth. In the resulting structure, the wires 72F are exposed in the region 60.

In fig. 22, the photoresist 56 is trimmed to expose additional portions of the multilayer stack 58. The photoresist 56 may be trimmed using acceptable photolithography techniques. As a result of trimming, the width of photoresist 56 is reduced and portions of multilayer stack 58 in regions 60 and 62 are exposed. For example, the top surface of the wire 72G in the region 62 and the top surface of the wire 72F in the region 60 may be exposed.

The exposed portions of multilayer stack 58 may then be etched using photoresist 56 as a mask. The etch may be any suitable etch process such as wet or dry etch, RIE, NBE, etc., or combinations thereof. The etching process may be anisotropic. The etch may extend opening 61 further into multilayer stack 58. Because the conductive lines 72 and the dielectric layer 52 have different material compositions, the etchant used to remove the exposed portions of these layers may be different. In some embodiments, dielectric layers 52G and 52F serve as etch stops during the etching of conductive lines 72G and 72F, respectively, and conductive lines 72F and 72E serve as etch stops during the etching of dielectric layers 52G and 52F, respectively. Accordingly, portions of the conductive lines 72 and the dielectric layer 52 may be selectively removed without removing the remaining layers of the multilayer stack 58, and the openings 61 may be extended to a desired depth. Alternatively, a timed etch process may be used to stop etching openings 61 after openings 61 reach a desired depth. Furthermore, during the etching process, the unetched portions of conductive line 72 and dielectric layer 52 serve as a mask for the underlying layers, and thus, the previous pattern of conductive line 72G and dielectric layer 52G (see fig. 21) may be transferred to underlying conductive line 72F and underlying dielectric layer 52F. In the resulting structure, wires 72F are exposed in region 62, and wires 72E are exposed in region 60.

In fig. 23, the photoresist 56 is trimmed to expose additional portions of the multilayer stack 58. The photoresist 56 may be trimmed using acceptable photolithography techniques. As a result of trimming, the width of photoresist 56 is reduced and portions of multilayer stack 58 in regions 60, 62, and 63 are exposed. For example, the top surface of wire 72G in region 63, the top surface of wire 72F in region 62, and the top surface of wire 72E in region 60 may be exposed.

The exposed portions of multilayer stack 58 may then be etched using photoresist 56 as a mask. The etch may be any suitable etch process such as wet or dry etch, RIE, NBE, etc., or combinations thereof. The etching process may be anisotropic. The etch may extend opening 61 further into multilayer stack 58. Because the conductive lines 72 and the dielectric layer 52 have different material compositions, the etchant used to remove the exposed portions of these layers may be different. In some embodiments, dielectric layers 52G, 52F, and 52E serve as etch stops during the etching of conductive lines 72G, 72F, and 72E, respectively, and conductive lines 72F, 72E, and 72D serve as etch stops during the etching of dielectric layers 52G, 52F, and 52E, respectively. Accordingly, portions of the conductive lines 72 and the dielectric layer 52 may be selectively removed without removing the remaining layers of the multilayer stack 58, and the openings 61 may be extended to a desired depth. Alternatively, a timed etch process may be used to stop etching openings 61 after openings 61 reach a desired depth. Furthermore, during the etching process, the unetched portions of conductive lines 72 and dielectric layer 52 serve as a mask for the underlying layers, and thus, the previous pattern of conductive lines 72G and 72F and dielectric layers 52G and 52F (see fig. 22) may be transferred to underlying conductive lines 72F and 72E and underlying dielectric layers 52F and 52E. In the resulting structure, wires 72F are exposed in region 63, wires 72E are exposed in region 62, and wires 72D are exposed in region 60.

In fig. 24, the photoresist 56 is trimmed to expose additional portions of the multilayer stack 58. The photoresist 56 may be trimmed using acceptable photolithography techniques. As a result of trimming, the width of photoresist 56 is reduced and portions of multilayer stack 58 in regions 60, 62, 63, and 64 are exposed. For example, the top surface of area wire 72G in 64, the top surface of wire 72F in area 63, the top surface of wire 72E in area 62, and the top surface of wire 72D in area 60 may be exposed.

The exposed portions of multilayer stack 58 may then be etched using photoresist 56 as a mask. The etch may be any suitable etch process such as wet or dry etch, RIE, NBE, etc., or combinations thereof. The etching process may be anisotropic. The etch may extend opening 61 further into multilayer stack 58. Because the conductive lines 72 and the dielectric layer 52 have different material compositions, the etchant used to remove the exposed portions of these layers may be different. In some embodiments, dielectric layers 52G, 52F, 52E, and 52D serve as etch stop layers during the etching of conductive lines 72G, 72F, 72E, and 72D, respectively, and conductive lines 72F, 72E, 72D, and 72C serve as etch stop layers during the etching of dielectric layers 52G, 52F, 52E, and 52D, respectively. Accordingly, portions of the conductive lines 72 and the dielectric layer 52 may be selectively removed without removing the remaining layers of the multilayer stack 58, and the openings 61 may be extended to a desired depth. Alternatively, a timed etch process may be used to stop etching openings 61 after openings 61 reach a desired depth. Furthermore, during the etching process, the unetched portions of conductive lines 72 and dielectric layer 52 serve as a mask for the underlying layers, and thus, the previous pattern of conductive lines 72G-72E and dielectric layers 52G-52E (see fig. 23) may be transferred to underlying conductive lines 72F-72D and underlying dielectric layers 52F-52D. In the resulting structure, wire 72F is exposed in region 64, wire 72E is exposed in region 63, wire 72D is exposed in region 62, and wire 72C is exposed in region 60.

In fig. 25, the photoresist 56 is trimmed to expose additional portions of the multilayer stack 58. The photoresist 56 may be trimmed using acceptable photolithography techniques. As a result of trimming, the width of photoresist 56 is reduced and portions of multilayer stack 58 in regions 60, 62, 63, 64, and 65 are exposed. For example, the top surface of wire 72G in region 65, the top surface of wire 72F in region 64, the top surface of wire 72E in region 63, the top surface of wire 72D in region 62, and the top surface of wire 72C in region 60 may be exposed.

The exposed portions of multilayer stack 58 may then be etched using photoresist 56 as a mask. The etch may be any suitable etch process such as wet or dry etch, RIE, NBE, etc., or combinations thereof. The etching process may be anisotropic. The etch may extend opening 61 further into multilayer stack 58. Because the conductive lines 72 and the dielectric layer 52 have different material compositions, the etchant used to remove the exposed portions of these layers may be different. In some embodiments, dielectric layers 52G, 52F, 52E, 52D, and 52C serve as etch stops during the etching of conductive lines 72G, 72F, 72E, 72D, and 72C, respectively, and conductive lines 72F, 72E, 72D, 72C, and 72B serve as etch stops during the etching of dielectric layers 52G, 52F, 52E, 52D, and 52C, respectively. Accordingly, portions of the conductive lines 72 and the dielectric layer 52 may be selectively removed without removing the remaining layers of the multilayer stack 58, and the openings 61 may be extended to a desired depth. Alternatively, a timed etch process may be used to stop etching openings 61 after openings 61 reach a desired depth. Furthermore, during the etching process, the unetched portions of conductive lines 72 and dielectric layer 52 serve as a mask for the underlying layers, and thus, the previous pattern of conductive lines 72G-72D and dielectric layers 52G-52D (see fig. 24) may be transferred to underlying conductive lines 72F-72C and underlying dielectric layers 52F-52C. In the resulting structure, wire 72F is exposed in region 65, wire 72E is exposed in region 64, wire 72D is exposed in region 63, wire 72C is exposed in region 62, and wire 72B is exposed in region 60.

In fig. 26, the photoresist 56 is trimmed to expose additional portions of the multilayer stack 58. The photoresist 56 may be trimmed using acceptable photolithography techniques. As a result of trimming, the width of photoresist 56 is reduced and portions of multilayer stack 58 in regions 60, 62, 63, 64, 65, and 66 are exposed. For example, a top surface of wire 72G in region 66, a top surface of wire 72F in region 65, a top surface of wire 72E in region 64, a top surface of wire 72D in region 63, a top surface of wire 72C in region 62 may be exposed, and a top surface of wire 72B in region 60 may be exposed.

The exposed portions of multilayer stack 58 may then be etched using photoresist 56 as a mask. The etch may be any suitable etch process such as wet or dry etch, RIE, NBE, etc., or combinations thereof. The etching process may be anisotropic. The etch may extend opening 61 further into multilayer stack 58. Because the conductive lines 72 and the dielectric layer 52 have different material compositions, the etchant used to remove the exposed portions of these layers may be different. In some embodiments, dielectric layers 52G, 52F, 52E, 52D, 52C, and 52B function as etch stops during the etching of conductive lines 72G, 72F, 72E, 72D, 72C, and 72B, respectively, and conductive lines 72F, 72E, 72D, 72C, 72B, and 72A function as etch stops during the etching of dielectric layers 52G, 52F, 52E, 52D, 52C, and 52B, respectively. Accordingly, portions of the conductive lines 72 and the dielectric layer 52 may be selectively removed without removing the remaining layers of the multilayer stack 58, and the openings 61 may be extended to a desired depth. Alternatively, a timed etch process may be used to stop etching openings 61 after openings 61 reach a desired depth. Furthermore, during the etching process, the unetched portions of conductive lines 72 and dielectric layer 52 serve as a mask for the underlying layers, and thus, the previous pattern of conductive lines 72G-72C and dielectric layers 52G-52C (see fig. 25) may be transferred to underlying conductive lines 72F-72B and underlying dielectric layers 52F-52B. In the resulting structure, wire 72F is exposed in region 66, wire 72E is exposed in region 65, wire 72D is exposed in region 64, wire 72C is exposed in region 63, wire 72B is exposed in region 62, and wire 72A is exposed in region 60.

In fig. 27, the photoresist 56 is trimmed to expose additional portions of the multilayer stack 58. The photoresist 56 may be trimmed using acceptable photolithography techniques. As a result of trimming, the width of photoresist 56 is reduced and portions of multilayer stack 58 in regions 60, 62, 63, 64, 65, 66, and 67 are exposed. For example, the top surface of wire 72G in region 67, the top surface of wire 72F in region 66, the top surface of wire 72E in region 65, the top surface of wire 72D in region 64, the top surface of wire 72C in region 63, the top surface of wire 72B in region 62, and the top surface of wire 72A in region 60 may be exposed.

The exposed portions of multilayer stack 58 may then be etched using photoresist 56 as a mask. The etch may be any suitable etch process such as wet or dry etch, RIE, NBE, etc., or combinations thereof. The etching process may be anisotropic. The etch may extend opening 61 further into multilayer stack 58. Because the conductive lines 72 and the dielectric layer 52 have different material compositions, the etchant used to remove the exposed portions of these layers may be different. In some embodiments, dielectric layers 52G, 52F, 52E, 52D, 52C, 52B, and 52A serve as etch stops during the etching of conductive lines 72G, 72F, 72E, 72D, 72C, 72B, and 72A, respectively, and conductive lines 72F, 72E, 72D, 72C, 72B, and 72A and substrate 50 serve as etch stops during the etching of dielectric layers 52G, 52F, 52E, 52D, 52C, 52B, and 52A, respectively. Accordingly, portions of the conductive lines 72 and the dielectric layer 52 may be selectively removed without removing the remaining layers of the multilayer stack 58, and the openings 61 may be extended to a desired depth. Alternatively, a timed etch process may be used to stop etching openings 61 after openings 61 reach a desired depth. Furthermore, during the etching process, the unetched portions of conductive lines 72 and dielectric layer 52 serve as a mask for the underlying layers, and thus, the previous pattern of conductive lines 72G-72B and dielectric layers 52G-52B (see FIG. 26) may be transferred to underlying conductive lines 72F-72A and underlying dielectric layers 52F-52A. In the resulting structure, wire 72F is exposed in region 67, wire 72E is exposed in region 66, wire 72D is exposed in region 65, wire 72C is exposed in region 64, wire 72B is exposed in region 63, wire 72A is exposed in region 62, and substrate 50 is exposed in region 60.

In fig. 28, the photoresist 56 may be removed, such as by an acceptable ashing or wet strip process. Thus, a memory array 200 is formed that includes a staircase structure 68. The stair-step structure 68 comprises a stack of alternating layers of conductive lines 72 and dielectric layers 52. As shown in fig. 28, the length of the wires 72 increases in a direction toward the substrate 50, such that the lower wires 72 are longer and extend laterally beyond the upper wires 72. Thus, in subsequent processing steps, conductive contacts may be made from over the stepped structure 68 to each of the leads 72.

In fig. 29, an inter-metal dielectric (IMD)70 is deposited over multilayer stack 58. IMD70 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, PECVD, flowable CVD (fcvd), and the like. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), Undoped Silicate Glass (USG), and the like. In some embodiments, IMD70 may include oxides (e.g., silicon oxide, etc.), nitrides (e.g., silicon nitride, etc.), combinations thereof, and the like. Other dielectric materials formed by any acceptable process may be used. IMD70 extends along sidewalls of conductive lines 72A-72G and sidewalls of dielectric layers 52A-52G. In addition, IMD70 may contact leads 72A-72G and the top surface of substrate 50.

In fig. 30A to 30D, a contact 110 is formed that extends to and is electrically coupled to the wire 72. The stepped shape of the wire 72 provides a surface on each of the wires 72 for the contact 110 to rest on. Forming contacts 110 may include patterning openings in IMD70 to expose portions of leads 72, for example, using a combination of lithography and etching. In some embodiments, the openings in IMD70 may be formed by a process having a high etch selectivity to the material of IMD 70. Thus, openings in IMD70 may be formed without significantly removing material of leads 72. In some embodiments, openings exposing each of the wires 72A-72G may be formed simultaneously. Because of the varying thickness of IMD70 overlying each of leads 72A-72G, lead 72G may be exposed to etching for a longer duration than lead 72F, lead 72F may be exposed to etching for a longer duration than lead 72E, and so on, with 72A being exposed to etching for a shortest duration. Exposure to etching results in some material loss, pitting, or other damage in wire 72 such that wire 72G is damaged to a maximum extent, wires 72F-72B are damaged to a lesser extent, and wire 72A is damaged to a minimum extent. In some embodiments, the openings to the conductive lines 72A-72G may be formed in one or more etching processes. For example, a first etching process may be used to form openings that expose wires 72A-72D, and a second etching process may be used to form openings to wires 72E-72G. In some embodiments, each of the etching processes performed on the conductive lines 72 may be performed on 4-5 layers of the conductive lines 72. Performing multiple etching processes to form the openings may reduce damage to the wires 72 away from the substrate 50.

A liner (not separately shown) such as a diffusion barrier layer, an adhesive layer, or the like and a conductive material are formed in the opening. The liner may comprise titanium, titanium nitride, tantalum nitride, and the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process such as CMP may be performed to remove excess material from the surface of IMD 70. The remaining pad and conductive material form a contact 110 in the opening. As shown in fig. 30A-30D, the contact 110 may extend to each of the leads 72A-72G.

Further, in fig. 30A to 30D, the contact 112 extending to and electrically coupled to the wire 106 and the wire 108 is formed. Forming contacts 112 may include patterning openings in IMD70 to expose portions of leads 106 and 108, for example, using a combination of lithography and etching. The contacts 112 may be formed using the same or similar processes and materials as those used to form the contacts 110. The contacts 112 may be formed simultaneously with the contacts 110 or separately from the contacts 110.

In fig. 31A to 31C, an interconnect structure 120 is formed over IMD70, contact 110, and contact 112. The interconnect structure 120 may include one or more layers of conductive features 122 formed in one or more stacked dielectric layers 124. Each of the stacked dielectric layers 124 may include a dielectric material, such as a low-k dielectric material, an ultra low-k (elk) dielectric material, and the like. Dielectric layer 124 may be deposited using a suitable process such as CVD, ALD, PVD, PECVD, and the like.

The conductive features 122 may include conductive lines and conductive vias interconnecting layers of the lines. Conductive vias may extend through respective dielectric layers 124 to provide vertical connections between layers of conductive lines. The conductive features 122 may be formed by any acceptable process, such as a damascene process, a dual damascene process, and the like.

In some embodiments, the conductive features 122 may be formed using a damascene process in which a respective dielectric layer 124 is patterned using a combination of photolithography and etching techniques to form trenches corresponding to the desired pattern of the conductive features 122. An optional diffusion barrier layer and/or an optional adhesion layer may be deposited in the trench, and the trench may then be filled with a conductive material. Suitable materials for the barrier layer include titanium, titanium nitride, titanium oxide, tantalum nitride, titanium oxide, or other alternatives. Suitable materials for the conductive material include copper, silver, gold, tungsten, aluminum, combinations thereof, and the like. In an embodiment, the conductive features 122 may be formed by depositing a seed layer of copper or copper alloy and filling the trenches with electroplating. A Chemical Mechanical Planarization (CMP) process or the like may be used to remove excess conductive material from the surface of the respective dielectric layer 124 and to planarize the surfaces of the conductive features 122 and dielectric layer 124 for subsequent processing.

Fig. 31A to 31C show three layers of the conductive member 122 and the dielectric layer 124. However, it should be understood that the interconnect structure 120 may include any number of conductive features 122 disposed in any number of dielectric layers 124. The conductive members 122 of the interconnect structure 120 may be electrically coupled to the contacts 110 and 112.

In the embodiment shown in FIG. 31A, the contacts 110 electrically coupled to the leads 72A-72F extend only through the IMD70 such that the top surfaces of the contacts 110 are flush with the top surface of the IMD 70. However, in the embodiment shown in FIG. 31B, contacts 110 electrically coupled to leads 72A-72F extend through IMD70 and dielectric layer 124 such that the top surfaces of contacts 110 are flush with the top surface of topmost dielectric layer 124. The contacts 110 may be part of an interconnect structure 120. Forming the contacts 110 extending through the dielectric layer 124 and IMD70 reduces the patterning steps required to form the contacts 110 and interconnect structure 120, but reduces the flexibility of connection. Any of the embodiments shown in fig. 31A and 31B may be used in a subsequently formed device.

Fig. 32-34 illustrate bonding a semiconductor die to an interconnect structure 120. In fig. 32, the backside of the semiconductor device 300 is bonded to the interconnect structure 120. In the illustrated embodiment, the semiconductor device 300 is bonded to the interconnect structure 120 by hybrid bonding. The topmost dielectric layer 124 is bonded to the substrate 350 by a dielectric-to-dielectric bond without using any adhesive material (e.g., die attach film), and the topmost conductive member 122 is bonded to the TSV332 by a metal-value metal bond without using any eutectic material (e.g., solder). Bonding may include pre-bonding and annealing. During pre-bonding, a small pressure is applied to press the semiconductor device 300 against the interconnect structure 120. The pre-bonding is performed at a low temperature, such as room temperature, such as a temperature in the range of about 15 ℃ to about 30 ℃. In some embodiments, an oxide, such as a native oxide, is formed at the backside of the substrate 350 for bonding. The bond strength is then improved in a subsequent annealing step in which the dielectric layer 124 and the substrate 350 are annealed at a high temperature, such as a temperature in the range of about 100 ℃ to about 400 ℃. After annealing, a bond, such as a fusion bond, is formed joining the dielectric layer 124 and the substrate 350. For example, the bond may be a covalent bond between the dielectric layer 124 and the substrate 350. Conductive feature 122 and TSV332 may be in physical contact after pre-bonding, or may expand to be in physical contact during annealing. Further, during the anneal, the materials of conductive feature 122 and TSV332 (e.g., copper) mix, forming a metal-to-metal bond. Thus, the resulting bond between the semiconductor device 300 and the interconnect structure 120 is a hybrid bond that includes a dielectric-to-dielectric bond and a metal-to-metal bond.

In some embodiments, the semiconductor device 300 may be a wafer including a plurality of integrated circuits, which are subsequently diced. In other embodiments, the semiconductor device 300 is cut prior to bonding, and one or more semiconductor dies may be bonded to the memory array 200. The memory array 200 may be diced before or after bonding to the semiconductor device 300. In embodiments where the memory array 200 and the semiconductor device 300 are diced after bonding, the memory array 200 and the semiconductor device 300 may be diced at the same time. Thus, the semiconductor device 300 may be bonded to the memory array 200 by wafer-to-wafer bonding (e.g., dicing the semiconductor device 300 and the memory array 200 after bonding), die-to-die bonding (e.g., dicing the semiconductor device 300 and the memory array 200 before bonding), or die-to-wafer bonding (e.g., dicing the semiconductor device 300 or the memory array 200 before bonding).

In some embodiments, the semiconductor device 300 may be a logic device that includes circuitry such as decoders, processors, multiplexers, controllers, sense amplifiers, and so forth. The semiconductor device 300 may provide control for read and write operations, etc. to the memory array 200. In contrast, memory array 200 may have no logic circuitry, and all transistors 204 in memory array 200 may be used as memory cells 202.

As discussed with respect to fig. 31A-31C, the interconnect structure 120 may provide connections to the contacts 110 and the contacts 112. Bonding the semiconductor device 300 to the interconnect structure 120 provides the circuitry of the semiconductor device 300 and the routing and interconnection between the contacts 110 and 112 of the memory array 200.

Bonding semiconductor device 300 to interconnect structure 120 formed over memory array 200 simplifies routing between memory array 200 and semiconductor device 300, reduces the number of process steps required to form the routing, and shortens the length of the connections between memory array 200 and semiconductor device 300, as compared to conventional memory arrays formed over semiconductor dies and routed to semiconductor dies by interconnect structures formed over and adjacent to the memory array. This reduces cost, reduces device defects, and improves device performance.

In fig. 33, the front side of the semiconductor device 400 is bonded to the interconnect structure 120. In the illustrated embodiment, the semiconductor device 400 is bonded to the interconnect structure 120 by hybrid bonding. The topmost dielectric layer 124 is bonded to the topmost dielectric layer 324 by a dielectric-to-dielectric bond without using any adhesive material (e.g., die attach film), and the topmost conductive component 122 is bonded to the topmost conductive component 322 by a metal-to-metal bond without using any eutectic material (e.g., solder). Bonding may include pre-bonding and annealing. During pre-bonding, a small pressure is applied to press the semiconductor device 400 against the interconnect structure 120. The pre-bonding is performed at a low temperature, such as room temperature, such as a temperature in the range of about 15 ℃ to about 30 ℃. The bond strength is then improved in a subsequent annealing step in which dielectric layer 124 and dielectric layer 324 are annealed at a high temperature, such as a temperature in the range of about 100 ℃ to about 400 ℃. After annealing, a bond, such as a fusion bond, is formed joining dielectric layer 124 and dielectric layer 324. For example, the bond may be a covalent bond between dielectric layer 124 and dielectric layer 324. Conductive feature 122 and conductive feature 322 may be in physical contact after pre-bonding, or may expand to be in physical contact during annealing. Further, during the anneal, the materials of conductive features 122 and conductive features 322 (e.g., copper) mix, forming a metal-to-metal bond. Thus, the resulting bond between the semiconductor device 400 and the interconnect structure 120 is a hybrid bond that includes a dielectric-to-dielectric bond and a metal-to-metal bond.

In some embodiments, the semiconductor device 400 may be a wafer including a plurality of integrated circuits, which will be subsequently diced. In other embodiments, the semiconductor device 400 is cut prior to bonding, and one or more semiconductor dies may be bonded to the memory array 200. The memory array 200 may be diced before or after bonding to the semiconductor device 400. In embodiments where the memory array 200 and the semiconductor device 400 are diced after bonding, the memory array 200 and the semiconductor device 400 may be diced at the same time. Thus, the semiconductor device 400 may be bonded to the memory array 200 by wafer-to-wafer bonding (e.g., dicing the semiconductor device 400 and the memory array 200 after bonding), die-to-die bonding (e.g., dicing the semiconductor device 400 and the memory array 200 before bonding), or die-to-wafer bonding (e.g., dicing the semiconductor device 400 or the memory array 200 before bonding).

In some embodiments, the semiconductor device 400 may be a logic device including circuits such as decoders, processors, multiplexers, controllers, sense amplifiers, and the like. The semiconductor device 400 may provide control for read and write operations, etc. to the memory array 200. Conversely, the memory array 200 may have no logic circuitry, and all of the transistors 204 in the memory array 200 may be used as memory cells 202.

As discussed with respect to fig. 31A-31C, the interconnect structure 120 may provide connections to the contacts 110 and the contacts 112. Bonding semiconductor device 400 to interconnect structure 120 provides the circuitry of semiconductor device 400 and the routing and interconnection between contacts 110 and contacts 112 of memory array 200.

Bonding the semiconductor device 400 to the interconnect structure 120 formed over the memory array 200 simplifies routing between the memory array 200 and the semiconductor device 400, reduces the number of process steps required to form the routing, and shortens the length of the connection between the memory array 200 and the semiconductor device 400 as compared to conventional memory arrays formed over semiconductor dies and routed to semiconductor dies by interconnect structures formed over and adjacent to the memory array. This reduces cost, reduces device defects, and improves device performance.

In fig. 34, a plurality of semiconductor devices 300 are bonded to the interconnect structure 120. As previously discussed, each of the semiconductor devices 300 may be a logic die, a peripheral die, a memory die, a power management die, an RF die, a sensor die, a MEMS die, a signal processing die, a front-end die, the like, or combinations thereof. In some embodiments, the plurality of semiconductor devices 300 may include a logic die and a peripheral die, such as an input/output die. The logic die may include circuits such as decoders, processors, multiplexers, controllers, sense amplifiers, and so forth. The logic die may provide control for read and write operations, etc. to the memory array 200. In contrast, memory array 200 may have no logic circuitry, and all transistors 204 in memory array 200 may be used as memory cells 202. The input/output die may be used to interface with external semiconductor devices and the like. The semiconductor device 300 may be bonded to the interconnect structure 120 using the same or similar processes as those discussed above with respect to the embodiment shown in fig. 32.

As discussed with respect to fig. 31A-31C, the interconnect structure 120 may provide connections to the contacts 110 and the contacts 112. Bonding the semiconductor device 300 to the interconnect structure 120 provides routing and interconnection between the circuitry of the semiconductor device 300 and the contacts 110 and 112 of the memory array 200.

Bonding semiconductor device 300 to interconnect structure 120 formed over memory array 200 simplifies routing between memory array 200 and semiconductor device 300, reduces the number of process steps required to form the routing, and shortens the length of the connections between memory array 200 and semiconductor device 300, as compared to conventional memory arrays formed over semiconductor dies and routed to semiconductor dies by interconnect structures formed over and adjacent to the memory array. This reduces cost, reduces device defects, and improves device performance. Also, any number of semiconductor devices 300 or semiconductor devices 400 may be bonded to memory array 200.

Fig. 35-37 illustrate an embodiment of forming a bonding layer 402 over the interconnect structure 120 of the memory array 200, bonding the substrate 350 to the bonding layer 402, and forming circuitry of the semiconductor device 300 in and on the substrate 350. In fig. 35, a bonding layer 402 is formed over interconnect structures 120 of memory array 200. In some embodiments, the bonding layer 402 comprises silicon oxide (e.g., High Density Plasma (HDP) oxide, etc.) deposited by CVD, ALD, PVD, etc. Other suitable materials may be used for the bonding layer 402.

In fig. 36, a substrate 350 is bonded to a bonding layer 402. The substrate 350 may be the same as discussed above with respect to fig. 2. The substrate 350 may be bonded to the bonding layer 402 by fusion bonding or the like. In some embodiments, the substrate 350 may be bonded to the bonding layer 402 by a dielectric-to-dielectric bond without the use of any adhesive material (e.g., a die attach film). Bonding may include pre-bonding and annealing. During pre-bonding, a small pressure is applied to press the substrate 350 against the bonding layer 402. The pre-bonding is performed at a low temperature, such as room temperature (e.g., a temperature in the range of about 15 ℃ to about 30 ℃). In some embodiments, an oxide, such as a native oxide, is formed at the backside of the substrate 350 for bonding. Then, the bond strength is improved in a subsequent annealing step in which the substrate 350 and the bonding layer 402 are annealed at a high temperature, such as a temperature in the range of about 100 ℃ to about 400 ℃. After annealing, a bond, such as a fusion bond, is formed that bonds the substrate 350 to the bonding layer 402. For example, the bond may be a covalent bond between the substrate 350 and the bonding layer 402.

The substrate 350 may be singulated before or after bonding the substrate 350 to the memory array 200. For example, in some embodiments, substrate 350 may be a wafer that is bonded to memory array 200 and subsequently singulated. The wafer may be singulated by sawing along the scribe areas and the individual substrates 350 may be separated from each other. In some embodiments, substrate 350 may be a die that is singulated prior to bonding to memory array 200.

In fig. 37, circuitry is formed in and over a substrate 350 to form a semiconductor device 300. The same or similar processes as those described in fig. 3-8A may be performed to form the semiconductor device 300. As shown in fig. 37, a TSV332 may be formed that extends through the substrate 350 and the bonding layer 402. The TSVs 332 may be electrically coupled and in physical contact with the conductive features 122 of the interconnect structure 120. The TSVs 332 may taper and narrow in a direction toward the memory array 200.

Bonding the substrate 350 to the interconnect structure 120 formed over the memory array 200 simplifies routing between the memory array 200 and the semiconductor device 300, reduces the number of process steps required to form the routing, and shortens the length of the connection between the memory array 200 and the semiconductor device 300 as compared to conventional memory arrays formed over semiconductor dies and routed to semiconductor dies by interconnect structures formed over and adjacent to the memory array. This reduces cost, reduces device defects, and improves device performance.

Embodiments may achieve various advantages. For example, forming an interconnect structure over the memory array and directly bonding the semiconductor die to the interconnect structure simplifies the interconnects between the semiconductor die and the memory array, reduces interconnect length, and reduces the steps required to form the interconnects. This reduces cost, reduces device defects, and improves device performance.

According to an embodiment, a semiconductor device includes: a memory array, comprising: a gate dielectric layer contacting the first word line and the second word line; and an Oxide Semiconductor (OS) layer contacting the source line and the bit line, a gate dielectric layer disposed between the OS layer and each of the first word line and the second word line; an interconnect structure located over the memory array, a distance between the second word line and the interconnect structure being less than a distance between the first word line and the interconnect structure; and an integrated circuit die bonded to the interconnect structure opposite the memory array, the integrated circuit die bonded to the interconnect structure by dielectric-to-dielectric bonding and metal-to-metal bonding. In an embodiment, the length of the first word line is greater than the length of the second word line. In an embodiment, a front-side interconnect structure of an integrated circuit die is bonded to an interconnect structure. In an embodiment, the backside of the integrated circuit die is bonded to the interconnect structure. In an embodiment, the integrated circuit die includes substrate vias extending through the semiconductor substrate, the substrate vias electrically coupling source/drain regions of the integrated circuit die to the interconnect structure. In an embodiment, the interconnect structure includes a first contact electrically coupling the first wordline to the integrated circuit die, the first contact extending from the first wordline to the integrated circuit die. In an embodiment, the semiconductor device further comprises: a second integrated circuit die hybrid bonded to an interconnect structure adjacent to the integrated circuit die.

According to another embodiment, a device comprises: a logic die comprising a semiconductor substrate; an interconnect structure located over the logic die; and a memory array located over the interconnect structure, the memory array comprising: a first memory cell including a first portion of a gate dielectric layer contacting a first word line; and a second memory cell including a second portion of the gate dielectric layer contacting the second word line, the second memory cell disposed farther from the interconnect structure than the first memory cell in a first direction perpendicular to the major surface of the semiconductor substrate, the second word line having a length in a second direction perpendicular to the first direction greater than a length of the first word line in the second direction, and the logic die including circuitry configured to perform read and write operations in the memory array. In an embodiment, the logic die is bonded to the interconnect structure by dielectric-to-dielectric bonding and metal-to-metal bonding. In an embodiment, the logic die includes a front-side interconnect structure, and the front-side interconnect structure is bonded to the interconnect structure. In an embodiment, the back side of the logic die is bonded to the interconnect structure. In an embodiment, the logic die includes a substrate via electrically coupled to the source/drain region, the substrate via extends through the semiconductor substrate of the logic die, and the semiconductor substrate and the substrate via are bonded to the interconnect structure. In an embodiment, the interconnect structure includes a contact extending from the substrate via to the first word line.

According to a further embodiment, the method comprises: forming a memory array, the forming a memory array comprising: forming a multilayer stack over a substrate, the multilayer stack comprising alternating conductive and dielectric layers; patterning a first trench extending through the multilayer stack; depositing a gate dielectric layer along sidewalls and a bottom surface of the first trench; and depositing an Oxide Semiconductor (OS) layer over the gate dielectric layer; forming a first interconnect structure over the memory array; and bonding the integrated circuit device to the first interconnect structure using a dielectric-to-dielectric bond and a metal-to-metal bond. In an embodiment, the method further comprises: read/write operations are implemented in the memory array, and the integrated circuit device controls the read/write operations. In an embodiment, a backside of the integrated circuit device is bonded to the first interconnect structure. In an embodiment, a plurality of integrated circuit devices on the wafer are bonded to the first interconnect structure, the plurality of integrated circuit devices including integrated circuit devices, the method further comprising dicing the memory array and the wafer. In an embodiment, forming the memory array further comprises: the conductive layer and the dielectric layer are etched to form a stepped structure, the conductive layer and the dielectric layer having a reduced length in a direction away from the substrate. In an embodiment, a first interconnect structure is formed over a memory array opposite a substrate. In an embodiment, bonding the integrated circuit device to the first interconnect structure includes bonding a front-side interconnect structure of the integrated circuit device to the first interconnect structure.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.