阅读说明：本技术 同步镜延迟电路和同步镜延迟操作方法 (Synchronous mirror delay circuit and synchronous mirror delay operation method ) 是由 何文乔 于 2018-08-27 设计创作，主要内容包括：本发明提供了一种同步镜延迟电路。同步镜延迟电路包括延迟监视电路、向前延迟电路、第一位移电路、向后延迟电路、第二位移电路,以及时脉频率检验电路。时脉频率检验电路包含复数时脉频率检验单元。每一时脉频率检验单元会判断外部输入时脉信号的频率是否比振荡器输出的参考时脉信号的频率慢,以产生一判断结果。每一时脉频率检验单元会将判断结果传送给第一位移电路和第二位移电路。第一位移电路和第二位移电路会根据判断结果,决定是否先延迟外部输入时脉信号。(The invention provides a synchronous mirror delay circuit. The synchronous mirror delay circuit includes a delay monitor circuit, a forward delay circuit, a first shift circuit, a backward delay circuit, a second shift circuit, and a clock frequency check circuit. The clock frequency checking circuit includes a plurality of clock frequency checking units. Each clock frequency checking unit will determine whether the frequency of the external input clock signal is slower than the frequency of the reference clock signal output by the oscillator, so as to generate a determination result. Each clock frequency checking unit will transmit the judgment result to the first shift circuit and the second shift circuit. The first shift circuit and the second shift circuit determine whether to delay the external input clock signal according to the determination result.)

1. A synchronous mirror delay circuit, the circuit comprising:

a delay monitor circuit coupled to an input buffer;

a forward delay circuit;

a first shift circuit coupled to said delay monitor circuit and said forward delay circuit;

a backward delay circuit;

a second shift circuit coupled to the backward delay circuit and a clock driver; and

a clock frequency checking circuit coupled to the first shift circuit and the second shift circuit,

wherein the clock frequency checking circuit determines whether a frequency of an externally input clock signal is slower than a frequency of a reference clock signal to generate a determination result, and transmits the determination result to the first and second shift circuits, and

the first shift circuit and the second shift circuit determine whether to delay the external input clock signal first according to the judgment result.

2. The synchronous mirror delay circuit of claim 1, wherein the delays produced by the first and second shift circuits are greater than the delays produced by the forward and backward delay circuits.

3. The synchronous mirror delay circuit of claim 1 wherein the clock frequency check circuit comprises a plurality of clock frequency check units.

4. The synchronous mirror delay circuit of claim 3, further comprising: a frequency divider coupled to the clock frequency checking circuit,

wherein the frequency dividing circuit divides the reference clock signal into frequencies according to different multiples and inputs the reference clock signals with different frequencies into each clock frequency checking unit respectively,

each clock pulse frequency checking unit respectively transmits the judgment result of the reference clock pulse signal corresponding to different frequencies to the first shift circuit and the second shift circuit.

5. The synchronous mirror delay circuit of claim 4 wherein the clock frequency verification circuit further comprises:

a plurality of decision logic circuits coupled to each of the clock frequency check units,

the majority logic circuit receives the judgment result of each clock frequency checking unit and ignores the unreasonable judgment result in all the judgment results according to all the judgment results.

6. The synchronous mirror delay circuit of claim 3, wherein the clock frequency verification unit comprises:

a first register for receiving the reference clock signal and the external input clock signal;

a second register for receiving a reverse reference clock signal and the external input clock signal;

an AND gate coupled to the first register and the second register and generating a flag signal according to output signals of the first register and the second register;

a third register coupled to the AND gate and receiving the flag signal and an inverted external input clock signal; and

an SR latch coupled to the third register and outputting the determination result according to the output signal of the third register.

7. The synchronous mirror delay circuit of claim 1, wherein the first and second displacement circuits each comprise:

a plurality of switching circuits; and

plural delay circuits, which will generate different delay values respectively;

wherein, according to the determination result, if the external input clock signal needs to be delayed first, one or more of the plurality of switch circuits are turned on to determine how long the external input clock signal should be delayed.

8. A synchronous mirror delay operation method is applied to a synchronous mirror delay circuit, and is characterized by comprising the following steps:

judging whether the frequency of an external input clock pulse signal is slower than that of a reference clock pulse signal through a clock pulse frequency check circuit of the synchronous mirror delay circuit so as to generate a judgment result;

a first shift circuit and a second shift circuit for transmitting the determination result to the synchronous mirror delay circuit, an

The first shift circuit and the second shift circuit determine whether to delay the external input clock signal first according to the judgment result.

9. The synchronous mirror delay operation of claim 8, wherein the delay generated by the first and second shift circuits is greater than the delay generated by a forward delay circuit and a backward delay circuit of the synchronous mirror delay circuit.

10. The synchronized mirror delay operation method of claim 8, further comprising:

when the frequency of the external input clock pulse signal is slower than that of the reference clock pulse signal, the judgment result generated by the clock pulse frequency inspection circuit is a first level; and

when the frequency of the external input clock pulse signal is not slower than the frequency of the reference clock pulse signal, the judgment result generated by the clock pulse frequency inspection circuit is a second level.

11. The synchronized mirror delay operation method of claim 10, further comprising:

when the judgment result is the first level, determining how long the external input clock signal is delayed by the first shift circuit and the second shift circuit according to the frequency of the reference clock signal; and

when the determination result is the second level, the external input clock signal is not delayed by the first shift circuit and the second shift circuit.

12. The method of claim 8, wherein the clock frequency checking circuit comprises a plurality of clock frequency checking units, the method further comprising:

reducing the frequency of the reference clock signal by different multiples through a frequency dividing circuit;

inputting the reference clock signals with different frequencies into each clock frequency checking unit for checking the clock frequency respectively; and

and respectively transmitting the judgment results of the reference clock signals corresponding to different frequencies to the first shift circuit and the second shift circuit through each clock frequency checking unit.

13. The synchronized mirror delay operation method of claim 12, further comprising:

receiving the judgment result of each clock frequency checking unit through a majority logic circuit; and

and ignoring unreasonable judgment results in all the judgment results according to all the judgment results through the majority logic circuit.

14. The synchronous mirror delay operation method of claim 8, wherein the first and second shift circuits respectively include a digital-to-analog converter and a delay control circuit, and the synchronous mirror delay operation method further comprises:

receiving the judgment result through the digital-to-analog converter, and generating a potential signal corresponding to the judgment result according to the judgment result; and

determining, by the delay control circuit, whether to delay the external input clock signal according to the potential signal, and determining how long the external input clock signal should be delayed if the external input clock signal needs to be delayed.

Technical Field

The present invention relates generally to a Synchronous Mirror Delay (SMD) circuit technology, and more particularly to a SMD circuit technology applicable to a wide bandwidth range.

Background

Synchronous mirror delay circuits are widely used in the design of memory circuits. The synchronous mirror delay circuit can be used for synchronizing an external input clock signal and an internal operation clock signal of the memory circuit according to different external input clock signals input into the memory circuit.

As shown in fig. 1, the memory circuit 100 may include an input buffer (input buffer)110, a synchronous mirror delay circuit 120, and a clock driver (clock driver) 130. In addition, the synchronous mirror delay circuit 120 may include a Delay Monitor Circuit (DMC) 121,A forward delay (forward delay) circuit 123, a phase detector (phase detector) circuit 124, and a backward delay (backward delay) circuit 125, wherein the forward delay circuit 123, the phase detector circuit 124, and the backward delay circuit 125 each include delay units of complex order. FIG. 2 shows an original external input clock signal CLK_EXTInternal operation clock signal CLK_INTAnd an externally input clock signal CLK_EXTSignal at point B, D, E.

Referring to FIG. 2, in the conventional SMD operation, in order to externally input a clock signal CLK_EXTAnd internal operation clock signal CLK of memory circuit_EXTSynchronization can be achieved by making it necessary for the delay tV from point B to point D in the synchronous mirror delay circuit 120 to satisfy the condition of tV ═ tCK- (D1+ D2), where tV represents the delay generated by the front delay circuit 123 and the rear delay circuit 125, and tCK represents the externally input clock signal CLK_EXTThe period of (c). Therefore, when the conditions are satisfied, the derivation is carried out (i.e. 2 × d1+ d2+2 × tV + d2 ═ 2 × d1+ d2+2 × tCK- (d1+ d2)]+ d2 ═ 2 × tCK), it is known that after 2 times tCK time, the clock signal CLK is inputted from the outside_EXTAnd internal operation clock signal CLK of memory circuit_EXTSynchronization can be achieved.

However, in the conventional SMD operation, the externally input clock signal CLK is unknown_EXTIs fast or slow, so that it is necessary to pre-configure a relatively multi-stage delay unit so that if the clock signal CLK is inputted externally_EXTWhen the period of the clock signal CLK is slow, the clock signal CLK is inputted_EXTAnd internal operation clock signal CLK of memory circuit_EXTSynchronization can still be achieved.

However, these multi-step delay cells will cause the synchronous mirror delay circuit to generate larger current consumption and require larger size in the process of the synchronous mirror delay circuit.

Disclosure of Invention

In view of the foregoing problems, the present invention provides a synchronous mirror delay circuit, which is suitable for a wide period of an external input clock signal and has a smaller current consumption and a smaller size compared to the conventional SMD.

A synchronous mirror delay circuit is provided according to an embodiment of the present invention. The synchronous mirror delay circuit comprises a delay monitoring circuit, a forward delay circuit, a first shift circuit, a backward delay circuit, a second shift circuit and a clock frequency checking circuit. The delay monitor circuit is coupled to an input buffer. A first shift circuit couples the delay monitor circuit and the forward delay circuit. The second shift circuit is coupled to the backward delay circuit and a clock driver. The clock frequency checking circuit is coupled to an oscillator, the first shift circuit and the second shift circuit, and includes a plurality of clock frequency checking units. Each clock pulse frequency checking unit judges whether the frequency of an external input clock pulse signal is slower than that of a reference clock pulse signal output by the oscillator so as to generate a judgment result, and transmits the judgment result to the first shift circuit and the second shift circuit. The first shift circuit and the second shift circuit determine whether to delay the external input clock signal according to the judgment result.

A Synchronous Mirror Delay (SMD) operation method is provided according to an embodiment of the present invention. The synchronous mirror delay operation method is suitable for a synchronous mirror delay circuit. The synchronous mirror delay operation method comprises the following steps: judging whether the frequency of an external input clock pulse signal is slower than the frequency of a reference clock pulse signal output by the oscillator through a clock pulse frequency check circuit of the synchronous mirror delay circuit so as to generate a judgment result; and transmitting the judgment result to a first shift circuit and a second shift circuit of the synchronous mirror delay circuit, and determining whether to delay the external input clock pulse signal first through the first shift circuit and the second shift circuit according to the judgment result.

Other additional features and advantages of the present invention will be apparent to those skilled in the art, and it is intended that various modifications and variations can be made in the synchronous mirror delay circuit and the synchronous mirror delay operation method disclosed in the present application without departing from the spirit and scope of the invention.

Drawings

FIG. 1 is a block diagram of a conventional memory circuit.

FIG. 2 is a timing diagram showing the corresponding memory circuit.

FIG. 3 is a block diagram of a memory circuit according to an embodiment of the invention.

FIG. 4 is a circuit diagram of a clock frequency checking unit according to an embodiment of the present invention.

FIG. 5A is a timing diagram illustrating an embodiment of the present invention when the frequency of the external input clock signal is slower than the frequency of the reference clock signal.

FIG. 5B is a timing diagram illustrating an embodiment of the present invention when the frequency of the external input clock signal is faster than the frequency of the reference clock signal.

FIG. 5C is a timing diagram of the memory circuit according to the embodiment of the invention.

FIG. 6 is a diagram illustrating a clock frequency checking circuit according to an embodiment of the present invention.

FIG. 7 is a diagram illustrating a clock frequency checking circuit according to another embodiment of the present invention.

FIG. 8 is a diagram illustrating a shift circuit according to an embodiment of the present invention.

FIG. 9 is a diagram illustrating a shift circuit according to another embodiment of the present invention.

FIG. 10 is a flowchart of a method for delaying a synchronous mirror according to an embodiment of the present invention.

Reference numerals

100. 300 memory circuits 110, 310 input buffer

120. 320 synchronous mirror delay circuit

121. 321 delay monitor circuit

322 first shift circuit 123, 323 forward delay circuit

124. 324 phase detector circuit

125. 325 backward delay circuit 450 third register

326 second displacement circuit 460SR latch

327 clock frequency checking circuit 710 majority logic circuit

130. 330 clock driver 800, 900 displacement circuit

340 oscillator 810 first delay circuit

410 OR gate 820 second delay circuit

420 first register 830 third delay circuit

430 second register 910 digital to analog converter

440 AND gate 920 delay control circuit

CFC 0-CFC n-1 clock frequency checking unit

CLK_BASE、CLK_BASE/1、CLK_BASE/2…CLK_BASE/2^(n-1)Reference clock signal

CLK_EXTExternally inputting clock signal

CLK_INTInternal operation clock signal

CLKSLOW, CLKSLOW [0] -CLKSLOW [ n-1] judgment results

FG generates flag signal RESET RESET signal

IN input SW0 first switch

OUT output terminal SW1 second switch

POR enable reset signal SW2 third switch

Q_outOutput signal TRG2 second trigger signal

Vbias potential signal TRG1 first trigger signal

ZCLK_BASEReverse reference clock signal

ZCLK_EXTReverse external input clock signal

Detailed Description

The best mode for carrying out the invention is set forth in this section for the purpose of illustrating the spirit of the invention and not for the purpose of limiting the scope of the invention as defined by the appended claims.

FIG. 3 shows a block diagram of a memory circuit 300 according to an embodiment of the invention. As shown in fig. 3, the memory circuit 300 may include an input buffer 310, a synchronous mirror delay circuit 320, a clock driver 330, and an oscillator 340.

As shown in fig. 3, the synchronous mirror delay circuit 320 may include a delay monitor circuit 321, a first shift circuit 322, a forward delay circuit 323, a phase detector circuit 324, a backward delay circuit 325, a second shift circuit 326, and a clock-frequency-checker (CSC) circuit 327. The delay monitor circuit 321 may include a dummy input buffer (dummy input buffer) and a dummy clock driver (dummy clock driver). The forward delay circuit 323, the phase detector circuit 324, and the backward delay circuit 325 may include delay units of complex order.

When the clock signal CLK is inputted from the outside_EXTAfter the clock signal CLK is inputted to the synchronous mirror delay circuit 320 through the input buffer 310_EXTIs sent to delay monitor circuit 321 and clock frequency check circuit 327. The clock frequency checking circuit 327 is used to check the clock frequency according to the externally inputted clock signal CLK_EXTAnd a reference clock signal CLK generated by an oscillator 340_BASEThe determination result CLKSLOW is generated and transmitted to the first shift circuit 322 and the second shift circuit 326. Then, the first shift circuit 322 determines the external input clock signal CLK outputted by the delay monitor circuit 321 according to the determination result CLKSLOW_EXTWhether or not it needs to be delayed for a certain time before being processed by the forward delay circuit 323, the phase detector circuit 324, and the backward delay circuit 325. Finally, the second shift circuit 326 outputs the external input clock signal CLK to the post delay circuit 325_EXTThe same operation as the first shift circuit 322 is performed,and processing the external input clock signal CLK_EXTTransmitted to the clock driver 330 to generate the internal operation clock signal CLK required by the control circuit of the memory circuit 300_INT. The following examples will be described in more detail.

As shown in fig. 4, the clock frequency checking circuit 327 may include an or gate 410, a first register 420, a second register 430, an and gate 440, a third register 450, and an SR latch 460. It should be noted that the clock frequency checking circuit unit can also achieve equivalent functions by other circuit architectures.

As shown in FIG. 4, the OR gate 410 receives an enable reset signal POR or receives an externally input clock signal CLK_EXT. When the OR gate 410 receives the power-on reset signal POR or the external input clock signal CLK_EXTThe or gate 410 sends a RESET signal RESET to the pins RST of the first and second registers 420 and 430 to RESET the values of the pins Q of the first and second registers 420 and 430 (e.g., to RESET the value of Q to 0). That is, the reset signal POR is activated or the clock signal CLK is externally inputted_EXTThe value of the pin Q of the first register 420 and the second register 430 is reset (e.g., the value of Q is reset to 0).

In this embodiment, the pin CK of the first register 420 receives the reference clock signal CLK_BASEAnd the pin D of the first register 420 receives the clock signal CLK_EXT. At each reference clock signal CLK_BASEPositive edge of (CLK), clock signal_EXTThe value of (c) is sent to the pin Q of the first register 420 to output the first trigger signal TRG1 to the and gate 440 (see fig. 5A-5B). In addition, the pin CK of the second register 430 receives the reverse reference clock signal ZCLK_BASEAnd the pin D of the second register 430 receives the clock signal CLK_EXT. At each reverse reference clock signal ZCLK_BASEPositive edge of (CLK), clock signal_EXTThe value of (c) is sent to the pin Q of the second register 430 to output the second trigger signal TRG2 to the and gate 440 (see fig. 5A-5B). When the AND gate 440 receives the first trigger signal TRG1 and the second trigger signalWhen the signal TRG2 is asserted, the and gate 440 operates on the first trigger signal TRG1 and the second trigger signal TRG2 to generate the flag signal FG. Then, the AND gate 440 transmits the flag signal FG to the pin D of the third register 450.

In addition, in this embodiment, the pin CK of the third register 450 receives the inverted external input clock signal ZCLK_EXT. At each reverse external input clock signal ZCLK_EXTThe value of the flag signal FG is sent to the pin Q of the third register 450 to output the signal Q_outTo SR latch 460. SR latch 460 receives output signal Q_outThen, according to the output signal Q_outA determination result CLKSLOW is generated. According to an embodiment of the present invention, when the determination result CLKSLOW is a first level (e.g., 1), it indicates that the external input clock signal CLK is asserted_EXTIs compared with the reference clock signal CLK_BASEIs slow; when the determination result CLKSLOW is at a second level (e.g., 0), it indicates that the external input clock signal CLK is asserted_EXTHas a frequency no higher than that of the reference clock signal CLK_BASEIs slow.

Referring to fig. 5A, the and gate 440 operates on the first trigger signal TRG1 and the second trigger signal TRG 2. Therefore, when the values of the first trigger signal TRG1 and the second trigger signal TRG2 are both high (e.g., 1), the value of the flag signal FG is high (e.g., 1). In addition, the clock signal ZCLK is inputted in each reverse direction_EXTThe value of the flag signal FG is sent to the pin Q of the third register 450 to output the signal Q_outTo SR latch 460. Therefore, when the signal Q is output_outWhen the signal level is high (e.g., 1), the determination result CLKSLOW output by the SR latch 460 will be high (e.g., 1). When CLKSLOW is at high level, it indicates the external input clock signal CLK_EXTIs compared with the reference clock signal CLK_BASEIs slow. Therefore, the clock signal CLK is inputted from the outside_EXTA delay time is required by the first and second shift circuits 322 and 326. Thus, the forward delay circuit 323, the phase detector circuit 324 and the backward delay circuit 325 do not need to be configured muchA stage delay unit for achieving an internal operation clock signal CLK_INTAnd an original external input clock signal CLK_EXTSynchronization of (2).

Note that in the embodiment of the present invention, the forward delay circuit 323 and the backward delay circuit 325 also generate the delay tV, respectively. In addition, in the embodiment of the present invention, the delay generated by the first shift circuit 322 and the second shift circuit 326 is greater than tV.

On the other hand, as shown in FIG. 5B, since the first trigger signal TRG1 and the second trigger signal TRG2 are both at the high level (e.g., 1), the flag signal FG is both at the low level (e.g., 0). Since the flag signal FG is at a low level (e.g., 0), the determination result CLKSLOW output by the SR latch 460 is at a low level (e.g., 0). When the determination result CLKSLOW is not at the high level, it indicates that the external input clock signal CLK is not present_EXTHas a frequency no higher than that of the reference clock signal CLK_BASEIs slow. Therefore, the clock signal CLK is inputted from the outside_EXTWithout being delayed for a period of time by the first and second shift circuits 322, 326.

Referring to fig. 3 and 5C, according to an embodiment of the present invention, forward delay circuit 323 includes delay units D (0) -D (n), and backward delay circuit 325 includes delay units E (0) -E (n). The delay from point B in the synchronous mirror delay circuit 320 to the e (n) th delay cell of the backward delay circuit 325 is t1, the delay from the e (n) th delay cell of the backward delay circuit 325 to the clock driver 330 is t2, where t1 is tCSC + tFD, and t1 is t2, and where tCSC represents the delay time generated by the first shift circuit 322 and the second shift circuit 326, and tFD represents the delay generated by the forward delay circuit 323 and the backward delay circuit 325. Therefore, in order to externally input the clock signal CLK_EXTAnd internal operation clock signal CLK of memory circuit_EXTSynchronization can be achieved by making the delay t1 from point B in the synchronous mirror delay circuit 320 to the e (n) th delay cell of the backward delay circuit 325 meet the condition that t1 is tCK- (d1+ d2) so that the total delay time t is twice tCK (i.e., t is [ d1+ (d1+ d2) + t 1)+t2+d2]2t CK). Therefore, in the embodiment of the invention, the delay time required by the first shift circuit 322 and the second shift circuit 326 is determined according to the determination result CLKSLOW to satisfy the condition. Therefore, in the present invention, the forward delay circuit 323, the phase detector circuit 324, and the backward delay circuit 325 of the synchronous mirror delay circuit 320 can achieve the internal operation clock signal CLK without the need of configuring too many stages of delay units_INTAnd an original external input clock signal CLK_EXTSynchronization of (2).

As shown in FIG. 6, clock frequency checking circuit 327 may include a plurality of clock frequency checking units CFC [0]]～CFC[n-1]Wherein n is a positive integer. Each clock frequency checking unit CFC [0]]～CFC[n-1]The architecture shown in fig. 4 may be applied. According to an embodiment of the present invention, the synchronous mirror delay circuit 320 may further include a frequency divider circuit (not shown). The frequency divider circuit can divide the reference clock signal CLK_BASEDown-converting by different multiples to generate reference clock signal CLK with different frequencies_BASEE.g. CLK as shown in FIG. 6_BASE/1、CLK_BASE/2…CLKBASE/2^(n-1)。

As shown in FIG. 6, clock frequency checking unit CFC [0] of clock frequency checking circuit 327]～CFC[n-1]Will receive reference clock signal CLK with different frequencies respectively_BASE/1、CLK_BASE/2…CLK_BASE/2^(n-1). Clock frequency checking unit CFC [0]]～CFC[n-1]Will be based on the received reference clock signal CLK_BASE/1、CLK_BASE/2…CLK_BASE/2^(n-1)Respectively generate a determination result CLKSLOW [0]]、CLKSLOW[1]…CLKSLOW[n-1]. Each clock frequency checking unit CFC [0]]～CFC[n-1]Will generate the determination result CLKSLOW [0]]、CLKSLOW[1]…CLKSLOW[n-1]To the first shift circuit 322 and the second shift circuit 326. The first shift circuit 322 and the second shift circuit 326 can be used to determine CLKSLOW [0] according to all the determination results]、CLKSLOW[1]…CLKSLOW[n-1](or as CLKSLOW [ n-1: 0]]) Determining an external input clock signal CLK_EXTHow long the delay (or shift) is. For example, when only the determination result CLKSLOW [0]]Is 1 (i.e. only in the reference clock signal CLK)_BASEIs CLK_BASEAt time/1, a clock signal CLK is inputted from the outside_EXTHas a frequency higher than that of the reference clock signal CLK_BASESlow frequency of) of the clock signal CLK, the clock signal CLK is externally input_EXTIs only slightly slower than the reference clock signal CLK_BASESo as to delay the externally input clock signal CLK_EXTA shorter time. When the determination result CLKSLOW [ n-1]]Is 1 (i.e., at the reference clock signal CLK)_BASEIs CLK_BASE/1、CLK_BASE/2…CLK_BASE/2^(n-1)Clock, externally inputting clock signal CLK_EXTAre all of a higher frequency than the reference clock signal CLK_BASESlow frequency of) of the clock signal CLK, the clock signal CLK is externally input_EXTHas a relatively slow frequency and thus delays the externally input clock signal CLK_EXTFor a longer time.

As shown in FIG. 7, clock frequency checking circuit 327 further includes a majority logic circuit 710. A majority logic circuit 710 is coupled to each clock frequency checking unit CFC [0] of clock frequency checking circuit 327]～CFC[n-1]To receive the determination result CLKSLOW [0]]、CLKSLOW[1]…CLKSLOW[n-1]. When the majority logic 710 receives the determination result CLKSLOW [0]]、CLKSLOW[1]…CLKSLOW[n-1]Then, according to all the judgment results CLKSLOW [0]]、CLKSLOW[1]…CLKSLOW[n-1]And neglecting unreasonable judgment results in all judgment results. For example, if the reference clock signal CLK_BASE/4 and CLK_BASEDetermination result CLKSLOW [2 ] at/16]And CLKSLOW [4 ]]Are respectively 0 and 1, i.e. are judged as being compared with CLK_BASESlow/16 but slower than CLK_BASEFast/4, which is contradictory because of CLK_BASE16 ratio CLK_BASESlow at/4. At this time, the clock signal CLK can be referenced_BASE/1、CLK_BASE/2 and CLK_BASEThe judgment result at time/8. For example, at this time CLKSLOW [0]]、CLKSLOW[1]And CLKSLOW [3 ]]When all are 1, the majority logic 710 will use the corresponding reference clock signal CLK_BASEDetermination result CLKSLOW [4 ] of/16]. That is to say CLKSLOW [2 ]]The judgment of (1) should be ignored for erroneous judgment.

According to one embodiment of the present invention, the first shift circuit 322 and the second shift circuit 326 are configuredA plurality of switch circuits and a plurality of delay circuits to satisfy the requirements of different determination results CLKSLOW. For example, when the first shift circuit 322 and the second shift circuit 326 receive the determination result CLKSLOW from the clock frequency checking circuit 327 as 3 bits (i.e. the determination result CLKSLOW [2: 0]]) Meanwhile, 2 delay circuits are required to be disposed in the first shift circuit 322 and the second shift circuit 326 to satisfy the requirements of different determination results CLKSLOW. When the first and second shift circuits 322 and 326 are configured with 2 delay circuits, the first and second shift circuits 322 and 326 can generate 4 different delay values. In this embodiment, the 2 delay circuits may have different delay values. In addition, in this embodiment, the first shift circuit 322 and the second shift circuit 326 determine to turn on those switch circuits according to different determination results CLKSLOW. That is, the first shift circuit 322 and the second shift circuit 326 determine the external input clock signal CLK received from the delay monitor circuit 321 according to the different determination results CLKSLOW_EXTHow long the delay (or shift) is. The following description will be made by taking fig. 8 as an example.

The shift circuit 800 shown in fig. 8 is suitable for the first shift circuit 322 and the second shift circuit 326. The shift circuit 800 may include an input terminal IN, an output terminal OUT, a first switch SW0, a second switch SW1, a third switch SW2, a first delay circuit 810, and a second delay circuit 820. The first delay circuit 810 and the second delay circuit 820 have a delay 1 and a delay 2, respectively. When the CLKSLOW is [000], the first switch SW0 and the third switch SW2 are turned on, and the second switch SW1 is turned off, so that the shift circuit 800 does not have a delay. When the determination result CLKSLOW is [100], the third switch SW2 is turned on, and the first switch SW0 and the second switch SW1 are turned off, so that the delay 1 is generated in the shift circuit 800. When the CLKSLOW is [110], the first switch SW0 and the second switch SW1 are turned on, and the third switch SW2 is turned off, so that the delay 2 is generated in the shift circuit 800. When the CLKSLOW is [111], the second switch SW1 is turned on, and the first switch SW0 and the third switch SW2 are turned off, so that the shift circuit 800 generates the delays delay 1 plus delay 2.

The shift circuit 900 shown in fig. 9 is applicable to the first shift circuit 322 and the second shift circuit 326. The shift circuit 900 may include an input terminal IN, an output terminal OUT, a digital-to-analog converter 910, and a delay control circuit 920. The digital-to-analog converter 910 receives the determination result CLKSLOW from the clock frequency check circuit 327, and generates the potential signal Vbias corresponding to the determination result CLKSLOW according to the determination result CLKSLOW. The digital-to-analog converter 910 then transmits the voltage level signal Vbias to the delay control circuit 920. The delay control circuit 920 receives an external input clock signal CLK from an input IN_EXTAnd determines the external input clock signal CLK according to the potential signal Vbias received from the digital-to-analog converter 910_EXTHow long the delay (or shift) is.

Referring to fig. 10, the Synchronous Mirror Delay (SMD) operation method may be applied to the synchronous mirror delay circuit of the present invention. In step S1010, a clock frequency checking circuit of the synchronous mirror delay circuit determines an external input clock signal CLK_EXTWhether the frequency of the reference clock signal is higher than that of a reference clock signal CLK output by an oscillator_BASEIs slow to generate a determination result CLKSLOW. In step S1020, the clock frequency check circuit transmits the determination result CLKSLOW to a first shift circuit and a second shift circuit of the synchronous mirror delay circuit. In step S1030, the first and second shift circuits determine whether to delay the external input clock signal CLK first according to the determination result CLKSLOW_EXT。

According to an embodiment of the present invention, in the synchronous mirror delay operation method, when the clock signal CLK is inputted externally_EXTIs compared with the reference clock signal CLK_BASEWhen the clock frequency is slow, the determination result CLKSLOW generated by the clock frequency check circuit of the synchronous mirror delay circuit 320 is at a first level. When the clock signal CLK is inputted from the outside_EXTHas a frequency no higher than that of the reference clock signal CLK_BASEWhen the clock frequency is slow, the determination result CLKSLOW generated by the clock frequency check circuit of the synchronous mirror delay circuit 320 is at a second level.

According to an embodiment of the invention, the synchronous mirror delay operation methodThe method further includes that when the determination result CLKSLOW is at a first level, the first shift circuit and the second shift circuit will be based on the reference clock signal CLK_BASEDetermines the frequency of the external input clock signal CLK_EXTHow long the first is delayed. When the determination result CLKSLOW is at the second level, the first and second shift circuits do not delay the external input clock signal CLK first_EXT。

According to an embodiment of the present invention, the method further comprises a frequency divider circuit of the synchronous mirror delay circuit 320 for dividing the reference clock signal CLK_BASEThe reference clock signal CLK with different frequencies is divided down by different multiples and the frequency dividing circuit_BASEEach of the clock frequency check units of the clock frequency check circuit is inputted. Then, each clock frequency checking unit will respectively correspond to the reference clock signal CLK with different frequencies_BASEThe determination result CLKSLOW is transmitted to the first shift circuit and the second shift circuit. According to an embodiment of the present invention, the method further includes that a majority logic circuit of the synchronous mirror delay circuit 320 receives the determination result CLKSLOW of each clock frequency checking unit, and ignores unreasonable determination results in all the determination results CLKSLOW according to all the determination results CLKSLOW through the majority logic circuit.

According to an embodiment of the present invention, in the synchronous mirror delay operation method, the first shift circuit and the second shift circuit respectively include a plurality of switch circuits and a plurality of delay circuits. According to the determination result CLKSLOW, if the clock signal CLK is inputted externally_EXTThe first and second shift circuits are delayed to turn on one or more of the plurality of switch circuits to determine the external input clock signal CLK_EXTHow long the delay is. According to another embodiment of the present invention, in the synchronous mirror delay operation method, the first shift circuit and the second shift circuit respectively include a digital-to-analog converter and a delay control circuit. The digital-to-analog converter receives the determination result CLKSLOW and generates a potential signal Vbias corresponding to the determination result CLKSLOW according to the determination result CLKSLOW. The delay control circuit determines whether to delay the external input clock signal according to the potential signal VbiasNumber CLK_EXTAnd if the clock signal CLK is inputted externally_EXTNeeds to be delayed to determine the external input clock signal CLK_EXTHow long this is delayed.

According to the embodiment of the invention, the synchronous mirror delay operation method is provided when the clock signal CLK is inputted externally_EXTWhen the period of the clock signal CLK is too slow, the clock signal CLK is inputted_EXTWill be delayed for a period of time. Therefore, the forward delay circuit, the phase detector circuit, and the backward delay circuit of the synchronous mirror delay circuit 320 do not need to be configured with too many stages of delay cells to achieve the internal operation clock signal CLK_INTAnd an original external input clock signal CLK_EXTSynchronization of (2). Therefore, the method for operating the delay of the synchronous mirror according to the embodiment of the present invention can avoid the large current consumption of the delay circuit of the synchronous mirror and the large size required in the process of the delay circuit of the synchronous mirror. In addition, the Synchronous Mirror Delay (SMD) circuit 320 according to the present invention can be applied or operated in a wide-range.

Although the present disclosure has been described with reference to exemplary embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure.