阅读说明：本技术 用于经由温度设置本地电源域超时的方法及装置
(Method and apparatus for setting local power domain timeout via temperature
) 是由 S·J·洛维特 于 2019-05-21 设计创作，主要内容包括：本发明涉及用于经由温度设置本地电源域超时的方法及装置。一种半导体装置可包含：本地电源域,其经配置以选择性地将电力提供到存储器装置的逻辑块或防止电力到所述存储器装置的逻辑块；及温度传感器,其定位在所述半导体装置上。所述半导体装置还可包含超时电路,其至少部分基于来自温度传感器的温度信息将所述本地电源域的断电延迟超时时间。(The invention relates to a method and apparatus for setting local power domain timeouts via temperature. A semiconductor device may include: a local power domain configured to selectively provide power to or prevent power from logic blocks of a memory device; and a temperature sensor positioned on the semiconductor device. The semiconductor device may also include a timeout circuit that delays a power down of the local power domain for a timeout time based at least in part on temperature information from a temperature sensor.)
1. A memory device, comprising:
a local power domain configured to selectively provide power to or prevent power from logic blocks of the memory device;
a temperature sensor positioned on the memory device; and
a timeout circuit configured to delay a power down of the local power domain for a timeout time based at least in part on temperature information from the temperature sensor.
2. The memory device of claim 1, wherein the timeout circuit is configured to delay the powering down of the local power domain in response to signaling of an allowed power off state of the local power domain.
3. The memory device of claim 2, wherein the signaling comprises a CKE signal.
4. The memory device of claim 2, wherein the allowed power off state indicates that the logic block is temporarily unused.
5. The memory device of claim 1, wherein the timeout circuit is configured to determine the timeout time based at least in part on a leakage current of the logic block, a switching energy of the local power domain, or a combination thereof.
6. The memory device of claim 5, wherein the timeout comprises a period of time, wherein a total amount of the leakage current within the period of time is approximately equal to the switching energy.
7. The memory device of claim 1, wherein the timeout circuit is configured to send a power down signal to the local power domain after the timeout.
8. The memory device of claim 1, wherein the timeout circuit is configured to maintain the local power domain in a power on state in response to a first signaling of an allowed power off state for a duration of the timeout time.
9. The memory device of claim 8, wherein the timeout circuit is configured to continue to maintain the local power domain in the power on state in response to a second signaling of an allowed power on state occurring temporarily before the timeout time ends.
10. The memory device of claim 1, wherein the memory device is operably coupled to a controller.
11. The memory device of claim 1, wherein the temperature sensor comprises a 4-bit temperature sensor.
12. A semiconductor device, comprising:
logic circuitry configured to process signals in the semiconductor device;
a temperature sensor configured to sense a temperature corresponding to the logic circuit; and
a timeout circuit configured to control a supply of power to the logic circuit based at least in part on the temperature.
13. The semiconductor device of claim 12, wherein the timeout circuit is configured to control power to the logic circuit via a local power domain.
14. The semiconductor device of claim 12, wherein the timeout circuit is configured to delay powering down the logic circuit in response to an indication that the logic circuit is not in use.
15. The semiconductor device of claim 12, wherein the timeout circuit is configured to not switch power down to a logic circuit until a timeout delay ends.
16. The semiconductor device of claim 15, wherein the timeout circuit comprises a resistor-capacitor (RC) circuit.
17. The semiconductor device of claim 16, wherein a capacitance of the RC circuit increases in response to an increase in the temperature, wherein the increase in the capacitance increases the timeout delay.
18. The semiconductor device of claim 12, wherein the temperature sensor and the logic circuit of the semiconductor device are positioned on a die.
19. The semiconductor device according to claim 12, wherein the temperature is an average temperature of the semiconductor device.
20. The semiconductor device of claim 12, wherein the semiconductor device comprises a memory device.
21. A method, comprising:
receiving temperature information corresponding to a logic block of a semiconductor device;
determining a timeout delay of a power down signal based at least in part on the temperature information, wherein the power down signal is configured to turn off power to the logic block; and
delaying power down of the logic block by the timeout delay in response to a signaling that the logic block is not in use.
22. The method of claim 21, comprising maintaining power to the logic block during a timeout delay and not powering down the logic block in response to power on a signal before the timeout delay ends.
23. The method of claim 21, comprising resetting the timeout delay in response to power on a signal.
24. The method of claim 21, comprising turning off power to the logic block after the timeout delay.
25. The method of claim 21, wherein determining the timeout delay comprises weighing leakage energy of the logic block versus switching energy corresponding to turning off power to the logic block.
Technical Field
Embodiments described herein relate generally to the field of semiconductor devices. More specifically, the present embodiments include one or more systems, devices, and methods for setting a power down delay of a local power domain based at least in part on temperature.
Background
This paragraph is intended to introduce the reader to various aspects of art that may be related to various aspects of the present invention, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Various modes of operation in memory devices and other logic circuitry may implement logic circuitry, including various types of circuitry, such as boolean logic gates, to generate certain outputs depending on corresponding inputs. At any point in time, some logic circuits may be in use while other logic circuits are not. However, when not in use, the logic circuit may still consume power (e.g., due to leakage current). A Local Power Domain (LPD) may individually supply power to one or more logic circuits and, as a result, allow individual logic circuits to be powered down when not in use. Switching power to the logic circuit may also consume power, and the rapid cycling of the LPD may result in additional power usage. Accordingly, embodiments described herein may be directed to one or more of the problems set forth above.
Disclosure of Invention
In one aspect, the present disclosure provides a memory device comprising: a local power domain configured to selectively provide power to or prevent power from logic blocks of the memory device; a temperature sensor positioned on the memory device; and a timeout circuit that delays a power down of the local power domain for a timeout time based at least in part on temperature information from the temperature sensor.
In another aspect, the present invention provides a semiconductor device comprising: logic circuitry configured to process signals in the semiconductor device; a temperature sensor configured to sense a temperature corresponding to the logic circuit; and a timeout circuit configured to control a supply of power to the logic circuit based at least in part on the temperature.
In yet another aspect, the invention provides a method comprising: receiving temperature information corresponding to a logic block of a semiconductor device; determining a timeout delay of a power down signal based at least in part on the temperature information, wherein the power down signal is configured to turn off power to the logic block; and delaying power down of the logic block by the timeout delay in response to a signaling that the logic block is not in use.
Drawings
FIG. 1 is a block diagram illustrating a computer system according to an embodiment of the present invention;
FIG. 2 is a block diagram illustrating an example memory device, according to an embodiment of the invention;
FIG. 3 is a schematic diagram of an example power control circuit, according to an embodiment of the invention;
FIG. 4 is a graph of energy usage versus timeout time according to an embodiment of the present invention;
FIG. 5 is an illustration of an example timing diagram for a high temperature scene and a low temperature scene, according to an embodiment of the disclosure;
FIG. 6 is a schematic diagram of an example timeout circuit according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of example logic to output temperature information; and
FIG. 8 is a flow diagram of an example method for delaying power down of a logic block in accordance with an embodiment of the present invention.
Detailed Description
One or more specific embodiments will be described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design and fabrication for those of ordinary skill having the benefit of this disclosure.
To help reduce power consumption due to leakage current, in some embodiments, a clock enable signal (e.g., CKE) or other notification signal provides a notification to a Local Power Domain (LPD) of when power to logic circuits may be turned off and when power is requested to be turned on. The CKE signal may or may not be periodic and, as such, the requested power may not be predictable by the LPD. Thus, it may be advantageous to delay the powering down of the logic circuit to prevent rapid cycling of the LPD to reduce overall power consumption. The ideal delay time may correspond to the amount of leakage current consumed when the logic circuit is not in use and the amount of energy used to switch the LPD. Furthermore, logic circuits may have higher leakage currents at higher temperatures than at relatively cooler temperatures. Thus, the power down delay may be based at least in part on the temperature of the logic circuit, which may be measured by an on-die temperature sensor (e.g., positioned on the same silicon substrate, chip, and/or circuit board as the logic circuit). Further, in some embodiments, the output of the timeout circuit may directly control power to the logic circuit without using a local power domain.
Referring now to FIG. 1, illustrating a simplified block diagram of a computer system 10, the computer system 10 may include one or more LPDs for supplying power to logic circuits. The computer system 10 includes a controller 11 and a semiconductor device 12. The controller 11 may include processing circuitry, such as one or more processors 13 (e.g., one or more microprocessors), which may execute software programs to provide various signals to the semiconductor device 12 via one or more bidirectional communication buses 14 to facilitate data transmission and reception. Further, processor 13 may include multiple microprocessors, one or more "general purpose" microprocessors, one or more special purpose microprocessors, and/or one or more Application Specific Integrated Circuits (ASICs), or some combination thereof. For example, the processor 13 may include one or more Reduced Instruction Set (RISC) processors.
The processor 13 may be coupled to one or more memories 15, which may store information such as control logic and/or software, look-up tables, configuration data, and the like. In some embodiments, processor 13 and/or processor 15 may be external to controller 11. The memory 15 may include a tangible, non-transitory, machine-readable medium, such as volatile memory (e.g., Random Access Memory (RAM)) and/or non-volatile memory (e.g., Read Only Memory (ROM), flash memory, a hard drive, or any other suitable optical, magnetic, or solid-state storage medium, or a combination thereof). The memory 15 may store a variety of information and may be used for various purposes. For example, the memory 15 may store machine-readable and/or processor-executable instructions (e.g., firmware or software) for execution by the processor 13, such as instructions for providing various signals and commands to the semiconductor device 12 to facilitate the transmission and reception of data to be written, read, processed, or relayed by the semiconductor device 12.
The controller 11 may communicate with the semiconductor device 12 through one or more command and input/output (I/O) interfaces 16. In general, the command and input/output interface 16 provides access to various components of the semiconductor device 12 by external devices, such as the controller 11. Clock signals may be passed between semiconductor device 12 and an external device, such as controller 11, to provide for synchronous data transfer and internal use within semiconductor device 12. For example, CKE signal 17 may provide an indication of when to enable and/or disable logic circuitry, such as logic block 18. CKE signal 17 may be communicated to semiconductor device 12 from controller 11, for example, or may be generated by circuitry within semiconductor device 12.
In one embodiment, CKE signal 17 may be used to control the LPD of logic block 18 on semiconductor device 12. Additionally, the timeout circuit 20 may be used to power down the logic block 18 based on the temperature delay. One or more temperature sensors 22 may be positioned on the die or in close proximity to the semiconductor device 12 and may measure the direct temperature of the logic block 18, the ambient temperature, or the overall (e.g., average) temperature of the semiconductor device 12. In one embodiment, a temperature sensor 22 is positioned on the semiconductor device 12 to determine the temperature of the logic block 18. Thus, multiple LPDs of the semiconductor device 12 may each have a timeout circuit 20 depending on the temperature sensor 22 located at the respective logic block 18 of each LPD. Additionally or alternatively, multiple LPDs may use a single timeout circuit 20 and/or multiple timeout circuits 20 may share a common temperature sensor 22.
As should be appreciated, the controller 11 and the semiconductor device 12 may be implemented as separate components or implemented together as a single device. Further, LPD, logic block 18, and timeout circuit 20 may be implemented on any suitable semiconductor device 12. For example, FIG. 2 is a functional block diagram illustrating a memory device 24 as an example semiconductor device 12. In some embodiments, the memory device 24 may be disposed in (physically integrated into or otherwise connected to) or otherwise coupled to the host device. The host device may include any of a desktop computer, a laptop computer, a pager, a cellular telephone, a personal organizer, a portable audio player, control circuitry, a camera, and the like. The host device may also be a network node, such as a router, a server, and/or a client (e.g., one of the computer types previously described). The host device may be some other kind of electronic device, such as a copier, a scanner, a printer, a game console, a television, a set-top box video distribution or recording system, a cable box, a personal digital media player, a factory automation system, an automotive computer system, or a medical device. It should be noted that terms used to describe these various examples of systems, such as other terms used herein, may share some references and, as such, should not be construed narrowly because of the other terms listed.
The host device may thus be a processor-based device, which may include a processor, such as a microprocessor, that controls the processing of system functions and requests in the host device. Further, any host processor may include multiple processors sharing system control. The host processor may be directly or indirectly coupled to additional system elements of the host device such that the host processor controls the operation of the host device by executing instructions that may be stored within or outside of the host device.
In some embodiments, the memory device 24 may include DDR5 (double data rate 5) SDRAM (synchronous dynamic random access memory) integrated on a semiconductor chip, LPDDR4 (low power double data rate 4) type DRAM (dynamic random access memory) integrated on a single semiconductor chip, and the like. However, as should be appreciated, the embodiments discussed herein may be utilized in connection with any suitable type of memory device 24. Each electronic device is provided with a memory device 24 coupled to an external terminal. It should be understood that these external terminals may be bond pads, inputs, pins, terminals, and the like, but are referred to herein as pads for ease of discussion. The memory device 24 may facilitate operations (e.g., read and/or write operations) based at least in part on command/address signals (e.g., CA signals) and/or clock signals (e.g., Clk and ClkF).
The CA and clock signals may be supplied to CA pads 25 and clock pads 26 of the electronic device, for example, via a CA bus and clock bus or any suitable communicative coupling from the controller 11 or host processor. The CA signal and the external clock signal may be supplied to the memory device 24 or generated on-board, thereby facilitating an access operation with respect to the memory cell array included in the memory device 24. In addition, the memory devices 24 may receive additional signals from the controller, such as Chip Select (CS) signals, and these signals may be individually supplied to one or more memory devices 24 of the electronic device. As depicted, the memory device 24 may receive a chip select signal at the chip select pad 27. The chip select signal may enable the memory device 24 for memory operations.
Memory device Data (DQ) may be read from or written to the memory device 24 at a data (e.g., DQ) pad 28 via a communicative coupling. In some embodiments, the memory device 24 may not permit both read and write operations, such as in the case of Read Only Memory (ROM) based electronic devices.
Memory device 24 may include one or more arrays 29 of memory cells (e.g., memory BANKs BANK-0 through BANK-7), each of which may include a Word Line (WL) and a bit line (BL, inverse BL as BLB), respectively. The row decoder/driver 30 may select a word line, while the column decoder/driver 31 may select a bit line. The bit lines may be paired and may be coupled to sense amplifiers 32(SA) of the memory cell array 29. The sense amplifier 32 may amplify a voltage difference generated between the bit lines BL and BLB. Sense amplifier 32 may also supply read data to a complementary local input/output line (LIOT/B) based at least in part on a voltage difference generated between bit lines BL and BLB, where the local input/output line may represent a pair of lines (e.g., normal and inverted lines). The read data supplied to the local input/output line may be transferred to a complementary main input/output line (MIOT/B) via a switching circuit (TG) 34. The read data on the main input/output lines may be converted to single-ended signals and transmitted to the data input/output circuit 36 via a read/write amplifier 38(RW AMP), the read/write amplifier 38 used to translate electrical signal values (e.g., voltage levels) between values that may be interpreted at the pad and values that may be interpreted by the internal memory cell array 29.
As previously described, the memory device 24 may include a CA pad 25, a clock pad 26, a data pad 28, and one or more chip select pads 27. Memory device 24 may also include a voltage pad 40 that receives a first amount of voltage and a voltage pad 42 that receives a second amount of voltage, e.g., corresponding to logic high and low voltage values (e.g., VDD and VSS), respectively. The CA signal is received at the CA pad 25 and may be transmitted to the CA input circuit 44. Memory device 24 may include any suitable number of CA pads 25, and as depicted, memory device 24 includes m number of CA pads 25.
As previously described, the CA signals may include address signals and command signals. The address signals may be transmitted to an address decoder 46 and the command signals may be transmitted to a command decoder 48. The address decoder 46 may supply a row address to the row decoder/driver 30 and may supply a column address to the column decoder/driver 31. The command decoder 48 may generate an internal command by decoding the command signal, and may transmit the internal command to the internal control signal generator 50. For example, the command decoder 48 may generate valid signals, read signals, write signals, and the like for transmission to the internal control signal generator 50. In response to the output from the command decoder 48, the internal control signal generator 50 may enable and/or disable various control signals to operate memory device 24 circuitry, such as mode registers, delay circuits, reset control circuits, column decoder/driver 31, and row decoder/driver 30, and the like, to perform operations according to internal commands, such as reset operations, read operations, and/or write operations. For example, in response to an activate command, the command decoder 48 and internal control signal generator 50 may be operable to enable a wordline in response to a row address transmitted to the memory device 24. CA input circuit 44, address decoder 46, command decoder 48, column decoder/driver 31, and row decoder/driver 30 may constitute CA control circuitry and may access memory cell array 29.
The clock signal may be transmitted to the memory device 24 at the clock pad 26. The external clock signal Clk and the external clock signal ClkF may be complementary signals (e.g., ClkF is the inverse of Clk), and both may be supplied to a clock input circuit and/or an internal clock generator, referred to herein as clock input circuit 52. Clock input circuitry 52 may generate one or more internal clock signals, such as latch timing signals that are used as timing signals to define the operation of one or more latch circuits of memory device 24. Clock input circuit 52 may also generate various other timing signals, such as phase controller internal clock signals.
Voltage pads 40 and 42 may receive power supply potentials of a system high Voltage (VDD) and a system low Voltage (VSS). The power supply potential may be supplied to the power circuit 56. The power circuitry 56 may generate various internal potentials based at least in part on the power supply potential. Internal potentials can be transmitted to the row decoder 30, sense amplifiers 32, and the like to facilitate operation of the memory device 24. Further, the voltage pads 40 and 42 may be operably coupled to a power-on detector to determine whether an electrical signal (e.g., current) is flowing at the voltage pads 40 and/or 42. In response to this determination, the memory device 24 may change operation, e.g., may be used to reset its own circuitry in preparation for the next memory operation.
In addition, the chip select pad 27 may receive a chip select signal to activate a memory operation of the memory device 24. The chip select signal is transmitted from the chip select pad 27 to the chip select input circuit 58. The chip select input circuit 58 includes a plurality of circuits to enable the CA input circuit 44 to permit the CA signal to be transmitted into the memory device 24.
As should be appreciated, various other components (e.g., power supply circuitry, mode registers, read/write amplifiers, etc.) may also be incorporated into the memory device 24. Moreover, the timeout circuit 20 and the temperature sensor 22 of the disclosed techniques may be used in conjunction with any suitable logic block 18 of various components within the memory device 24 or another semiconductor device 12. It should be understood, therefore, that the block diagram of FIG. 2 is provided to emphasize certain functional features of the memory device 24 as an example semiconductor device 12, and is not limiting.
In further illustration, FIG. 3 is a schematic diagram of a power control circuit 60 utilizing an LPD 62. The incoming CKE signal 17 may provide an indication of when to allow power to the logic block 18 to be turned off (e.g., LPD is not currently in use) and when to request power be turned on. As noted above, CKE signal 17 may or may not be periodic and, as such, the power requested may not be predictable. Although unpredictable, in some embodiments there may be little room in the timing of powering up the logic block 18. In other words, LPD62 may cycle to or remain in a power on state when power is requested to logic block 18 regardless of the previous state of LPD62 or timeout circuit 20. When CKE signal 17 notifies the timeout circuit that it is possible to shut down logic block 18 (e.g., logic block 18 is not currently in use), timeout circuit 20 may delay the powering down of logic block 18 to prevent rapid cycling of LPD62 in this case where it is requested to logic block 18 quite quickly after the notification of power down CKE signal 17. For example, LPD62 may not cycle power to logic block 18 if the latter power call following power down CKE signal 17 is less than the timeout delay. Preventing rapid cycling of the LPD62 may reduce overall power consumption by inducing leakage currents in shorter durations (rather than the greater energy costs associated with switching the LPD 62).
The optimal delay may take into account the amount of leakage current consumed when the logic circuit is not in use and the amount of energy used to switch the LPD 62. Depending on the temperature of the logic block 18, for example, as measured by the temperature sensor 22, the optimal delay may vary. In response to CKE signal 17 and the temperature sensor input, timeout circuit 20 may output a power down signal 64 to LPD62 to turn off power to logic block 18 and stop or reduce current leakage. As should be appreciated, although logic block 18 is depicted as a group of boolean logic gates, logic block 18 may be any suitable circuit where it may be desirable to power down logic block 18 to prevent current leakage, for example, via LPD 62.
As described above, the leakage current of the logic block 18 may depend on the temperature of the logic block 18. FIG. 4 is a graph 66 of normalized energy usage on the y-axis 68 and normalized timeout time on the x-axis 70. As depicted by graph 66, the leakage energy at a high temperature (e.g., 90 degrees celsius (C)) 72 is greater than the leakage energy at a low temperature (e.g., 25C)74 over the course of a given timeout. Although shown as constant leakage energy (e.g., linear energy usage over time), the leakage energy may be represented by different characteristic curves (e.g., polynomial, exponential, logarithmic, etc.), depending on the implementation. Additionally, the LPD handover energy 76 amortized over the course of the timeout may decrease with larger timeout delays due to the substantially fixed energy costs associated with handing over the LPD 62. The maximum total energy for a particular timeout at a given temperature is the sum of the LPD switching energy 76 and the leakage energy 72, 74 for the LPD for the given temperature. Although this is the maximum total energy, as described above, if CKE signal 17 invokes the power on state of logic block 18 before the end of the timeout, less energy may be used, thereby not switching LPD 62. The minimum value of the total high temperature energy 78 produces an optimal timeout for the high temperature condition and the minimum value of the total low temperature energy 80 produces an optimal timeout for the low temperature condition. This minimum value may also correspond to a timeout where the accumulated leakage energy is equal to the amortized LPD switching energy 76.
To help illustrate the implementation of the optimal timeout, fig. 5 shows a high temperature timing diagram 82 and a low temperature timing diagram 84. In some embodiments, when CKE signal 17 indicates a logic high, power may be requested to logic block 18. Conversely, LPD62 may be turned off (e.g., logic block 18 is not in use) when CKE signal 17 indicates a logic low. Additionally, a logic high of power down signal 64 may turn off power to LPD 62. For illustrative purposes, the complement of CKE signal 17, CKE x signal 85, is used to help exhibit a timeout delay. As should be appreciated, a logic high or low may be used depending on the implementation to indicate a power on state, and/or a complementary signal may be used to indicate a desired state of LPD 62. The power down signal 64 from the timeout circuit 20 has a delayed logic high in response to CKE x signal 85. For purposes of example, the high temperature timeout 86 is set to 1 microsecond (μ s). Although the example depicts a high temperature scenario of 1 μ s, the timeout delay may be any length of time depending on the implementation (e.g., logic block leakage current, LPD switching energy) and the temperature of the logic block 18. Thus, the timeout delay may be on the order of nanoseconds, microseconds, milliseconds, seconds, or the like. In the high temperature case, segments of CKE signal 85 that go to logic high for less than the high temperature timeout 86 (e.g., 500 nanoseconds) are ignored. However, if CKE x signal 85 is at logic high for more than high temperature timeout 86, power down signal 64 may go to logic high after the timeout period and indicate LPD62 to turn off power to logic block 18.
Similar to the high temperature timing diagram 82, the low temperature timing diagram 84 depicts the power down signal 64 from the timeout circuit 20 in response to CKE signal 85. In low temperature situations, the logic block 18 may leak less current than in high temperature situations. Thus, the low temperature timeout 88 may be a longer period of time (e.g., 3 μ s) than the high temperature timeout 86. Overall, the energy savings due to the reduced cycling of LPD62 outweighs the leakage current incurred during the timeout delay.
As described above, CKE signal 17 may be unpredictable. However, if CKE signal 17 is predictable, e.g., periodic, energy savings may be further increased. In this case, LPD62 may be switched to the off state immediately or at a time less than the corresponding timeout if the predicted length of logic high of CKE signal 85 (e.g., the length of time that logic block 18 is not in use and may shut down) is greater than the timeout delay at the given temperature. If the predicted length of CKE at logic high signal 85 is less than the timeout delay, power down signal 64 remains at logic low to prevent LPD62 from toggling.
Fig. 6 is an example of a timeout circuit 20 that calculates a timeout delay based on the temperature of the logic block 18 using a resistor-capacitor (RC) circuit 90. In the illustrated example, CKE signal 17 is inverted to CKE signal 85 to charge one or more capacitors when CKE signal 17 indicates that power may shut off power from logic block 18 (e.g., logic low). The RC circuit 90 may have an increased or decreased capacitance depending on the temperature sensed by the temperature sensor 22, and thus, take a shorter or longer amount of time to trigger the power down signal 64. For example, at colder temperatures, more capacitors 92 may be connected to the RC circuit 90 in response to the input 94 from the temperature sensor 22. The additional capacitor increases the capacitance and charging time of the RC circuit 90, increasing the timeout delay. Conversely, the capacitance of the RC circuit 90 may be reduced at hotter temperatures. When CKE signal 17 requests power to logic block 18 (e.g., a logic high CKE signal 17), RC circuit 90 may be grounded, resetting the timeout delay for the next CKE signal event.
In further illustration of the example timeout circuit 20, FIG. 7 is a temperature table 96 and example logic 98 for the output of the temperature sensor 22 (e.g., T <3:0>) and the input 94 to the RC circuit 90 (e.g., TRANGE <3:0 >). In the depicted example, the temperature sensor output is a 4-bit indication representing a temperature from approximately-38C to 217C. Example logic 98 is shown only as an example and thus is non-limiting. Example logic 98 may be incorporated into timeout circuit 20, temperature sensor 22, or anywhere on semiconductor device 12. In some embodiments, the output of the temperature sensor 22 may be directly connected to the timeout circuit 20 as input 94.
As should be appreciated, any suitable temperature sensor 22 that outputs a characteristic value of the temperature of the logic block 18 may be used. For example, in some embodiments, the temperature sensor may be a 1-bit threshold temperature sensor. At temperatures above the threshold, a longer timeout delay may be used relative to the timeout delay corresponding to temperatures below the threshold. The fidelity of the temperature sensor 22 may use any number of bits (e.g., 1, 2, 4, 8, etc.) depending on the implementation and the desired accuracy of the timeout delay. Likewise, although shown using four capacitors 92, the RC circuit 90 may include any number of capacitors depending on the implementation and/or desired accuracy.
The example timeout circuit 20 and the example logic 98 depicted by the RC circuit 90 are given by way of example only and are not limiting. Timeout circuit 20 may be any suitable circuit for generating a timeout delay for LPD62 based on temperature. Other examples of timeout circuits may include analog circuits, digital logic, multiplexers, one or more counters, calculations in software, or combinations thereof.
Fig. 8 is a flow diagram 100 of an example process for applying an optimal timeout delay to LPD62 of logic block 18. Timeout circuit 20 may receive CKE signal 17, allowing power down of logic block 18 (process block 102). The timeout circuit 20 may also receive temperature information corresponding to the logic block 18 (process block 104). An optimal timeout delay may be determined based at least in part on the temperature information (process block 106). Then, an optimal timeout delay may be implemented to delay power down of LPD62 (process block 108). If CKE signal 17 does not request power to logic block 18 before the timeout delay ends, a power down signal 64 may be sent to LPD62 to shut down power to logic block 18 until CKE signal 17 requests power to be restored to logic block 18 (process block 110). If CKE signal 17 requests power to logic block 18 before the timeout delay ends, power to logic block 18 may be maintained (process block 112). The timeout delay may be reset for the next power down availability and/or temperature change (process block 114). As should be appreciated, although the flowchart 100 is depicted in a particular order, in certain embodiments, steps may be recorded, altered, deleted, repeated, and/or occur concurrently.
While the current technology may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. It should be understood, however, that the current technology is not intended to be limited to the particular forms disclosed. Rather, the present embodiments are intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present technology as defined by the following appended claims.
The techniques presented and claimed herein are cited and applied to material objects and specific examples that clearly improve the practical nature of the art and are thus not abstract, intangible, or purely theoretical. Furthermore, if any claim appended to the end of this specification contains one or more elements labeled as "means for performing ] [ function ] … …" or "step for performing ] [ function ] … …", it is intended that such elements be interpreted in accordance with 35U.S. C.112 (f). However, for any claim containing elements identified in any other way, it is intended that such elements not be interpreted according to 35u.s.c.112 (f).
