阅读说明：本技术 具有增强浮置栅极的闪速存储器结构及其形成方法
(Flash memory structure with enhanced floating gate and method of forming the same
) 是由 黄宏书
刘铭棋 于 2019-06-20 设计创作，主要内容包括：在一些实施例中,本公开涉及闪速存储器结构。闪速存储器结构具有设置在衬底内的源极区和漏极区。选择栅极在衬底上方设置在源极区和漏极区之间,并且浮置栅极在衬底上方设置在选择栅极和源极区之间。控制栅极设置在浮置栅极上方。浮置栅极的侧壁限定从浮置栅极的下表面向下延伸的突出物以限定浮置栅极底部内的凹槽。本发明的实施例还提供了闪速存储器结构的形成方法。(In some embodiments, the present disclosure relates to flash memory structures. The flash memory structure has a source region and a drain region disposed within a substrate. A select gate is disposed over the substrate between the source and drain regions, and a floating gate is disposed over the substrate between the select gate and the source region. The control gate is disposed over the floating gate. The sidewalls of the floating gate define a protrusion extending downward from the lower surface of the floating gate to define a recess within the bottom of the floating gate. Embodiments of the invention also provide methods of forming flash memory structures.)
1. A flash memory structure, comprising:
a source region and a drain region disposed within the substrate;
a select gate formed over the substrate between the source region and the drain region;
a floating gate disposed over the substrate between the select gate and the source region;
a control gate disposed over the floating gate; and
wherein the floating gate has sidewalls defining a protrusion extending downward from a lower surface of the floating gate to define a recess within a bottom of the floating gate.
2. The flash memory structure of claim 1, further comprising:
a plurality of isolation structures disposed within a trench defined by sidewalls of the substrate, wherein the source region and the drain region are separated along a first direction and the floating gate is disposed between the plurality of isolation structures along a second direction, wherein the second direction is perpendicular to the first direction.
3. The flash memory structure of claim 2, wherein uppermost surfaces of the plurality of isolation structures are higher than a bottom surface of the floating gate and lower than a top surface of the floating gate.
4. The flash memory structure of claim 2, further comprising:
a dielectric layer disposed between the floating gate and the substrate, wherein the dielectric layer is disposed along a sidewall of the substrate.
5. The flash memory structure of claim 4, wherein the dielectric layer extends vertically below a bottom-most surface of the floating gate.
6. The flash memory structure of claim 4, wherein the protrusion is disposed between the dielectric layer and the isolation structure.
7. The flash memory structure of claim 1,
wherein the source region and the drain region are separated by a portion of the substrate that includes a channel region; and
wherein the floating gate surrounds a plurality of surfaces of a portion of the substrate including the channel region.
8. The flash memory structure of claim 1, wherein the protrusion has angled sidewalls to decrease a width of the protrusion as a distance from a lower surface of the floating gate increases.
9. A flash memory structure, comprising:
a source region and a drain region disposed within the substrate and separated by a channel region along a first direction;
a plurality of isolation structures disposed within trenches defined by sidewalls of the substrate, wherein the plurality of isolation structures are separated along a second direction that is perpendicular to the first direction;
a control gate disposed over the channel region; and
a floating gate vertically disposed between the control gate and the channel region and laterally disposed between the plurality of isolation structures, wherein the floating gate extends into a trench defined by sidewalls of the substrate.
10. A method of forming a flash memory structure, comprising:
forming a protective layer over a substrate;
forming a plurality of trenches extending through the protective layer to reach into the substrate;
forming an isolation layer over the protective layer and within the plurality of trenches;
forming a sacrificial mask layer over the isolation layer;
removing portions of the sacrificial mask layer and the isolation layer, wherein a remainder of the sacrificial mask layer has an outermost sidewall that is separated from sidewalls of the protection layer defining the plurality of trenches by the isolation layer;
selectively etching the isolation layer between the sacrificial mask layer and sidewalls of the protection layer to form a recess along edges of the plurality of trenches;
removing the protective layer to define the floating gate recess; and
and forming floating gate materials in the floating gate groove and the pit.
Technical Field
Embodiments of the invention relate generally to the field of semiconductor technology, and more particularly to flash memory structures with enhanced floating gates and methods of forming the same.
Background
Many modern electronic devices contain electronic memory configured to store data. The electronic memory may be either volatile or non-volatile memory. Volatile memory stores data when power is applied, while non-volatile memory is capable of storing data when power is removed. Flash memory is a type of non-volatile memory that can be electrically erased and reprogrammed. The flash memory is widely used in various electronic devices and apparatuses (e.g., consumer electronics, automobiles, etc.).
Disclosure of Invention
According to an aspect of the present invention, there is provided a flash memory structure including: a source region and a drain region disposed within the substrate; a select gate formed over the substrate between the source region and the drain region; a floating gate disposed over the substrate between the select gate and the source region; a control gate disposed over the floating gate; and wherein the floating gate has sidewalls defining a protrusion extending downward from a lower surface of the floating gate to define a recess within a bottom of the floating gate.
According to an aspect of the present invention, there is provided a flash memory structure including: a source region and a drain region disposed within the substrate and separated by a channel region along a first direction; a plurality of isolation structures disposed within trenches defined by sidewalls of the substrate, wherein the plurality of isolation structures are separated along a second direction that is perpendicular to the first direction; a control gate disposed over the channel region; and a floating gate vertically disposed between the control gate and the channel region and laterally disposed between the plurality of isolation structures, wherein the floating gate extends into a trench defined by sidewalls of the substrate.
According to an aspect of the present invention, there is provided a method of forming a flash memory structure, comprising: forming a protective layer over a substrate; forming a plurality of trenches extending through the protective layer to reach into the substrate; forming an isolation layer over the protective layer and within the plurality of trenches; forming a sacrificial mask layer over the isolation layer; removing portions of the sacrificial mask layer and the isolation layer, wherein a remainder of the sacrificial mask layer has an outermost sidewall that is separated from sidewalls of the protection layer defining the plurality of trenches by the isolation layer; selectively etching the isolation layer between the sacrificial mask layer and sidewalls of the protection layer to form a recess along edges of the plurality of trenches; removing the protective layer to define the floating gate recess; and forming a floating gate material within the floating gate recess and the pit.
Drawings
Various aspects of the invention are better understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with industry standard practice, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1A-1B illustrate cross-sectional views of some embodiments of flash memory structures with enhanced floating gates.
Fig. 2A-2C illustrate some additional embodiments of an integrated chip having an embedded flash memory structure with enhanced floating gates.
FIG. 3 illustrates a perspective view of some embodiments of an integrated chip having a flash memory structure including an enhanced floating gate.
Fig. 4-22 illustrate cross-sectional views of some embodiments of methods of forming an integrated chip having an embedded flash memory structure with an enhanced floating gate.
Figure 23 illustrates a flow diagram of some embodiments of a method of forming an integrated chip having an embedded flash memory structure with an enhanced floating gate.
Detailed Description
The present disclosure provides many embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the description that follows, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an accessory feature may be formed between the first and second features such that the first and second features are not in direct contact. Moreover, the present disclosure may repeat reference numerals and/or letters in the various examples. These iterations are for simplicity and clarity and do not in themselves dictate a relationship between the various embodiments and/or configurations discussed.
Also, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another (or other) element or component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Embedded memories are already common in modern integrated chips. Embedded memory is electronic memory located on the same integrated chip die as the logic function (e.g., processor or ASIC). By embedding the memory device and the logic device on the same integrated chip die, the conductive interconnects between the memory device and the logic device can be shortened, thereby reducing power consumption and improving performance of the integrated chip. Flash memory is commonly used in many embedded memory systems due to its non-volatility (i.e., its ability to retain stored data states when power is not supplied), its high density, its fast write speed, and its compatibility with modern CMOS fabrication processes.
Embedded flash memory structures typically include a floating gate disposed between a control gate and a substrate. The floating gate has a planar lower surface separated from the substrate by a dielectric layer. During operation, a channel region is formed in the substrate under the floating gate. Application of a bias voltage to the control gate causes charge carriers to tunnel from the channel region through the dielectric layer into the floating gate. The charge trapped within the floating gate is indicative of the stored data state (e.g., a logic "0" or "1").
However, as the size of flash memory cells is scaled down, the length of the control gate is also reduced and the control gate may begin to experience short channel effects (e.g., leakage induced barrier lowering, velocity saturation, etc.), which may degrade the performance of the flash memory cell. For example, short channel effects may make it more difficult to drive charge carriers into the floating gate (i.e., provide a low coupling ratio for the floating gate), resulting in data programming inefficiencies (e.g., difficulty in driving charge into the floating gate) and/or a smaller read window (i.e., a smaller difference in current output between a stored '0' and a stored '1').
In some embodiments, the present disclosure relates to flash memory structures having enhanced floating gates configured to improve device performance. The flash memory structure includes a source region and a drain region disposed within a substrate. The select gate and the floating gate are disposed above the substrate between the source region and the drain region. The control gate is disposed over the floating gate. The floating gate has sidewalls defining a protrusion extending perpendicularly outward from a lower surface of the floating gate. The overhang causes the floating gate to surround a portion of the substrate forming the channel region, thereby increasing the size of the interface region between the channel region and the floating gate (e.g., an opposing floating gate having a flat lower surface). Increasing the size of the interface region more readily drives charge carriers into the floating gate, thereby improving the data programming efficiency and read window of the disclosed flash memory structure.
Fig. 1A-1B illustrate cross-sectional views 100 and 124 of some embodiments of flash memory structures with enhanced floating gates.
Fig. 1A shows a cross-sectional view 100 of a flash memory structure along a first direction (X-direction) and a second direction (Z-direction). As shown in cross-sectional view 100, the flash memory structure includes a common source region 104 disposed between a first drain region 106a and a second drain region 106b within a substrate 102. The first channel region 108a extends between the common source region 104 and the first drain region 106 a. The second channel region 108b extends between the common source region 104 and the second drain region 106 b.
The flash memory structure also includes a first floating gate 112a, wherein the first floating gate is disposed over the first channel region 108a and is configured to store charge associated with a first data state (e.g., '1' or '0'). The first floating gate 112a is separated from the substrate 102 by a dielectric layer 110 and from the overlying first control gate 114a by one or more additional dielectric materials 120. The first select gate 116a is disposed on a first side of the first floating gate 112 a. The common erase gate 118 is disposed on a second side of the first floating gate 112a opposite the first side. One or more additional dielectric materials 120 laterally separate the first floating gate 112a from both the first select gate 116a and the common erase gate 118.
The second floating gate 112b is disposed over the second channel region 108b and is configured to store charge associated with a second data state. The second floating gate 112b is separated from the underlying substrate 102 by a dielectric layer 110 and from the overlying second control gate 114b by one or more additional dielectric materials 120. The second select gate 116b is disposed on a first side of the second floating gate 112 b. The common erase gate 118 is disposed on a second side of the second floating gate 112b opposite the first side. One or more additional dielectric materials 120 laterally separate the second floating gate 112b from both the second select gate 116b and the common erase gate 118. An interlayer dielectric (ILD) structure may be disposed over the one or more additional dielectric materials 120.
FIG. 1B shows a cross-sectional view 124 of the flash memory structure along section A-A' of FIG. 1A. The cross-sectional view 124 extends along a third direction (Y-direction) and a second direction (Z-direction).
As shown in cross-section 124, a plurality of isolation structures 126 are disposed in trenches within substrate 102. A plurality of isolation structures 126 are disposed on opposite sides of the first floating gate 112 a. The first floating gate 112a extends from between the plurality of isolation structures 126 to directly above the plurality of isolation structures 126. The first floating gate 112a includes a protrusion 128 extending outward (e.g., downward) from the lower surface 112l of the first floating gate 112a to define a recess 113 in the bottom of the floating gate 112 a. The overhang 128 causes the first floating gate 112a to surround multiple surfaces of a portion of the substrate 102 including the first channel region 108 a. The dielectric layer 110 lines the inner surface of the substrate 102 along the interface region between the substrate 102 and the first floating gate 112 a. In some embodiments, the dielectric layer 110 may extend vertically beyond the bottom of the first floating gate 112a by a first non-zero distance 130. The second floating gate (112 b of figure 1A) also has a protrusion extending outward (e.g., downward) from a lower surface of the second floating gate to surround a plurality of surfaces of a portion of the substrate including the second channel region.
Referring again to fig. 1A, to write data to the first floating gate 112a, a voltage may be applied to the first control gate 114a and the first select gate 116 a. This voltage causes first select gate 116a to generate a first electric field, wherein the first electric field drives charge carriers (along line 134) into first channel region 108 a. The voltage also causes the first control gate 114a to generate a second electric field, wherein the second electric field injects charge carriers within the first channel region 108a through the dielectric layer 110 into the first floating gate 112 a. The injected charge carriers change the floating gate threshold voltage to represent a logic '0' state (while the uncharged floating gate represents a "1" state). Erasing data from the first floating gate 112a may be accomplished by applying a negative voltage to the common erase gate 118. The negative voltage drives the stored charge from the first floating gate 112a to the common erase gate 118 (along line 136) by Fowler-Nordheim tunneling.
Once programmed, data may be read from the first floating gate 112a by applying a reference voltage to the first select gate 116a and the first drain region 106a while the common source region 104 is grounded. If the first floating gate 112a is erased (low threshold state), the embedded flash memory cell conducts current and the embedded flash memory cell outputs a logic '1'. However, if the first floating gate 112a is programmed (high threshold state), the embedded flash memory cell is not conductive and the embedded flash memory cell outputs a logic "0".
By surrounding the substrate 102 with the first floating gate 112a, the interface area between the first floating gate 112a and the substrate 102 is increased to be larger than a floating gate having a flat lower surface. By increasing the interface region between the first floating gate 112a and the substrate 102, charge carriers within the first channel region 108a can more easily enter the first floating gate 112a, thereby increasing the amount of charge on the first floating gate 112a and improving writing efficiency. The increased amount of charge on the first floating gate 112a also increases the difference in channel conductive lines between different data states and, therefore, increases the read window of the first floating gate 112 a.
Fig. 2A-2C illustrate some additional embodiments of an integrated chip having an embedded flash memory structure with enhanced floating gates.
Fig. 2A shows a cross-sectional view 200 of an integrated chip along a first direction (X-direction) and a second direction (Z-direction). As shown in cross-sectional view 200, the integrated chip includes a substrate 102 having an embedded memory region 201a and a logic region 201 b. In some embodiments, the substrate 102 may have a recessed surface 102a located within the embedded memory region 201 a. The recessed surface 102a is recessed below the upper surface 102u of the substrate 102 by a non-zero distance d. In some embodiments, the recessed surface 102a is coupled to the upper surface by an angled sidewall. In some embodiments, the isolation structure 202 may be configured along an edge of the recessed surface 102a of the substrate 102.
The embedded memory region 201a includes an embedded flash memory structure 203 having a common source region 104 separated from an overlying common erase gate 118 by a first dielectric layer 204. In some embodiments, the first dielectric layer 204 also extends along sidewalls of the common erase gate 118. The first floating gate 112a and the second floating gate 112b are disposed on opposite sides of the common erase gate 118. The first floating gate 112a is separated from the underlying substrate 102 by a second dielectric layer 206 and from the overlying first control gate 114a by a third dielectric layer 208. The second floating gate 112b is separated from the underlying substrate 102 by a second dielectric layer 206 and from the overlying second control gate 114b by a third dielectric layer 208. The first select gate 116a is disposed on a first side of the first floating gate 112a opposite the common erase gate 118 and the second select gate 116b is disposed on a second side of the second floating gate 112b opposite the common erase gate 118. The first select gate 116a is laterally separated from the first floating gate 112a and the first control gate 114a by a first dielectric layer 204. The second select gate 116b is laterally separated from the second floating gate 112b and the second control gate 114b by the first dielectric layer 204. The first select gate 116a and the second select gate 116b are vertically separated from the substrate 102 by a fourth dielectric layer 210.
First sidewall spacers 212 are disposed along opposing sides of first control gate 114a and second control gate 114 b. First sidewall spacers 212 laterally separate first and second control gates 114a and 114b from common erase gate 118 and from first and second select gates 116a and 116 b. Second sidewall spacers 214 are configured along sidewalls of first select gate 116a and second select gate 116b that face away from common erase gate 118.
Logic region 201b includes transistor device 216 disposed within substrate 102. Transistor device 216 includes a gate electrode 218 disposed above substrate 102 between a source region 222a and a drain region 222 b. The gate electrode 218 is separated from the substrate 102 by a gate dielectric layer 220 comprising one or more dielectric materials. In some embodiments, the gate electrode 218 may include a metal such as aluminum, ruthenium, palladium, hafnium, zirconium, titanium, and the like. In some embodiments, the gate dielectric layer 220 may include a material such as hafnium oxide (HfO)2)、TiO2、HfZrO、Ta2O3、HfSiO4、ZrO2、ZrSiO2And the like. Sidewall spacers 224 are disposed on opposite sides of gate electrode 218 and gate dielectric layer 220.
A first interlayer dielectric (ILD) layer 226 is disposed on the substrate 102 and laterally surrounds the embedded flash memory structure 203 and the transistor device 216. A first ILD layer 228 is disposed above the first ILD layer 226. Conductive contacts 230 extend through the first ILD layer 226 and the second ILD layer 228 to contact the embedded flash memory structure 203 and the transistor device 216. In some embodiments, the first ILD layer 226 may comprise one or more of low pressure Tetraethylorthosilicate (TEOS), silicon-rich oxide (SRO), Plasma Enhanced (PE) oxynitride, PE nitride, and PE-TEOS. In some embodiments, the first ILD layer 228 may comprise one or more of silicon dioxide, SiCOH, fluorosilicate glass, phosphate glass (e.g., borophosphosilicate glass), and the like. In some embodiments, the conductive contacts 230 may include a metal such as tungsten, copper, or the like (e.g., tungsten, aluminum, or the like).
Fig. 2B shows a cross-sectional view 232 extending along the second direction (Z-direction) and along the third direction (Y-direction).
As shown in cross-sectional view 232, a plurality of first isolation structures 126 are disposed within the trenches of the substrate 102 in the embedded memory region 201 a. A plurality of second isolation structures 234 are disposed within the trenches of the substrate 102 in the logic region 201 b. In some embodiments, the plurality of first isolation structures 126 and the plurality of second isolation structures 234 may each comprise a shallow trench isolation structure having one or more dielectric materials disposed within a trench of the substrate 102.
The first control gate 114a continuously extends over the plurality of floating gates 112a, 112c, and 112 d. The plurality of floating gates 112a, 112c, and 112d include protrusions 128 extending outwardly (e.g., downwardly) from the lower surfaces 112l of the plurality of floating gates 112a, 112c, and 112d, respectively. The protrusions 128 are disposed along outer sidewalls of the plurality of floating gates 112a, 112c, and 112d, respectively. Outer sidewalls of the plurality of floating gates 112a, 112c, and 112d are separated by the plurality of first isolation structures 126 and by the second dielectric layer 206. The second dielectric layer 206 also separates the plurality of floating gates 112a, 112c, and 112d from the first control gate 114 a. In some embodiments, the remainder of the floating gate material 236 may be disposed along a sidewall of the substrate 102 between the embedded memory region 201a and the logic region 201 b.
FIG. 2C shows a top view 238 of the integrated chip showing section A-A 'of FIG. 2A and section B-B' of FIG. 2B. The top view 238 extends along a first direction (X-direction) and a third direction (Y-direction).
FIG. 3 illustrates a perspective view of some embodiments of an integrated chip 300 having a flash memory structure including an enhanced floating gate.
The integrated chip 300 includes a plurality of isolation structures 126 disposed within trenches located at the upper surface 102u of the substrate 102. The trench is defined by angled sidewalls 102s of the substrate 102, wherein the angled sidewalls 102s cause the width of the trench to decrease with increasing distance from the upper surface 102u of the substrate 102.
The first dielectric layer 204 extends along the sidewalls 102s and the horizontally extending surface 102h of the substrate 102. The first dielectric layer 204 may include an oxide (e.g., silicon oxide), a nitride (e.g., silicon oxynitride), and the like. In some embodiments, the first dielectric layer 204 may protrude beyond the sidewalls 102s of the substrate 102 defining the trench by a first non-zero distance 302. In some embodiments, a horizontally extending section of the first dielectric layer 204 disposed along the horizontally extending surface 102h of the substrate 102 may have a first thickness t1Wherein the first thickness is different from a second thickness t provided along a vertically extending section of the sidewall 102s of the substrate 1022。
The floating gate 112 is disposed over the first dielectric layer 204 and between the plurality of isolation structures 126. The floating gate 112 extends laterally from directly above the horizontally extending surface 102h of the substrate 102 to directly above the plurality of isolation structures 126. In some embodiments, the floating gate 112 may extend laterally a second non-zero distance 304 over one of the plurality of isolation structures 126. In some embodiments, second non-zero distance 304 may be in a range between about 30 angstroms and about 100 angstroms. In some embodiments, the plurality of isolation structures 126 have an uppermost surface 126u recessed below the upper surface 112u of the floating gate 112.
The floating gate 112 includes a protrusion 128 from the lower surface of the floating gate 112112l project outwardly (e.g., downwardly) into the groove. The protrusions 128 result in the floating gate 112 having a first height 306 along an outer sidewall of the floating gate 112 and having a second height 308 between the plurality of protrusions 128. The first height 306 is greater than the second height 308. In some embodiments, the difference between first height 306 and second height 308 is in a range between about 50 angstroms and about 150 angstroms. In some embodiments, the protrusion 128 is defined by angled sidewalls, thereby decreasing the width of the protrusion 128 as the distance from the lower surface 112l of the floating gate 112 increases. In some embodiments, the opposing sidewalls of the protrusion 128 may have different sidewall angles. For example, in some embodiments, the protrusion 128 is defined by a first sidewall and an opposing second sidewall, wherein the first sidewall is oriented at a first acute angle θ relative to a horizontal plane extending along a bottommost surface of the floating gate 1121And the opposing second side wall is oriented at a second acute angle θ relative to horizontal2Wherein the second acute angle is different from the first acute angle theta1。
Fig. 4-22 illustrate cross-sectional views 400-2200 of some embodiments of methods of forming an integrated chip having an embedded flash memory structure with an enhanced floating gate. Although fig. 4-22 are described as being method-dependent, it should be understood that the structures disclosed in fig. 4-22 are not limited to such methods, but instead may exist independently as method-independent structures.
As shown in cross-sectional view 400 of fig. 4, a substrate 102 is provided. In various embodiments, substrate 102 may include any type of semiconductor body (e.g., silicon/CMOS block, SiGe, SOI, etc.), such as a semiconductor wafer or one or more dies on a wafer, as well as any other type of semiconductor and/or epitaxial layers formed thereon and/or otherwise associated therewith. The substrate 102 has an embedded memory area 201a and a logic area 201 b. In some embodiments, the embedded memory region 201a of the substrate 102 may have a recessed surface 102a that is recessed a distance d below the upper surface 102u of the substrate 102. For example, the distance d may be about 10-1000 angstroms, about 10-500 angstroms, about 500-1000 angstroms, about 250-350 angstroms, or some other suitable recessed range.
In some embodiments, the substrate 102 may be recessed by forming a first masking layer 402 over the logic region 201b and subjecting the embedded memory region 201 to a thermal oxidation process that forms an oxide within the embedded memory region 201 a. The thermal oxidation process will consume a portion of the substrate 102 within the embedded memory region 201a, thereby recessing the surface of the substrate 102 within the embedded memory region 201 a. The oxide within the embedded memory region 201a is subsequently removed, resulting in a recessed surface 102a of the substrate 102. In an alternative embodiment, the substrate 102 within the embedded memory region 201a is recessed by: a first mask layer 402 is formed over the logic region 201b and the substrate 102 is subsequently etched in the regions not covered by the first mask layer.
As shown in the cross-sectional view 500 of fig. 5, a padding dielectric layer 502 is formed over the substrate 102 and a first protective layer 504 is formed over the padding dielectric layer 502. A plurality of first trenches 506 are formed and extend through the first protective layer 504 and the padding dielectric layer 502 to reach into the substrate 102. In some embodiments, the plurality of first trenches 506 may be formed by selectively exposing the first protective layer 504, the liner dielectric layer 502, and the substrate 102 to the first etchant 508 according to the second mask layer 510.
As shown in cross-sectional view 600 of fig. 6, the plurality of first trenches 506 are filled with a first isolation layer 602 comprising one or more dielectric materials. In some embodiments, the first isolation layer 602 may be formed by a deposition process to fill the plurality of first trenches 506 and extend above the uppermost surface of the first protection layer 504. A first planarization process (e.g., a chemical mechanical planarization process) may then be performed (along line 604) to remove the first isolation layer 602 from over the uppermost surface of the first protection layer 504 and to define a plurality of isolation structures 234. In some embodiments, the first isolation layer 602 may include an oxide (e.g., silicon oxide), a nitride, and the like. In some embodiments, the first protective layer 504 may be removed after the first planarization process is completed.
As shown in the cross-sectional view 700 of fig. 7, a second protective layer 702 is formed over the substrate 102. A second protective layer 702 is disposed over the padding dielectric layer 502 and the plurality of isolation structures 234. A plurality of second trenches 704 are formed and extend through the second protective layer 702 and the padding dielectric layer 502 to reach into the substrate 102. In some embodiments, a plurality of second trenches 704 are formed by selectively exposing the second protective layer 702, the liner dielectric layer 502, and the substrate 102 to a second etchant 706 according to the third mask layer 708.
As shown in the cross-sectional view of fig. 8, a second isolation layer 802 is formed to line the uppermost surfaces of the plurality of second trenches 704 and the second protection layer 702. The second insulating layer 802 defines divot shaped segments (divot)804 disposed within an upper surface of the second insulating layer 802. The turf-shaped segments 804 are positioned directly above the plurality of second grooves 704. In some embodiments, the turf-shaped segments 804 can extend to a position vertically below the uppermost surface of the second protective layer 702 (i.e., such that a horizontal line extending along the bottom of the turf-shaped segments 804 intersects the sidewalls of the second protective layer 702). In some embodiments, the second isolation layer 802 may comprise an oxide or a nitride. For example, the second isolation layer 802 may include silicon dioxide, silicon nitride, or the like. In various embodiments, second isolation layer 802 may be formed by way of a deposition process (e.g., PVD, CVD, PE-CVD, ALD, etc.).
As shown in cross-sectional view 900 of fig. 9, a sacrificial mask layer 902 is formed over the second isolation layer 802. Sacrificial mask layer 902 is disposed over second isolation layer 802 and within divot-shaped segments 804. In some embodiments, sacrificial mask layer 902 may comprise polysilicon. In other embodiments, the sacrificial mask layer 902 may comprise a different material (e.g., titanium, tantalum, etc.) having a high etch selectivity relative to the second isolation layer 802. In some embodiments, sacrificial mask layer 902 may be formed by way of a deposition process (e.g., PVD, CVD, PE-CVD, ALD, etc.).
As shown in cross-sectional view 1000 of fig. 10, portions of the sacrificial mask layer 902 and the second isolation layer 802 are removed. Removing portions of the sacrificial mask layer 902 and the second isolation layer 802 results in a remainder of the sacrificial mask layer 1002 having outermost sidewalls separated from sidewalls of the second protection layer 702 defining the plurality of second trenches 704 by the second isolation layer 802. In some embodiments, portions of the sacrificial mask layer 902 and the second isolation layer 802 may be removed by exposing the sacrificial mask layer 902 and the second isolation layer 802 to a third etchant. The third etchant reduces the thickness of the sacrificial mask layer 902 and the second isolation layer 802. In other embodiments, portions of the sacrificial mask layer 902 and the second isolation layer 802 may be removed by a second planarization process (e.g., a Chemical Mechanical Planarization (CMP) process) performed along the line 1004.
As shown in cross-sectional view 1100 of fig. 11, second isolation layer 802 between the remainder of sacrificial mask layer 904 and the sidewalls of second protection layer 702 is selectively removed, wherein the second protection layer defines a plurality of second trenches 704. Selectively removing the second isolation layer 802 forms a pit along the edges of the plurality of second trenches 704. The pits 1104 extend through the second protective layer 702 and the padding dielectric layer 502 along the edges of the plurality of second trenches 704 to a position between the substrate 102 and the sidewalls of the second isolation layer 802. In some embodiments, the second isolation layer 802 is selectively removed by exposing the second isolation layer 802 to a fourth etchant 1102 while using the sacrificial mask layer 904 as a mask. The sacrificial mask layer 904 will prevent the fourth etchant 1102 from etching the isolation layer 802 below the sacrificial mask layer 904 while allowing the second isolation layer 802 to be removed along the edges of the plurality of second trenches 704.
As shown in cross-sectional view 1200 of fig. 12, an etch-back process may be performed to remove sacrificial mask layer 904. In some embodiments, an etch back process may be performed using the fourth mask layer 1202. In such embodiments, the unmasked portions of the second protective layer 702 and the second isolation layer 802 may also be etched back such that the uppermost surfaces of the second protective layer 702 and the second isolation layer 802 within the embedded memory region 201a are lower than the uppermost surface of the second protective layer 702 within the embedded logic region 201 b.
A dielectric is also formed along exposed sidewalls of the substrate 102 defining a plurality of second trenches 704 to form the first dielectric layer 204. The formation of the dielectric results in the first dielectric layer 204 having a protrusion 205 extending outwardly (e.g., downwardly) from the lower surface 204l of the first dielectric layer 204. In some embodiments, the dielectric may be formed by a thermal oxidation process, forming the dielectric along exposed sidewalls of the substrate 102. In some such embodiments, first dielectric layer 204 may extend vertically across dimple 1104 by a first non-zero distance (not shown). In other embodiments, the dielectric may be formed by a deposition process.
As shown in the cross-sectional view 1300 of fig. 13, the second protective layer 702 is removed from within the embedded memory region 201 a. In some embodiments, the second protective layer 702 may be removed by: a fifth mask layer 1302 is formed over the logic region 201b followed by an etching process that exposes the second protective layer 702 to a fifth etchant 1304 that has a high etch selectivity with respect to the first isolation layer 802. In some embodiments, the fifth masking layer 1302 may be the same layer as the fourth masking layer 1202. Removal of the second protective layer 702 from within the embedded memory region 201a defines a floating gate recess 1306 between sidewalls of the second isolation layer 802. The pit 1104 extends outwardly from the floating gate groove 1306 to between the second isolation layer 802 and the substrate 102.
As shown in cross-section 1400 of fig. 14, a floating gate material 1402 is formed within the floating gate recess 1306. In some embodiments, the floating gate material 1402 may include doped polysilicon. In some embodiments, the floating gate material 1402 may be formed by a deposition process. In some embodiments, after the formation of the floating gate material 1402 is completed, a third planarization process (e.g., a chemical mechanical planarization process) may be performed along the line 1404. The third planarization process forms a substantially planarized plane along the top of the floating gate material 1402 and the second isolation layer 802.
As shown in the cross-sectional view 1500 of fig. 15, the floating gate material (1402 of fig. 14) is exposed to a sixth etchant 1502 to etch back the floating gate material to define a plurality of floating gates 112. In some embodiments, the etch-back process leaves a remainder of the floating gate material 236 along the sidewalls of the substrate 102 between the embedded memory region 201a and the logic region 201 b. In some embodiments, the second isolation layer (802 of fig. 4) may also be etched back (e.g., using a different etchant) to define a plurality of isolation structures 126 having an uppermost surface recessed below the top surfaces of the plurality of floating gates 112.
As shown in cross-section 1600 of fig. 16A and cross-section 1606 of fig. 16B, the remainder of the embedded flash memory structure 1602 is formed over the substrate 102. A cross-sectional view 1600 is shown in a first direction (Y-direction) and a second direction (Z-direction). A cross-sectional view 1600 along the section a-a' of fig. 16A is shown in the third direction (X direction) and the second direction (Z direction).
In some embodiments, the embedded flash memory structure 1602 may be formed by: a second dielectric layer 206 is formed over the plurality of floating gates 112, a control gate layer is formed over the second dielectric layer 206, and a first patterned hard mask 1604 is formed over the control gate layer. The control gate layer and the second dielectric layer 206 are then etched according to the first patterned hard mask 1604 to define a first control gate 114a and a second control gate 114b over the second dielectric layer 206. A first implantation process may then be performed to form the common source region 104 within the substrate 102.
First sidewall spacers 212 are formed along sidewalls of the first and second control gates 114a and 114 b. The plurality of floating gates 112 are then etched to separate the floating gates along a first direction (X-direction). For example, a first floating gate of the plurality of floating gates 112 is etched to form a first floating gate 112a and a second floating gate 112 b. The first dielectric layer 204 is formed along sidewalls of the first sidewall spacers 212, the first floating gate 112a, and the second floating gate 112 b.
A conductive layer (e.g., doped polysilicon) is then formed over the substrate 102 within the embedded memory region 201 a. A second hard mask layer 1608 is formed over the conductive layer and the conductive layer is selectively etched to define a first select gate 116a along a sidewall of the first floating gate 112a, a second select gate 116b along a sidewall of the second floating gate 112b, and a common erase gate 118 between the first floating gate 112a and the second floating gate 112 b. Second sidewall spacers 214 are then formed along the sidewalls of the first select gate 116a facing away from the first floating gate 112a and along the sidewalls of the second select gate 116b facing away from the second floating gate 112 b. A second implantation process may then be performed to form the first drain region 106a and the second drain region 106b within the substrate 102.
As shown in cross-sectional view 1700 of fig. 17, a sixth mask layer 1702 is formed over the embedded memory region 201 of the substrate 102. The second protective layer (702 of fig. 16B) and the liner dielectric layer (602 of fig. 16B) are then removed from within the logic region 201B. After removing the second protective layer and the liner dielectric layer, a gate dielectric layer 1704 and a sacrificial gate layer 1706 are formed over the logic region 201b of the substrate 102. In some embodiments, the gate dielectric layer 1704 may comprise one or more dielectric materials with high-k dielectric materials and the sacrificial gate layer 1706 may comprise polysilicon.
As shown in cross-section 1800 of fig. 18, the gate dielectric layer (1704 of fig. 17) and the sacrificial gate layer (1706 of fig. 17) are patterned to define dummy gate structures 1802 within logic regions 201 b. The dummy gate structure 1802 includes a dummy gate electrode 1804 located over the gate dielectric layer 220 having one or more dielectric materials. In some embodiments, the gate dielectric layer (1704 of fig. 17) and the sacrificial gate layer (1706 of fig. 17) may be patterned according to a seventh mask layer (not shown) formed over the sacrificial gate layer by selectively exposing the gate dielectric layer (1704 of fig. 17) and the sacrificial gate layer (1706 of fig. 17) to a seventh etchant.
In some embodiments, sidewall spacers 224 may be formed along sidewalls of the dummy gate structures 1802. In some embodiments, the sidewall spacers 224 may be formed by: one or more dielectric materials are deposited over the substrate 102 and then etched to remove the dielectric materials from the horizontal plane. In some embodiments, the one or more dielectric materials may include oxides, nitrides, carbides, and the like.
As shown in cross-sectional view 1900 of fig. 19, a first interlayer dielectric (ILD) layer 226 is formed over the substrate 102. The first ILD layer 226 laterally surrounds the embedded flash memory structure 1602 and the dummy gate structure 1802. In various embodiments, the first ILD layer 226 may comprise an oxide deposited on the substrate 102 by a Chemical Vapor Deposition (CVD) process using a high aspect ratio process (i.e., HARP oxide). For example, in some embodiments, the first ILD layer 226 may comprise borophosphosilicate glass deposited by a CVD process. After forming the first ILD layer 226, a fourth planarization process may be performed to expose an upper surface of the dummy gate electrode 1804.
As shown in the cross-sectional view 2000 of fig. 20, the sacrificial gate electrode (1804 of fig. 19) is removed from the dummy gate structure (1802 of fig. 19) to define a gate electrode cavity 2002. In some embodiments, the sacrificial gate electrode (1804 of fig. 19) may be removed by selectively exposing the sacrificial gate electrode (1804 of fig. 19) to the eighth etchant 2004.
As shown in cross-sectional view 2100 of fig. 21, a metal gate material 2102 is formed over gate dielectric layer 220. A metal gate material 2102 fills the gate electrode cavity 2002. In some embodiments, the metal gate material 2102 may be formed using deposition techniques (e.g., PVD, CVD, ALD, PE-CVD, etc.). A fifth planarization process is then performed along line 2104. A fifth planarization process removes portions of the metal gate material 2102 from over the first ILD layer 226 to define the gate electrode 218. The fifth planarization process may also remove the hard mask layer to define the embedded flash memory structure 107. In some embodiments, metal gate material 2102 can include an n-type gate metal, such as aluminum, tantalum, titanium, hafnium, zirconium, titanium silicide, tantalum nitride, tantalum silicon nitride, chromium, tungsten, copper, titanium aluminum, and the like. In other embodiments, the metal gate material 2102 can include a p-type metal gate, such as nickel, cobalt, molybdenum, platinum, lead, gold, tantalum nitride, molybdenum silicide, ruthenium, chromium, tungsten, copper, and the like.
As shown in cross-sectional view 2200 of fig. 22, the conductive contact 230 is formed on a second inter-layer dielectric (ILD) layer 228 overlying the first ILD layer 226. The conductive contact 230 may be formed by: forming a second ILD layer over the first ILD layer 226; selectively etching the second ILD layer 228 to form an opening; and subsequently depositing a conductive material within the opening. In some embodiments, for example, the conductive material may comprise tungsten (W) or titanium nitride (TiN).
Figure 23 illustrates a flow diagram of some embodiments of a method 2300 of forming an integrated chip of an embedded flash memory device with an enhanced floating gate.
While the method 2300 is illustrated and described hereinafter as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments described herein. Further, one or more of the acts illustrated herein may be implemented in one or more separate acts and/or phases.
At act 2302, the substrate is recessed into an embedded memory region of the substrate. Fig. 4 illustrates a cross-sectional view 400 of some embodiments corresponding to act 2302.
In act 2304, a plurality of isolation structures are formed within a plurality of first trenches within a logic region of a substrate. Fig. 5-6 illustrate cross-sectional views 500-600 of some embodiments corresponding to act 2304.
In act 2306, a protective layer is formed over the substrate and over the plurality of first isolation structures. Fig. 7 illustrates a cross-sectional view 700 of some embodiments corresponding to act 2306.
In act 2308, a plurality of second trenches is formed in the embedded memory region. Fig. 7 illustrates a cross-sectional view 700 of some embodiments corresponding to act 2308.
In act 2310, an isolation layer is formed over the substrate and within the plurality of second trenches. Fig. 8 illustrates a cross-sectional view 800 of some embodiments corresponding to act 2310.
In act 2312, a sacrificial mask layer is formed over the isolation layer and within the plurality of second trenches. Fig. 9 illustrates a cross-sectional view 900 of some embodiments corresponding to act 2312.
In act 2314, portions of the sacrificial mask layer and the isolation layer over the substrate are removed. The remainder of the sacrificial mask layer has an outer sidewall that is separated from sidewalls of the substrate defining the plurality of second trenches by an isolation layer. Fig. 10 illustrates a cross-sectional view 1000 of some embodiments corresponding to act 2314.
In act 2316, the isolation layer between the sacrificial mask layer and the sidewalls of the substrate is removed to form pits along edges of the plurality of second trenches. Fig. 11 illustrates a cross-sectional view 1100 of some embodiments corresponding to act 2316.
In act 2318, a dielectric is formed on the exposed surface of the substrate. In some embodiments, the dielectric is formed by performing a thermal oxidation process on exposed surfaces of the substrate. Fig. 12 illustrates a cross-sectional view 1200 of some embodiments corresponding to act 2318.
In act 2320, the protective layer is removed from within the embedded memory region to define a floating gate recess. Fig. 13 illustrates a cross-sectional view 1300 of some embodiments corresponding to act 2320.
In act 2322, a floating gate is formed within the floating gate recess and within the dimple. Fig. 14-15 illustrate cross-sectional views 1400-1500 of some embodiments corresponding to act 2322.
In act 2324, the remainder of the flash memory structure is formed. Fig. 16A-16B illustrate cross-sectional views 1600 and 1606 of some embodiments corresponding to act 2324.
In act 2326, a transistor device is formed within the logic region. In some embodiments, a high-k metal gate (HKMG) replacement process may be used to form the transistor devices. Fig. 17-21 illustrate cross-sectional views 1700-2100 of some embodiments corresponding to act 2326.
In act 2328, a conductive contact is formed within the ILD layer above the substrate. Fig. 22 illustrates a cross-sectional view 2200 of some embodiments corresponding to act 2328.
Accordingly, in some embodiments, the present disclosure is directed to an integrated chip having a flash memory structure with a floating gate whose sidewalls define a protrusion extending outwardly (e.g., downwardly) from a lower surface of the floating gate. The overhang causes the floating gate to surround a portion of the substrate forming the channel region, thereby improving the performance of the flash memory structure by increasing the size of the interface region between the channel region and the floating gate.
In some embodiments, the present disclosure relates to flash memory structures. The flash memory structure includes: a source region and a drain region disposed within the substrate; a select gate formed over the substrate between the source region and the drain region; a floating gate disposed over the substrate between the select gate and the source region; a control gate disposed over the floating gate; and wherein the floating gate has sidewalls defining a protrusion extending downward from a lower surface of the floating gate to define a recess within a bottom of the floating gate. In some embodiments, the flash memory structure further comprises: a plurality of isolation structures disposed within a trench defined by sidewalls of the substrate, wherein the source region and the drain region are separated along a first direction and the floating gate is disposed between the plurality of isolation structures along a second direction, wherein the second direction is perpendicular to the first direction. In some embodiments, the uppermost surfaces of the plurality of isolation structures are higher than the bottom surface of the floating gate and lower than the top surface of the floating gate. In some embodiments, the flash memory structure further comprises: a dielectric layer disposed between the floating gate and the substrate, wherein the dielectric layer is disposed along a sidewall of the substrate. In some embodiments, the dielectric layer extends vertically below a bottom most surface of the floating gate. In some embodiments, the protrusion is disposed between the dielectric layer and the isolation structure. In some embodiments, the source region and the drain region are separated by a portion of the substrate that includes a channel region; and the floating gate surrounds a plurality of surfaces of the portion of the substrate including the channel region. In some embodiments, the protrusion has angled sidewalls to decrease the width of the protrusion as the distance from the lower surface of the floating gate increases. In some embodiments, the height of the floating gate along the outer sidewall of the floating gate is greater than the height at the center of the floating gate. In some embodiments, the flash memory structure further comprises: a transistor device disposed over an upper surface of the substrate, wherein the floating gate is disposed over a recessed surface of the substrate, the recessed surface being coupled to the upper surface of the substrate by sidewalls of the substrate; and the remainder of the floating gate material is disposed along sidewalls of the substrate.
In an embodiment, the flash memory structure further comprises: a plurality of isolation structures disposed within a trench defined by sidewalls of the substrate, wherein the source region and the drain region are separated along a first direction and the floating gate is disposed between the plurality of isolation structures along a second direction, wherein the second direction is perpendicular to the first direction.
In an embodiment, the uppermost surfaces of the plurality of isolation structures are higher than the bottom surface of the floating gate and lower than the top surface of the floating gate.
In an embodiment, the flash memory structure further comprises: a dielectric layer disposed between the floating gate and the substrate, wherein the dielectric layer is disposed along a sidewall of the substrate.
In an embodiment, the dielectric layer extends vertically below a bottom most surface of the floating gate.
In an embodiment, the protrusion is arranged between the dielectric layer and the isolation structure.
In an embodiment, the source region and the drain region are separated by a portion of the substrate comprising a channel region; and the floating gate surrounds a plurality of surfaces of the portion of the substrate including the channel region.
In an embodiment, the protrusion has angled sidewalls to decrease the width of the protrusion as the distance from the lower surface of the floating gate increases.
In an embodiment, a height of the floating gate along an outer sidewall of the floating gate is greater than a height at a center of the floating gate.
In an embodiment, the flash memory structure further comprises: a transistor device disposed over an upper surface of the substrate, wherein the floating gate is disposed over a recessed surface of the substrate, the recessed surface being coupled to the upper surface of the substrate by sidewalls of the substrate; and wherein the remainder of the floating gate material is disposed along sidewalls of the substrate. In other embodiments, the present disclosure relates to flash memory structures. A flash memory structure comprising: a source region and a drain region disposed within the substrate and separated by a channel region along a first direction; a plurality of isolation structures disposed within trenches defined by sidewalls of the substrate, wherein the plurality of isolation structures are separated along a second direction that is perpendicular to the first direction; a control gate disposed over the channel region; and a floating gate vertically disposed between the control gate and the channel region and horizontally disposed between the plurality of isolation structures, wherein the floating gate extends into a trench defined by sidewalls of the substrate. In some embodiments, the floating gate has sidewalls defining a protrusion extending perpendicularly outward from a lower surface of the floating gate. In some embodiments, the protrusion has opposing sidewalls, wherein the opposing sidewalls are oriented at different sidewall angles with respect to a horizontal plane. In some embodiments, the flash memory structure further comprises: a first dielectric layer disposed between the floating gate and the substrate, wherein the first dielectric layer is disposed along a sidewall of the substrate. In some embodiments, the first dielectric layer extends vertically below a bottom most surface of the floating gate. In some embodiments, the floating gate is disposed directly between the first dielectric layer and the isolation structure.
In an embodiment, the floating gate has sidewalls defining a protrusion extending perpendicularly outward from a lower surface of the floating gate.
In an embodiment, the protrusion has opposing sidewalls, wherein the opposing sidewalls are oriented at different sidewall angles with respect to a horizontal plane.
In an embodiment, the flash memory structure further comprises: a first dielectric layer disposed between the floating gate and the substrate, wherein the first dielectric layer is disposed along a sidewall of the substrate.
In an embodiment, the first dielectric layer extends vertically below a bottom most surface of the floating gate.
In an embodiment, the floating gate is arranged directly between the first dielectric layer and the isolation structure.
In still other embodiments, the present disclosure relates to methods of forming flash memory structures. The method comprises the following steps: forming a protective layer over a substrate; forming a plurality of trenches extending through the protective layer to reach into the substrate; forming an isolation layer over the protective layer and within the plurality of trenches; forming a sacrificial mask layer over the isolation layer; removing portions of the sacrificial mask layer and the isolation layer, wherein a remainder of the sacrificial mask layer has an outermost sidewall that is separated from sidewalls of the protection layer defining the plurality of trenches by the isolation layer; selectively etching the isolation layer between the sacrificial mask layer and sidewalls of the protection layer to form a recess along edges of the plurality of trenches; removing the protective layer to define the floating gate recess; and forming a floating gate material within the floating gate recess and the pit. In some embodiments, the method further comprises: performing a thermal oxidation process after removing the protective layer, wherein the thermal oxidation process forms an oxide along sidewalls of the substrate defining the recess. In some embodiments, the method further comprises: the floating gate material is etched to reduce a thickness of the floating gate material and define a plurality of floating gates. In some embodiments, the pits extend through the protective layer to reach into the substrate.
In an embodiment, the method further comprises: performing a thermal oxidation process after removing the protective layer, wherein the thermal oxidation process forms an oxide along sidewalls of the substrate defining the recess.
In an embodiment, the method further comprises: the floating gate material is etched to reduce a thickness of the floating gate material and define a plurality of floating gates.
In an embodiment, the pits extend through the protective layer to reach into the substrate.
The above discussion of features of the various embodiments is presented to enable a person skilled in the art to better understand various aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
