阅读说明：本技术 存储器装置及其形成方法 (Memory device and forming method thereof ) 是由 周仲彦 于 2019-01-29 设计创作，主要内容包括：本发明的实施例提供一种存储器装置及其形成方法。方法包含在衬底上方的下部内连线层上方形成存储单元堆叠,存储单元堆叠包含位于底部金属上方的数据存储层。第一介电层形成在存储单元堆叠上方。第一掩模层形成在第一介电层上方。第一掩模层上覆于第一介电层的中心部分,且使得第一介电层的牺牲部分未经覆盖。根据第一掩模层形成第一介电层的第一刻蚀。金属间介电层形成在存储单元堆叠上方。顶部电极形成于存储单元堆叠上方的金属间介电层内。上部内连线层形成在顶部电极上方。上部内连线层以及下部内连线层包括与顶部电极不同的材料。(Embodiments of the invention provide a memory device and a method of forming the same. The method includes forming a memory cell stack over a lower interconnect layer over a substrate, the memory cell stack including a data storage layer over a bottom metal. A first dielectric layer is formed over the memory cell stack. A first mask layer is formed over the first dielectric layer. The first mask layer overlies a central portion of the first dielectric layer and leaves a sacrificial portion of the first dielectric layer uncovered. A first etch of the first dielectric layer is formed according to the first mask layer. An inter-metal dielectric layer is formed over the memory cell stack. A top electrode is formed within the inter-metal dielectric layer above the memory cell stack. An upper interconnect layer is formed over the top electrode. The upper interconnect layer and the lower interconnect layer comprise a different material than the top electrode.)

1. A method of forming a memory device, the method comprising:

forming a memory cell stack over a lower interconnect layer over a substrate, wherein the memory cell stack includes a data storage layer over a bottom metal;

forming a first dielectric layer over the memory cell stack;

forming a first mask layer over the first dielectric layer, wherein the first mask layer overlies a central portion of the first dielectric layer and leaves a sacrificial portion of the first dielectric layer uncovered;

performing a first etch of the first dielectric layer and the memory cell stack according to the first mask layer;

forming an inter-metal dielectric layer over the memory cell stack after performing the first etch;

forming a top electrode within the inter-metal dielectric layer and directly over the memory cell stack; and

forming an upper interconnect layer over the top electrode, wherein the upper interconnect layer and the lower interconnect layer comprise a different material than the top electrode.

2. The method of claim 1, wherein the top electrode is formed in direct contact with the data storage layer or a cap layer over the data storage layer.

3. The method of forming a memory device of claim 1,

wherein the memory cell stack further comprises a top metal layer over the data storage layer; and

wherein the top electrode directly contacts an upper surface of the top metal layer.

4. The method of claim 1, wherein outer sidewalls of the memory cells are aligned with outer sidewalls of the first dielectric layer.

5. The method of forming a memory device of claim 1, wherein:

wherein the first mask layer comprises a photoresist layer overlying a second dielectric layer, wherein the second dielectric layer is in direct contact with the first dielectric layer; and

wherein the first etch removes the photoresist layer and leaves a central portion of the second dielectric layer directly over the central portion of the first dielectric layer.

6. A memory device, comprising:

a resistive random access memory cell disposed over a bottom electrode and comprising a data storage layer located between a top metal layer and a bottom metal layer, wherein an outermost sidewall of the data storage layer, the top metal layer, and the bottom metal layer are substantially aligned;

an inter-metal dielectric layer over the resistive random access memory cell; and

a top electrode overlying the resistive random access memory cell and within the inter-metal dielectric layer, wherein the top electrode has a bottom surface with a first width and a top surface with a second width, the second width being greater than the first width, the bottom surface of the top electrode contacting the top metal layer at a location that is set back a non-zero distance from a sidewall of the top metal layer.

7. The memory device of claim 6, further comprising:

an upper interconnect layer contacting the top electrode, wherein the top electrode and the bottom electrode comprise a first material, and wherein the upper interconnect layer comprises a second material different from the first material.

8. The memory device of claim 6, wherein the resistive random access memory cell further comprises:

an etch stop layer overlying the top metal layer; and

wherein the top electrode extends through the etch stop layer to the top metal layer, wherein the bottom surface of the top electrode is lower than a top surface of the top metal layer.

9. A memory device, comprising:

a resistive random access memory cell disposed over a bottom electrode within a memory array region, wherein the resistive random access memory cell includes a data storage layer located between a top metal layer and a bottom metal layer;

an inter-metal dielectric layer over the resistive random access memory cell;

a top electrode overlying the resistive random access memory cell and within the inter-metal dielectric layer such that a top surface of the top electrode is aligned with a top surface of the inter-metal dielectric layer, wherein the top electrode extends through an etch stop layer of the resistive random access memory cell to directly contact the top metal layer;

an inter-level dielectric layer over the inter-metal dielectric layer within the memory array region;

a logic region adjacent to the memory array region, wherein a first lower surface of the interlayer dielectric layer within the memory array region is higher than a second lower surface of the interlayer dielectric layer within the logic region, a difference between the first lower surface and the second lower surface being defined by a height; and

wherein the height is equal to a distance between a bottom surface of the bottom metal layer and the top surface of the top electrode.

10. The memory device of claim 9, wherein a maximum width of the top electrode is less than a minimum width of the resistive random access memory cell.

Technical Field

Embodiments of the invention relate to a memory device and a method of forming the same.

Background

Many modern electronic devices contain electronic memory configured to store data. The electronic memory may be volatile memory or non-volatile memory. Volatile memory stores data only when it is powered, whereas non-volatile memory is capable of retaining data when power is removed. Resistive Random Access Memory (RRAM) is a promising candidate for next-generation non-volatile memory technologies due to its simple structure and the CMOS logic-compatible processing technology involved. The RRAM cell includes a dielectric data storage layer having a variable resistance placed between two electrodes disposed within an interconnect metallization layer.

Disclosure of Invention

Some embodiments of the present application provide a method of forming a memory device, the method comprising: forming a memory cell stack over a lower interconnect layer over a substrate, wherein the memory cell stack includes a data storage layer over a bottom metal; forming a first dielectric layer over the memory cell stack; forming a first mask layer over the first dielectric layer, wherein the first mask layer overlies a central portion of the first dielectric layer and leaves a sacrificial portion of the first dielectric layer uncovered; performing a first etch of the first dielectric layer and the memory cell stack according to the first mask layer; forming an inter-metal dielectric (IMD) layer over the memory cell stack after performing the first etch; forming a top electrode within the inter-metal dielectric layer and directly over the memory cell stack; and forming an upper interconnect layer over the top electrode, wherein the upper interconnect layer and the lower interconnect layer comprise a different material than the top electrode. .

Further, another embodiment of the present application provides a memory device, including: a Resistive Random Access Memory (RRAM) cell disposed above a bottom electrode and comprising a data storage layer between a top metal layer and a bottom metal layer, wherein an outermost sidewall of the data storage layer, the top metal layer, and the bottom metal layer are substantially aligned; an inter-metal dielectric (IMD) layer over the resistive random access memory cell; and a top electrode overlying the resistive random access memory cell and within the inter-metal dielectric layer, wherein the top electrode has a bottom surface with a first width and a top surface with a second width, the second width being greater than the first width, the bottom surface of the top electrode contacting the top metal layer at a location that is set back a non-zero distance from a sidewall of the top metal layer.

In addition, another embodiment of the present application provides a memory device, including: a Resistive Random Access Memory (RRAM) cell disposed over a bottom electrode within a memory array region, wherein the resistive random access memory cell includes a data storage layer between a top metal layer and a bottom metal layer; an inter-metal dielectric (IMD) layer over the resistive random access memory cell; a top electrode overlying the resistive random access memory cell and within the inter-metal dielectric layer such that a top surface of the top electrode is aligned with a top surface of the inter-metal dielectric layer, wherein the top electrode extends through an etch stop layer of the resistive random access memory cell to directly contact the top metal layer; an inter-layer dielectric (ILD) layer over the inter-metal dielectric layer within the memory array region; a logic region adjacent to the memory array region, wherein a first lower surface of the interlayer dielectric layer within the memory array region is higher than a second lower surface of the interlayer dielectric layer within the logic region, a difference between the first lower surface and the second lower surface being defined by a height; and wherein the height is equal to a distance between a bottom surface of the bottom metal layer and the top surface of the top electrode.

Drawings

Aspects of embodiments of the present invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, according to standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIGS. 1A, 1B, and 1C illustrate cross-sectional views of some embodiments of memory devices according to the present invention.

FIG. 2 illustrates a cross-sectional view of some embodiments of a memory device including a memory region and a logic region in accordance with the present invention.

Figures 3 through 4 illustrate cross-sectional views of some embodiments of memory devices according to the present invention.

FIG. 5 shows a cross-sectional view depicting some embodiments of a memory device including two memory cells according to the present disclosure.

FIG. 6 illustrates a top view of the memory device of FIG. 5 as indicated by the cut lines in FIG. 5, in accordance with an embodiment of the present invention.

Fig. 7-12 illustrate cross-sectional views of some embodiments of methods of forming memory devices according to the present invention.

Figure 13 illustrates a method depicting some embodiments of a method of forming a memory device according to the present invention in flow chart format.

Description of the reference numerals

100a, 100b, 200, 300: a memory device;

100c, 400, 700, 800, 900, 1000, 1100, 1200: a cross-sectional view;

101: a transistor;

102. 506: a substrate;

103: a conductive contact;

104: an interconnect wire;

106: an interlayer dielectric structure;

108: a bottom electrode;

110: a lower etch stop layer;

112: a bottom metal layer;

114: a dielectric data storage layer;

116: a top metal layer;

116a, 116 b: an outer edge;

118. 120: a dielectric layer;

122. 123, 125: a storage unit;

122a, 122 b: an outermost wall;

124: a top electrode;

126: an inter-metal dielectric layer;

130: an interlayer dielectric layer;

132. 202: a via hole;

134: a conductive wire;

150: a gate electrode;

152: transistor sidewall spacers;

154: a gate dielectric;

156: a source/drain region;

201 a: a storage array region;

201 b: a logic area;

500: an integrated circuit;

504: an interconnect structure;

508: shallow trench isolation regions;

510. 512: an access transistor;

514. 516: an access gate electrode;

518. 520, the method comprises the following steps: accessing the gate dielectric layer;

522: accessing the sidewall spacers;

524: a source/drain region;

526. 528, 530: an inter-metal dielectric layer;

532. 534, 536: a metallization layer;

538. 540 and 542: a metal wire;

544: a contact;

546: a through hole;

550. 552: a dielectric protective layer;

702. 902: a mask layer;

704a, 704 c: a sacrificial region;

704 b: a central region;

802. 1002: etching agent;

804a, 804 b: a side wall;

904. 1004: an opening;

1300: a method;

1302. 1304, 1306, 1308, 1310, 1312, 1314, 1316: an action;

BL₁、BL₂: a bit line;

h₁、h₂: a height;

W₁、W₂: a width;

WL: word lines.

Detailed Description

Embodiments of the invention provide many different embodiments or examples for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the embodiments of the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, embodiments of the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various implementations and/or configurations discussed.

Furthermore, spatially relative terms, such as "below," "lower," "above," "upper," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as well.

A Resistive Random Access Memory (RRAM) cell includes a dielectric data storage layer placed between a top metal layer and a bottom metal layer. Depending on the voltages applied to the top and bottom metal layers, the dielectric data storage layer will reversibly transition between a high resistance state associated with a first data state (e.g., '0' or 'RESET') and a low resistance state associated with a second data state (e.g., '1' or 'SET'). Once the resistance state is SET, the RRAM cell will retain the resistance state until another voltage is applied to induce either a RESET operation (resulting in a high resistance state) or a SET operation (resulting in a low resistance state). A top metal layer and a bottom metal layer are disposed between the top electrode and the bottom electrode. A top electrode via or wire overlies and directly contacts the top electrode of a corresponding RRAM cell, providing a conductive path to the RRAM cell from a metal layer disposed above.

During formation of the RRAM cell, a memory cell stack is formed over a substrate. The memory cell stack includes a dielectric data storage layer disposed between a top metal layer and a bottom metal layer. A top electrode layer is formed over the top metal layer, and a hard mask layer is formed over the top electrode layer. Separate etch processes are then performed to define the top and bottom electrodes. For example, a first etch process is performed to define the top electrode by patterning the top electrode layer and the top metal layer. During the first etch process, material from the top electrode layer will redeposit onto the sidewalls of the hard mask layer. During the second etch process for patterning the bottom electrode, material from the top electrode layer may be etched and redistributed onto the sidewalls of the dielectric data storage layer. Because the material is conductive, the material may electrically short the top metal layer and the bottom metal layer, rendering the RRAM cell inoperable.

In some embodiments of the present invention, to eliminate redeposition of material from the top electrode layer onto the sidewalls of the memory cell stack, the top electrode layer may be formed after patterning the memory cell stack. In such embodiments, an etch stop layer is formed over the top metal layer of the memory cell stack, and a mask layer is formed over a central portion of the etch stop layer. A selective etch process is performed to define the RRAM cell by removing the etch stop layer, the mask layer, and a portion of the memory cell stack. An inter-metal dielectric (IMD) layer is formed over the RRAM cell. A top electrode (e.g., top electrode layer) is formed within the IMD layer and over a top metal layer of the RRAM cell. This new method inhibits redeposition of conductive material on the sidewalls of the RRAM cell during the selective etch process and thereby prevents the memory cell stack from shorting together.

Referring to FIG. 1A, a cross-sectional view of a memory device 100a including a storage cell 122 according to some embodiments is provided.

The memory device 100a includes a storage cell 122 disposed over a substrate 102. A first ILD structure 106 comprising one or more inter-level dielectric (ILD) materials is disposed above the substrate 102. The transistor 101 is located within the substrate 102 and the first ILD structure 106. Memory cell 122 is coupled to transistor 101 via conductive contact 103 and interconnect line 104. The lower etch stop layer 110 is disposed between the memory cell 122 and the first ILD structure 106. Bottom electrode 108 is disposed between interconnect line 104 and memory cell 122.

Memory cell 122 includes bottom metal layer 112, dielectric data storage layer 114, top metal layer 116, first dielectric layer 118, and second dielectric layer 120. The bottom metal layer 112 is in direct contact with the bottom electrode 108 and the lower etch stop layer 110. Dielectric data storage layer 114 overlies bottom metal layer 112. A top metal layer 116 overlies dielectric data storage layer 114. A first dielectric layer 118, referred to as an etch stop layer in some embodiments, overlies the top metal layer 116. A second dielectric layer 120 overlies the first dielectric layer 118. In some embodiments, the outermost sidewalls of the various layers in the storage unit 122 are substantially aligned. An inter-metal dielectric (IMD) layer 126 is disposed over the memory cells 122 and surrounds the memory cells 122. Top electrode 124 is disposed within IMD layer 126 and directly contacts top metal layer 116.

In some embodiments, memory cell 122 is an RRAM cell. In the above-described embodiments, dielectric data storage layer 114 comprises a material having a variable resistance configured to undergo a reversible phase change between a high resistance state and a low resistance state. Dielectric data storage layer 114 may be or include, for example, a transition metal oxide including one or more layers of hafnium oxide (HfO)_x) Aluminum oxide (AlO)_x) Tantalum oxide (TaO)_x) Such as oxidationHafnium aluminum (HfAlO) or silicon oxide (SiO)₂) Or the like formed to a thickness in a range of about 10 Angstroms (Angstroms) to about 150 Angstroms. In still further embodiments, memory cells 122 are configured as Magnetoresistive Random Access Memory (MRAM) cells, phase-change random access memory (PCRAM) cells, or Programmable Metallization Random Access Memory (PMRAM) cells.

A second ILD layer 130 is disposed over the memory cells 122 and the top electrode 124. A first conductive line 134 overlies the first via 132. The first conductive line 134 and the first via 132 are disposed within the second ILD layer 130. The first conductive line 134 and the first via 132 electrically couple the memory cell 122 to an overlying metal layer (e.g., a bit line). The outer sidewall of the first via 132 is within the outer sidewall of the top electrode 124. The outer sidewalls of the top electrode 124 are within the outer sidewalls of the first conductive line 134.

In some embodiments, the bottom electrode 108 and the top electrode 124 may comprise the same material (e.g., TaN, TiN, etc.). In other embodiments, the bottom electrode 108 may comprise a first material (e.g., TaN) and the top electrode 124 may comprise a second material different from the first material (e.g., TiN). In some embodiments, the interconnect wire 104 and the first via 132 may comprise a material different from the material of the bottom electrode 108 and the top electrode 124. For example, in some embodiments, the interconnect wire 104 and the first via 132 may comprise copper (Cu), and the bottom electrode 108 and the top electrode 124 may comprise titanium nitride (TiN).

By overlaying the top electrode 124 through the first dielectric layer 118 to contact the top metal layer 116, redeposition of conductive material from the top electrode 124 to the outermost sidewalls 122a, 122b of the memory cell 122 is inhibited during fabrication of the memory cell 122. By inhibiting redeposition of conductive material from top electrode 124, outermost walls 122a, 122b of memory cell 122 are not electrically shorted together by conductive material, which therefore enables memory cell 122 to switch between a high resistance state and a low resistance state.

Referring to FIG. 1B, a cross-sectional view of a memory device 100B including a storage cell 122 according to some embodiments is provided.

The memory device 100b includes a substrate 102. The substrate 102 may be, for example, a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, P-doped silicon, or N-doped silicon. The transistor 101 is located within the substrate 102 and the first ILD structure 106. Transistor 101 includes a gate electrode 150, transistor sidewall spacers 152, a gate dielectric 154, and source/drain regions 156. The interconnect wire 104 is connected to the transistor 101 via the conductive contact 103. In some embodiments, the interconnect lines 104 may be or include aluminum, copper, or the like, for example. A lower etch stop layer 110 overlies the first ILD structure 106 and surrounds the bottom electrode 108. Bottom electrode 108 electrically couples interconnect wire 104 to memory cell 122. In some embodiments, the bottom electrode 108 may be or include, for example, titanium nitride (TiN), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), or the like, formed within a thickness of about 200 angstroms and about 1000 angstroms. In some embodiments, the first ILD structure 106 may be or include an oxide (e.g., SiO) for example₂) A low-k dielectric, a very low-k dielectric, or a combination thereof formed to a thickness of about 500 angstroms to about 3000 angstroms.

Memory cell 122 is disposed directly above lower etch stop layer 110 within IMD layer 126. In some embodiments, IMD layer 126 may be or include an oxide (e.g., SiO) for example₂) A low-k dielectric, a very low-k dielectric, or a combination thereof formed to a thickness of about 500 angstroms to about 3000 angstroms. As used herein, a low-k dielectric can be, for example, a dielectric having a dielectric constant k of less than about 3.9, 2, or 1.5. In some embodiments, the lower etch stop layer 110 may be or include, for example, silicon carbide (SiC), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), an oxide layer, or a combination of the above dielectric materials formed within a thickness of about 100 angstroms to about 400 angstroms.

In some embodiments, memory cell 122 includes bottom metal layer 112, dielectric data storage layer 114, top metal layer 116, first dielectric layer 118, and second dielectric layer 120. A bottom metal layer 112 overlying the bottom electrode 108 and a lower etch stop layer 110. In some embodiments, bottom metal layer 112 may be or include, for example, gold (Au), silver (Ag), Al, Cu, or the like formed to a thickness in a range of about 30 angstroms to about 350 angstroms. Dielectric data storage layer 114 overlies bottom metal layer 112. In some embodiments, dielectric data storage layer 114 may be or include, for example, SiO₂High-k dielectric, hafnium oxide (HfO)_x) Aluminum oxide (AlO)_x) Tantalum oxide (TaOx), or the like formed to a thickness of about 100 angstroms to about 350 angstroms. As used herein, a high-k dielectric may be, for example, a dielectric having a dielectric constant k greater than about 3.9, 10, or 20. A top metal layer 116 overlies dielectric data storage layer 114. In some embodiments, top metal layer 116 may be or include, for example, Au, Cu, Ag, Al, or the like formed to a thickness in a range of about 30 angstroms to about 350 angstroms. A first dielectric layer 118 overlies the top metal layer 116. In some embodiments, the first dielectric layer 118 may be or include, for example, silicon carbide (SiC), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), or the like formed within a thickness of about 500 angstroms to about 2000 angstroms. A second dielectric layer 120 overlies the first dielectric layer 118. In some embodiments, the second dielectric layer 120 may be or include, for example, SiO₂SiN, silicon oxynitride (SiON), or the like formed to a thickness of about 50 angstroms to about 500 angstroms. In some embodiments, second dielectric layer 120 and dielectric data storage layer 114 comprise the same material. For example, in some embodiments, second dielectric layer 120 and dielectric data storage layer 114 comprise silicon oxide.

Top electrode 124 is disposed within IMD layer 126. In some embodiments, top electrode 124 contacts top metal layer 116 through first dielectric layer 118 and second dielectric layer 120. In other embodiments (not shown), the top metal layer 116 may be omitted from the memory cell 122, and the top electrode 124 may directly contact the first dielectric layer 118 or a cap layer (not shown) on top of the first dielectric layer 118. A capping layer (not shown) is configured to store oxygen, which can contribute to a change in resistance within dielectric data storage layer 114. In various embodiments, the capping layer may comprise hafnium, titanium, tantalum, aluminum, zirconium, or the like. In some such embodiments, top electrode 124 may extend laterally to the outermost walls of dielectric data storage layer 114.

In some embodiments, the top electrode 124 may be or include, for example, titanium nitride (TiN), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), or the like formed within a thickness of about 200 angstroms and about 2000 angstroms. In some embodiments, the top electrode 124 includes angled sidewalls, wherein a topmost surface of the top electrode 124 includes a first width that is greater than a second width of a bottommost surface of the top electrode 124. The bottommost surface of top electrode 124 is lower than the topmost surface of top metal layer 116. The maximum width of the top electrode 124 is correspondingly within the maximum width of the top metal layer 116 and smaller than the maximum width of the top metal layer 116. In some embodiments, the material of top electrode 124 and bottom electrode 108 is the same and different from the material of top metal layer 116 and bottom metal layer 112, respectively. In some embodiments, the bottom surface of the top electrode 124 is lower than the upper surface of the top metal layer 116. In some embodiments, the bottom surface of the top electrode 124 is aligned with the upper surface of the top metal layer 116. The outermost sidewalls of the top electrode 124 are within the outermost sidewalls 122a, 122b of the memory cell 122. The outermost walls 122a and 122b of the memory cell 122 may be in direct contact with the IMD layer 126.

A second ILD layer 130 is disposed over the memory cells 122 and the top electrode 124. In some embodiments, the second ILD layer 130 may be or include, for example, SiO₂High-k dielectrics, low-k dielectrics, or the like. In some embodiments, the material of the second ILD layer 130 is different from the material of the IMD layer 126. A first conductive line 134 overlies the top electrode 124. In some embodiments, the first conductive line 134 may be or include, for example, Cu, Al, or the like. The outermost sidewall of the top electrode 124 is within the outermost sidewall of the first conductive line 134. The first conductive line 134 electrically couples the memory cell 122 to any overlying metal layer (e.g., a bit line).

Referring to fig. 1C, a cross-sectional view 100C of some alternative embodiments of the memory device of fig. IA is provided, with the second dielectric layer (120 of fig. 1A) omitted. In some embodiments, the topmost surface of the first dielectric layer 118 is in direct contact with the bottom surface of the IMD layer 126.

Referring to fig. 2, a cross-sectional view of a memory device 200 is provided, the memory device 200 including a memory array region 201a including memory cells 122 and a logic region 201b, according to some embodiments. Memory cells 122 within memory array region 201A are depicted and labeled as memory cells 122 in FIG. 1A.

Within the logic region 201b, the transistor 101 is disposed within the substrate 102 and the first ILD structure 106. Transistor 101 is electrically coupled to interconnect conductor 104 via conductive contact 103. The second via 202 is disposed within the lower etch stop layer 110 and the second ILD layer 130. In some embodiments, the second via 202 can be or include, for example, Cu, Al, or the like. The first conductive line 134 overlies the second via 202. In some embodiments, logical region 201b does not include IMD layer 126.

The first via hole 132 is disposed on the memory cell 122. The second via 202 extends vertically from below the bottom of the first via 132 to a horizontal plane that is parallel to the upper surface of the substrate 102 and extends along the top of the first via 132. Since the second via hole 202 extends from below the bottom of the first via hole 132, the second via hole 202 has a height greater than that of the first via hole 132.

Referring to FIG. 3, a cross-sectional view of a memory device 300 including a storage cell 122. The memory cell 122 is depicted and labeled as memory cell 122 in FIG. 1A.

A first height h is defined at the bottommost surface of top metal layer 116₁. A second height h is defined at the bottommost surface of the top electrode 124₂. In some embodiments, the first height h₁And a second height h₂The first distance therebetween is in a range of about 200 angstroms and about 700 angstroms. In some embodiments, the second height h₂In the range of about 50 angstroms to about 500 angstroms below the topmost surface of top metal layer 116.

First width W₁Defined between the outermost sidewalls of the top electrode 124. Second width W₂Defined between the outermost sidewalls of top metal layer 116. In some embodiments, the first width W₁Between aboutIn the range of 1000 angstroms and 3000 angstroms. In some embodiments, the second width W₂In the range of about 1500 angstroms and 4000 angstroms. First width W₁Is less than the second width W₂. First width W₁And a second width W₂Respectively, in the outermost walls of the bottom metal layer 112 and in the outermost walls of the interconnect lines 104. In some embodiments, the first width W₁Less than the width of the bottom electrode 108. In some embodiments, the first width W₁Greater than the width of the bottom electrode 108. In some embodiments, the first width W₁Within the outermost sidewalls of the bottom electrode 108.

Referring to fig. 4, a cross-sectional view 400 of some alternative embodiments of the memory device of fig. 1A is provided in which the bottommost surface of the top electrode 124 completely overlies the topmost surface of the top metal layer 116. In some embodiments, the bottommost surface of the top electrode 124 extends continuously from the first outer edge 116a of the top metal layer 116 to the second outer edge 116b of the top metal layer 116. The outermost sidewalls of the top electrode 124 extend through the outermost sidewalls of the memory cell 122 and the outermost sidewalls of the first conductive line 134.

Fig. 5 illustrates a cross-sectional view of some embodiments of an integrated circuit 500 including a first memory cell 123 and a second memory cell 125 disposed in an interconnect structure 504 of the integrated circuit 500. The first storage unit 123 and the second storage unit 125 are each shown and described as the storage unit 122 of fig. 1A.

The integrated circuit 500 includes a substrate 506. The substrate 506 may be, for example, a bulk substrate (e.g., a bulk silicon substrate) or a silicon-on-insulator (SOI) substrate. The illustrated embodiment depicts one or more Shallow Trench Isolation (STI) regions 508 that may include dielectric-filled trenches within the substrate 506.

Two access transistors 510, 512 are disposed between the STI regions 508. Access transistors 510 and 512 each include an access gate electrode 514 and an access gate electrode 516, respectively, an access gate dielectric 518, an access gate dielectric 520, an access sidewall spacer 522, and a source/drain region 524. Source/drain regions 524 are disposed within substrate 506Between access gate electrode 514, access gate electrode 516, and STI region 508, it is doped to have a first conductivity type opposite a second conductivity type of the channel region under gate dielectric 518, 520, respectively. The access gate electrodes 514, 516 may be, for example, doped polysilicon or a metal, such as aluminum, copper, or a combination thereof. Access gate dielectric layers 518 and 520 may be, for example, an oxide (e.g., silicon dioxide), or a high-k dielectric material. For example, the access sidewall spacers 522 may be formed of silicon nitride (e.g., Si)₃N₄) And (4) preparing. In some embodiments, access transistor 510 and/or access transistor 512 may be electrically coupled to a Word Line (WL), for example, such that an appropriate WL voltage may be applied to access gate electrode 514 and/or access gate electrode 516.

The interconnect structure 504 is disposed over the substrate 506 and couples devices (e.g., transistors 510, 512) to each other. Interconnect structure 504 includes a plurality of IMD layers 526, IMD layers 528, IMD layers 530, and a plurality of metallization layers 532, 534, 536 layered in an alternating manner with respect to each other. IMD layers 526, 528, 530 may be made of, for example: low- κ dielectrics, such as undoped silicate glass; or oxides, such as silicon dioxide; or an extremely low- κ dielectric layer. Metallization 532, metallization 534, metallization 536 include metal line 538, metal line 540, metal line 542, which are formed within the trench and may be made of a metal such as copper or aluminum. Contacts 544 extend from bottom metallization layer 532 to source/drain regions 524 and/or gate electrodes 514, 516; and vias 546 extend between metallization layers 532, 534, 536. The contacts 544 and vias 546 extend through the dielectric protection layer 550, dielectric protection layer 552 (which may be made of a dielectric material and can act as an etch stop layer during fabrication). For example, the dielectric protection layers 550, 552 may be made of an ultra low- κ dielectric material. For example, the contacts 544 and vias 546 may be made of a metal such as copper or tungsten. In some embodiments, for example, one of the metal lines 538 may be electrically coupled to a Source Line (SL) such that the outputs of the access transistors 510, 512 may be accessed at SL.

The first memory cell 123 and the second memory cell 125 configured to store corresponding data states are disposed within the interconnect structure 504 between adjacent metal layers. First memory cell 123 and second memory cell 125 each include a bottom metal layer 112, a dielectric data storage layer 114, a top metal layer 116, a first dielectric layer 118, a second dielectric layer 120, and a top electrode 124. The first memory cell 123 and the second memory cell 125 are connected to the first bit line BL through metal lines 542, respectively₁And a second bit line BL₂。

Fig. 6 depicts some embodiments of a top view 600 of the integrated circuit 500 of fig. 5, as indicated by the cross-sectional lines shown in fig. 5-6.

The first storage unit 123 and the second storage unit 125 may have a square shape or a circular shape when viewed from above in some embodiments. However, in other embodiments, the corners of the illustrated square shape can be curved, such that the first memory cell 123 and the second memory cell 125 have a square shape with curved corners, or have a circular shape, for example, due to the practicality of many etching processes. In some embodiments, the first memory cell 123 and the second memory cell 125 are each disposed over a metal line (540 of fig. 5) and each have an upper portion in direct electrical connection with the metal line 542 without a via or contact therebetween. In other embodiments, vias or contacts couple the upper portion to metal lines 542.

Fig. 7-12 illustrate cross-sectional views 700-1200 of some embodiments of methods of forming memory devices including memory cells according to embodiments of the invention. Although cross-sectional views 700-1200 shown in fig. 7-12 are described with reference to a method, it should be understood that the structures shown in fig. 7-12 are not limited to the method but may in fact be independent of the method alone. While fig. 7-12 are described as a series of acts, it is to be understood that these acts are not limited to the described order of acts, and may be altered in other embodiments and the disclosed methods are applicable to other configurations as well. In other embodiments, some acts shown and/or described may be omitted entirely or partially.

As shown in the cross-sectional view 700 of fig. 7, the first ILD structure 106 is formed over the substrate 102. Interconnect lines 104 are formed within the first ILD structure 106. In some embodiments, the interconnect wires 104 may be formed by a damascene process. A lower etch stop layer 110 is formed over the interconnect line 104 and the first ILD structure 106. A bottom electrode 108 is formed in a lower etch stop layer 110 over the interconnect line 104. A bottom metal layer 112 is formed over the lower etch stop layer 110. Dielectric data storage layer 114 is formed over bottom metal layer 112. Top metal layer 116 is formed over dielectric data storage layer 114. A first dielectric layer 118 (referred to as an etch stop layer in some embodiments) is formed over top metal layer 116. A second dielectric layer 120 is formed over the first dielectric layer 118. A first masking layer 702 is formed over the second dielectric layer 120. In some embodiments, the layers described above may be formed using a deposition process, such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), some other suitable deposition process, or any combination of the preceding.

The outermost sidewalls of the second dielectric layer 120 are aligned with the outermost sidewalls of the first mask layer 702. The second dielectric layer 120 and the first masking layer 702 are included within the central region 704b directly above the first dielectric layer 118. An upper surface of the first dielectric layer 118 is exposed in the first and second sacrificial regions 704a, 704c outside the central region 704 b.

As shown in cross-section 800 of fig. 8, an etch process is performed to etch the second dielectric layer 120 and the layers below the second dielectric layer 120. An etching process is performed by exposing the layers under the second dielectric layer 120 within the first and second sacrificial regions (704 a, 704c of fig. 7) to one or more etchants 802. For example, the etching process may be performed by a photolithography/etching process and/or some other suitable patterning process. In various embodiments, the etching process may include a single etch (i.e., a continuous etch that etches second dielectric layer 120, bottom metal layer 112, dielectric data storage layer 114, and top metal layer 116), or multiple etches performed in situ. The etching process completely removes the first mask layer (702 of fig. 7) and a portion of the second dielectric layer 120. In some embodiments, the etching process completely removes the second dielectric layer 120. In some embodiments, the etching process removes about 200 to about 600 angstroms of the second dielectric layer 120. In some embodiments, the etch process removes about 50 angstroms to about 500 angstroms of the lower etch stop layer 110.

The first plurality of sidewalls 804a and the second plurality of sidewalls 804b do not include resputtered conductive material. In some embodiments, individual sidewalls within the first plurality of sidewalls 804a are not electrically coupled together. In some embodiments, individual sidewalls within the second plurality of sidewalls 804b are not electrically coupled together. In some embodiments, each sidewall within the first plurality of sidewalls 804a is aligned. In some embodiments, each sidewall within the second plurality of sidewalls 804b is aligned.

As shown in cross-sectional view 900 of fig. 9, IMD layer 126 is formed over lower etch stop layer 110 and second dielectric layer 120. In some embodiments, IMD layer 126 directly contacts the outermost sidewall of second dielectric layer 120, the outermost sidewall of first dielectric layer 118, the outermost sidewall of top metal layer 116, the outermost sidewall of dielectric data storage layer 114, and the outermost sidewall of bottom metal layer 112. A second mask layer 902 is formed over the IMD layer 126 and includes a pair of sidewalls defining a first opening 904. In some embodiments, second mask layer 902 may be or include, for example, photoresist, silicon nitride (SiN), silicon carbide (SiC), or the like. First opening 904 is located directly above top metal layer 116.

As shown in cross-sectional view 1000 of fig. 10, an etch process is performed to remove a portion of top metal layer 116, first dielectric layer 118, second dielectric layer 120, and IMD layer 126. The etching process defines a second opening 1004 directly above top metal layer 116, thereby exposing the upper surface of top metal layer 116. An etch process is performed by exposing top metal layer 116, first dielectric layer 118, second dielectric layer 120, and IMD layer 126 to one or more etchants 1002. For example, the etching process may be performed by a photolithography/etching process and/or some other suitable patterning process. In some embodiments, the etch process removes about 50 angstroms to about 500 angstroms of top metal layer 116. In some embodiments, the etching process does not remove any portion of top metal layer 116.

As shown in the cross-sectional view 1100 of fig. 11, the top electrode 124 is formed within the second opening (1004 of fig. 10). The bottommost surface of top electrode 124 is lower than the topmost surface of top metal layer 116. In some embodiments, the bottommost surface of top electrode 124 and the topmost surface of top metal layer 116 are aligned in a horizontal transverse line. The top electrode 124 may be formed, for example, by: depositing a conductive layer to fill the second opening (1004 of fig. 10) and cover the IMD layer 126; and planarizing the conductive layer until reaching IMD layer 126.

In some alternative embodiments, top metal layer 116 may be omitted from over dielectric data storage layer 114 in such embodiments, top electrode 124 may be formed directly on dielectric data storage layer 114 or on a capping layer (not shown) overlying dielectric data storage layer 114.

As shown in cross-sectional view 1200 of fig. 12, second ILD layer 130 is formed over IMD layer 126. A first via 132 is formed in the second ILD layer 130 above the top electrode 124. A first conductive line 134 is formed within the second ILD layer 130 over the first via 132. The second ILD layer 130 may be formed, for example, by: CVD, PVD, some other suitable deposition process, or any combination of the foregoing. The first via hole 132 and the first conductive line 134 may be formed, for example, by: patterning the second ILD layer 130 to form a via opening having a pattern of first via holes 132 and/or first conductive lines 134; depositing a conductive layer to fill the via opening and cover the second ILD layer 130; and planarizing the conductive layer until the second ILD layer 130 is reached. For example, the patterning may be performed by a photolithography/etching process and/or some other suitable patterning process. For example, deposition may be performed by CVD, PVD, electroless plating, electro plating, some other suitable deposition process, or any combination of the foregoing. For example, planarization may be performed by CMP and/or some other suitable planarization process.

Fig. 13 illustrates a method 1300 of forming a memory device according to some embodiments. While method 1300 is illustrated and/or described as a series of acts or events, it will be appreciated that the method is not limited by the illustrated ordering or acts. Thus, in some embodiments, the actions may occur in a different order than shown, and/or may occur simultaneously. Further, in some embodiments, illustrated acts or events may be sub-divided into multiple acts or events, which may occur at different times or concurrently with other acts or sub-acts. In some embodiments, some illustrated acts or events may be omitted, and other acts or events not illustrated may be included.

At act 1302, a layer of memory cells is formed over a first inter-layer dielectric (ILD) structure, the layer of memory cells including a top metal layer. Fig. 7 illustrates a cross-sectional view 700 corresponding to some embodiments of act 1302.

At act 1304, a first dielectric layer is formed over the top metal layer. Fig. 7 illustrates a cross-sectional view 700 corresponding to some embodiments of act 1304.

At act 1306, a second dielectric layer is formed over the first dielectric layer and a first mask layer is formed over the second dielectric layer, the first mask layer and the second dielectric layer overlying and covering a central portion of the first dielectric layer. Fig. 7 illustrates a cross-sectional view 700 corresponding to some embodiments of act 1306.

At act 1308, the first mask layer is removed, outer portions of the first and second dielectric layers are removed, and outer portions of the layers of the memory cell are removed. Fig. 8 illustrates a cross-sectional view 800 corresponding to some embodiments of act 1308.

At act 1310, an inter-metal dielectric (IMD) layer is formed over the memory cell. Fig. 9 illustrates a cross-sectional view 900 corresponding to some embodiments of act 1310.

At act 1312, a second mask layer is formed over the IMD layer, including sidewalls defining a top electrode opening. Fig. 9 illustrates a cross-sectional view 900 corresponding to some embodiments of act 1312.

At act 1314, an etch process is performed to expose an upper surface of the top metal layer of the memory cell. Fig. 10 illustrates a cross-sectional view 1000 corresponding to some embodiments of act 1314.

At act 1316, a top electrode is formed within the top electrode opening that directly contacts the top metal layer. Fig. 11 illustrates a cross-sectional view 1100 corresponding to some embodiments of act 1316.

Accordingly, in some embodiments, the present invention relates to a method of forming a memory cell, the method comprising forming a top electrode over the memory cell after patterning a layer of the memory cell.

In some embodiments, the present disclosure relates to a method of manufacturing a memory device. The method comprises the following steps: forming a memory cell stack over a lower interconnect layer over a substrate, wherein the memory cell stack comprises a data storage layer over a bottom metal; forming a first dielectric layer over the memory cell stack; forming a first mask layer over the first dielectric layer, wherein the first mask layer overlies a central portion of the first dielectric layer and leaves a sacrificial portion of the first dielectric layer uncovered; performing a first etch of the first dielectric layer and the memory cell stack according to the first mask layer; forming an inter-metal dielectric (IMD) layer over the memory cell stack after performing the first etch; forming a top electrode within the IMD layer and directly over the memory cell stack; and forming an upper interconnect layer over the top electrode, wherein the upper interconnect layer and the lower interconnect layer comprise a different material than the top electrode.

According to some embodiments, wherein the top electrode is formed in direct contact with the data storage layer or a cap layer over the data storage layer.

According to some embodiments, wherein the stack of memory cells further comprises a top metal layer above the data storage layer; and wherein the top electrode directly contacts an upper surface of the top metal layer.

According to some embodiments, wherein a lower surface of the top electrode is lower than an upper surface of the top metal layer.

According to some embodiments, wherein the outer sidewalls of the memory cells are aligned with the outer sidewalls of the first dielectric layer.

According to some embodiments, wherein the first masking layer comprises a photoresist layer overlying a second dielectric layer, wherein the second dielectric layer is in direct contact with the first dielectric layer; and wherein the first etch removes the photoresist layer and leaves a central portion of the second dielectric layer directly over the central portion of the first dielectric layer.

According to some embodiments, the method of forming a memory device further comprises: forming an inter-layer dielectric (ILD) layer over the substrate prior to forming the memory cell stack, wherein the ILD layer is between the memory cell stack and the substrate and surrounds a bottom electrode; and wherein the bottom electrode is in direct contact with the bottom metal, and wherein a lower surface of the top electrode is within a sidewall of the bottom electrode.

According to some embodiments, wherein the top electrode and the bottom electrode are the same material.

According to some embodiments, wherein the same material is titanium nitride, and wherein the upper interconnect layer and the lower interconnect layer each comprise copper or aluminum.

In other embodiments, the present disclosure relates to a memory device. The memory device includes: a Resistive Random Access Memory (RRAM) cell disposed above the bottom electrode and comprising a data storage layer between a top metal layer and a bottom metal layer, wherein outermost sidewalls of the data storage layer, the top metal layer, and the bottom metal layer are substantially aligned; an inter-metal dielectric (IMD) layer over the RRAM cell; and a top electrode overlying the RRAM cell and within the IMD layer, wherein the top electrode has a bottom surface with a first width and a top surface with a second width, the second width being greater than the first width, the bottom surface of the top electrode contacting the top metal layer at a location that is set back from a sidewall of the top metal layer by a non-zero distance.

According to some embodiments, the memory device further comprises: an upper interconnect layer contacting the top electrode, wherein the top electrode and the bottom electrode comprise a first material, and wherein the upper interconnect layer comprises a second material different from the first material.

According to some embodiments, wherein the first material is titanium nitride and the second material is copper or aluminum.

According to some embodiments, the resistive random access memory cell further comprises: an etch stop layer overlying the top metal layer; and wherein the top electrode extends through the etch stop layer to the top metal layer, wherein the bottom surface of the top electrode is lower than a top surface of the top metal layer.

According to some embodiments, wherein the etch stop layer and the data storage layer comprise the same material.

According to some embodiments, wherein a width of the top electrode continuously decreases in a first direction from the top surface of the top electrode to the bottom surface of the top electrode, wherein a width of the resistive random access memory cell continuously increases in the first direction from a top surface of the resistive random access memory cell to a bottom surface of the resistive random access memory cell.

According to some embodiments, wherein the bottom surface of the top electrode is within an outer sidewall of the bottom electrode.

In still other embodiments, the present disclosure is directed to a memory device. The memory device includes: a Resistive Random Access Memory (RRAM) cell disposed over the bottom electrode within the memory array region, wherein the RRAM cell includes a data storage layer between a top metal layer and a bottom metal layer; an inter-metal dielectric (IMD) layer over the RRAM cell; a top electrode overlying the RRAM cell and within the IMD layer such that a top surface of the top electrode is aligned with a top surface of the IMD layer, wherein the top electrode extends through the etch stop layer of the RRAM cell to directly contact the top metal layer; an inter-layer dielectric (ILD) layer over the IMD layer in the memory array region; a logic region adjacent to the memory array region, wherein a first lower surface of the ILD layer in the memory array region is higher than a second lower surface of the ILD layer in the logic region, and a difference between the first lower surface and the second lower surface is defined by a height; and wherein the height is equal to a distance between a bottom surface of the bottom metal layer and a top surface of the top electrode.

According to some embodiments, wherein a maximum width of the top electrode is less than a minimum width of the resistive random access memory cell.

According to some embodiments, wherein the top electrode and the bottom electrode comprise a first material different from a second material comprised by the top metal layer and the bottom metal layer.

In accordance with some embodiments, an upper interconnect structure is disposed within the interlayer dielectric layer in the memory array region and the logic region, the upper interconnect structure including a third material different from the first material and the second material.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the embodiments of the present disclosure. Those skilled in the art should appreciate that they may readily use the present embodiments as a basis for designing or modifying other methods and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the embodiments of the present invention, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the embodiments of the present invention.