阅读说明：本技术 半导体结构及电机驱动装置 (Semiconductor structure and motor driving device ) 是由 余梦霖 肖金玉 郭守誉 于 2018-09-05 设计创作，主要内容包括：本发明涉及一种半导体结构,包括：衬底,具有第一导电类型；第一区域,形成于衬底上,包含第一阱区以及从第一阱区引出的电极,第一阱区具有第二导电类型；第二区域,形成于衬底上,包含第二阱区以及从第二阱区引出的电极,第二阱区具有第二导电类型；隔离结构,形成于衬底上且位于第一区域与第二区域之间以隔离第一阱区与第二阱区；隔离结构包括2M+1个阱区以及从2M+1个阱区中各阱区引出的电极,第一阱区、第二阱区和2M+1个阱区并排设置且相邻阱区的导电类型相反,M大于或等于1。通过在隔离结构中设置多个阱区,可以吸收三极管的绝大部分电子,隔离效果较好。本发明还涉及一种电机驱动装置,该电机驱动装置形成于上述半导体结构中。(The invention relates to a semiconductor structure, comprising: a substrate having a first conductivity type; a first region formed on the substrate and including a first well region having a second conductivity type and an electrode led out from the first well region; a second region formed on the substrate and including a second well region having a second conductivity type and an electrode led out from the second well region; the isolation structure is formed on the substrate and positioned between the first region and the second region to isolate the first well region and the second well region; the isolation structure comprises 2M +1 well regions and electrodes led out from the well regions in the 2M +1 well regions, the first well region, the second well region and the 2M +1 well regions are arranged side by side, the conduction types of the adjacent well regions are opposite, and M is larger than or equal to 1. Through set up a plurality of well regions in isolation structure, can absorb the overwhelming majority electron of triode, it is better to keep apart the effect. The invention also relates to a motor driving device which is formed in the semiconductor structure.)

1. A semiconductor structure, comprising:

a substrate having a first conductivity type;

a first region formed on the substrate and including a first well region and an electrode led out from the first well region, the first well region having a second conductivity type;

a second region formed on the substrate and including a second well region and an electrode led out from the second well region, the second well region having a second conductivity type;

the isolation structure is formed on the substrate and positioned between the first region and the second region so as to isolate the first well region and the second well region;

the isolation structure is characterized by comprising 2M +1 well regions and electrodes led out from the well regions in the 2M +1 well regions, wherein the first well region, the second well region and the 2M +1 well regions are arranged side by side, the conduction types of the adjacent well regions are opposite, and M is greater than or equal to 1.

2. The semiconductor structure of claim 1, wherein the first conductivity type is P-type and the second conductivity type is N-type, the P-well electrode in the isolation structure is grounded, and the N-well electrode in the isolation structure is connected to a positive voltage.

3. The semiconductor structure of claim 2, wherein the isolation structure comprises 3 well regions, respectively a P-well, an N-well, and a P-well.

4. The semiconductor structure of claim 2, wherein the isolation structure comprises 5 well regions, which are a P-well, an N-well, and a P-well, respectively.

5. The semiconductor structure of claim 1, wherein a buried layer is formed between the well region in the isolation structure and the substrate, the buried layer between the N-well in the isolation structure and the substrate is an N-type buried layer, and the P-well in the isolation structure and the buried layer of the substrate are P-type buried layers.

6. The semiconductor structure of claim 1, wherein a shallow junction is formed in each well region in the isolation structure, wherein a doping concentration of the shallow junction is greater than a concentration of a well region in which the shallow junction is located, and wherein each well region in the isolation structure leads out an electrode from the shallow junction.

7. The semiconductor structure of claim 1, wherein the isolation structure is a ring structure, the first region being located inside the ring structure, the second region being located outside the ring structure.

8. The semiconductor structure of claim 7, wherein a width of the well region in the ring structure at the bend increases.

9. The semiconductor structure of claim 7, wherein the first conductivity type is P-type, the second conductivity type is N-type, and an innermost N-well width in the ring structure is greater than or equal to 10 μ ι η.

10. A motor driving device, comprising a first switch tube and a second switch tube, and a first control unit for controlling the first switch tube and a second control unit for controlling the second switch tube, wherein the first switch tube and the second switch tube are connected and the connection end is used as the output end of the driving device to output PWM signal, the first control unit and the second control unit are integrated in the same semiconductor structure, the semiconductor structure is the semiconductor structure of any one of claims 1 to 9, the first region of the semiconductor structure forms the first control unit, and the second region of the semiconductor structure forms the second control unit.

Technical Field

The present invention relates to the field of semiconductors, and in particular, to a semiconductor structure and a motor driving apparatus.

Background

The conventional semiconductor structure usually integrates a plurality of regions, when the well region of the first region is adjacent to the well region of the second region and the conductivity type is the same, an isolation structure is usually arranged between the adjacent well regions to isolate the well regions, and when voltage is applied to the two adjacent well regions, the isolation structure can prevent the two adjacent well regions from being conducted to generate current, so that the two adjacent well regions interfere with each other and the semiconductor device is disordered in work. Currently, the isolation structure is generally a well region with a conductivity type opposite to that of an adjacent well region, and is isolated by forming a PN junction. However, the well region and two adjacent well regions in the isolation structure actually form a parasitic triode, the well region in the isolation structure is equivalent to the base region of the triode, the well regions on the two sides are equivalent to the collector region and the emitter region of the triode, when the voltage on the triple well region meets the conduction condition of the triode, namely the emitter region is forward biased, the collector region is reverse biased, the parasitic triode is conducted, and current is generated between the first region and the second region, so that the first region and the second region are not controlled, and the semiconductor device is disordered in work. Especially, when the semiconductor structure is used for controlling the two switching tubes to work to generate PWM signals, the two switching tubes can be conducted at the same time to damage the switching tubes.

Disclosure of Invention

Therefore, it is necessary to provide a new semiconductor structure to solve the problem that the isolation structure in the conventional semiconductor structure is easily broken down to turn on the two side regions to generate the interference current.

A semiconductor structure, comprising:

a substrate having a first conductivity type;

a first region formed on the substrate and including a first well region and an electrode led out from the first well region, the first well region having a second conductivity type;

a second region formed on the substrate and including a second well region and an electrode led out from the second well region, the second well region having a second conductivity type;

the isolation structure is formed on the substrate and positioned between the first region and the second region so as to isolate the first well region and the second well region;

the isolation structure comprises 2M +1 well regions and electrodes led out from the well regions in the 2M +1 well regions, the first well region, the second well region and the 2M +1 well regions are arranged side by side, the conduction types of the adjacent well regions are opposite, and M is larger than or equal to 1.

Above-mentioned semiconductor structure is provided with isolation structure between first well region and second well region, and this isolation structure includes 2M +1 well regions, and M is more than or equal to 1, and the 2M +1 well regions of first well region, second well region and isolation structure set up side by side and adjacent well region's electrically conductive type is opposite, and isolation structure and first well region, second well region form 2 at least parasitic triodes, exist the collecting electrode promptly in isolation structure. When the voltage applied to each well region accords with the conduction condition of the triode, the collector electrode of the isolation structure can absorb most electrons generated in the first well region, and only a very small amount of electrons can reach the second well region, so that the problem that the second region generates interference current to cause the semiconductor structure to work disorderly is effectively avoided.

In one embodiment, the first conductivity type is P-type, the second conductivity type is N-type, the P-well electrode in the isolation structure is grounded, and the N-well electrode in the isolation structure is connected to a positive voltage.

In one embodiment, the isolation structure includes 3 well regions, which are a P-well, an N-well, and a P-well.

In one embodiment, the isolation structure includes 5 well regions, which are a P-well, an N-well, and a P-well, respectively.

In one embodiment, a buried layer is formed between the well region in the isolation structure and the substrate, the buried layer between the N-well in the isolation structure and the substrate is an N-type buried layer, and the P-well in the isolation structure and the buried layer of the substrate are P-type buried layers.

In one embodiment, a shallow junction is formed in each well region in the isolation structure, the doping concentration of the shallow junction is greater than that of the well region where the shallow junction is located, and each well region in the isolation structure leads out an electrode from the shallow junction.

In one embodiment, the isolation structure is an annular structure, the first region is located inside the annular structure, and the second region is located outside the annular structure.

In one embodiment, the width of the well region in the annular structure at the bend is increased.

In one embodiment, the first conductivity type is P-type, the second conductivity type is N-type, and an innermost N-well width of the ring structure is greater than or equal to 10 μm.

The invention also discloses a motor driving device, which comprises a first switching tube, a second switching tube, a first control unit and a second control unit, wherein the first control unit is used for controlling the first switching tube, the second control unit is used for controlling the second switching tube, the first switching tube is connected with the second switching tube, the connecting end of the first switching tube and the second switching tube is used as the output end of the motor driving device to output PWM signals, the first control unit and the second control unit are integrated in the same semiconductor structure, the semiconductor structure is the semiconductor structure, the first control unit is formed in the first area of the semiconductor structure, and the second control unit is formed in the second area of the semiconductor structure.

According to the motor driving device, the first control unit and the second control unit are integrated in the semiconductor structure, so that the phenomenon that the first control unit and the second control unit interfere with each other to disturb the working time sequence of the first control unit and the second control unit can be effectively avoided, and the phenomenon that the first switch tube and the second switch tube are simultaneously conducted to burn the switch tube is avoided.

Drawings

FIG. 1 is a cross-sectional view of a semiconductor structure in accordance with one embodiment;

FIG. 2 is an electron flow diagram of an isolation structure including only one well region;

FIG. 3 is an electron flow diagram illustrating the conduction of a parasitic transistor according to an embodiment;

FIG. 4 is an equivalent circuit diagram of the parasitic transistor of FIG. 3;

FIG. 5 is an electron flow diagram illustrating the conduction of a parasitic transistor in another embodiment;

FIG. 6 is a cross-sectional view of a semiconductor structure in yet another embodiment;

FIG. 7 is a semiconductor structure layout according to an embodiment;

FIG. 8 is a schematic view of a motor drive;

FIG. 9 is a circuit diagram of a motor driving apparatus according to an embodiment.

Detailed Description

To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

As shown in fig. 1, the semiconductor structure includes a substrate 100, the substrate 100 has a first conductivity type, and the substrate 100 may be formed of undoped single crystal silicon, impurity-doped single crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), germanium-on-insulator (GeOI), or the like. As an example, in the present embodiment, the constituent material of the semiconductor substrate 100 is monocrystalline silicon. A first region 110 is formed on the substrate 100, the first region 110 includes a first well region 111 and an electrode led out from the first well region 111, and the first well region 111 has a second conductivity type, and a conductivity characteristic of the second conductivity type is opposite to a conductivity characteristic of the first conductivity type. A second region 120 is further formed on the substrate 100, the second region 120 and the first region 110 are arranged side by side on the substrate 100, the second region 120 includes a second well region 121 and an electrode led out from the second well region 121, and the second well region 121 has a second conductivity type. An isolation structure 130 is further formed on the substrate 100, the isolation structure 130 is located between the first region 110 and the second region 120 to isolate the first well region 111 and the second well region 121, that is, the first well region 111 and the second well region 121 are respectively located at two sides of the isolation structure 130, and the isolation structure 130 includes 2M +1 well regions 131 arranged side by side, the first well region 111, the second well region 121 and the 2M +1 well regions 131 in the isolation structure are arranged side by side and the conduction types of the adjacent well regions are opposite, that is, a P-well is disposed between two adjacent N-wells, an N-well is disposed in two adjacent P-wells, and the number of the well regions in the isolation structure is an odd number greater than 1, that is, the isolation structure 130 at least includes 3 well regions.

Because the first well region and the second well region have the same conduction type, an isolation structure is arranged between the first well region and the second well region for isolating the first well region and the second well region so as to improve withstand voltage. If only one well region is arranged in the isolation structure, the well region, the first well region and the second well region form a parasitic triode, when the voltage connected with the electrodes of each well region meets the triode conduction condition, namely the positive bias of an emitting electrode and the reverse bias of a collecting electrode are met, the parasitic triode is conducted, and conduction electron current occurs between the first well region and the second well region. As shown in fig. 2, if the semiconductor substrate is a P-type substrate, the first well region is a first N well, the second well region is a second N well, and the isolation structure is a P well, a parasitic NPN transistor is formed, wherein the P-type substrate and the P well in the isolation structure form a base of the parasitic NPN transistor, when an electrode VB led out from the first N well is connected to a negative voltage, such as-5V, and an electrode VCC led out from the second N well is connected to a positive voltage, such as 15V, and an electrode led out from the P well of the isolation structure is grounded, the first N well is an emitter of the parasitic transistor, the second N well is a collector of the parasitic transistor, and at this time, voltages applied to the parasitic transistor satisfy that the emitter is forward biased, the collector is reverse biased, the parasitic transistor NPN is turned on, and a conduction electron flow occurs between the first N well and the second N well (as shown by a dotted arrow in fig. 2.

In a general power device, the first well region and the second well region have respective independent functions, and mutual interference between the two well regions needs to be avoided. Taking a semiconductor structure as an example of a motor driving device, as shown in fig. 8 and 9, a motor system includes a motor driving device and a motor, the motor driving device includes a first switch Q1 and a second switch Q2, and a first control unit 210 for controlling the first switch Q1 and a second control unit 220 for controlling the second switch Q2, an output terminal of the first switch is connected to an input terminal of the second switch and the connection terminal is connected to the motor M as an output terminal of the motor driving device, the first control unit 210 and the second control unit 220 control operation timings of the first switch and the second switch to output a Pulse Width Modulation (PWM) signal, and a connection relationship between the first control unit 210 and the second control unit 220 is shown in fig. 9. When the first control unit and the second control unit are integrated in the same semiconductor structure, for example, the first control unit 210 is formed in the first region 110, the second control unit 220 is formed in the second region 120, the electrode VB led out by the first control unit is an electrode led out by the first well region, and the electrode VCC led out by the second control unit is an electrode led out by the second well region. Under normal conditions, first switch tube and second switch tube switch on in turn in order to output PWM signal, VCC and VB all connect the positive voltage, but in motor dead zone time sequence, when first switch tube and second switch tube are all closed, because the motor inductance is great, even first switch tube and second switch tube all close, motor current can not become 0 immediately, can continue to maintain original current in a certain time, the inductance can draw the current in order to maintain original current from the second switch tube promptly, so can make the voltage of the VS terminal in the circuit diagram be the burden, VS end and VB end pass through bootstrap capacitor and are connected, when VS dropped to the negative value, VB also can drop to the negative value in the twinkling of an eye, like-5V. Due to the existence of the parasitic triode, when the first well region corresponding to VB is an N-well, the second well region corresponding to VCC is an N-well, and the isolation structure only has a P-well, and the P-well is grounded, the phenomenon of conducting the parasitic NPN-type triode introduced above will occur. The parasitic triode is conducted, the second well region receives the electron current brought by the first well region, the working state of the second well region is interfered, if the control time sequence of the second control unit is changed, the second switch tube controlled by the second control unit can be changed from the off state to the on state, at the moment, if the first switch tube is also in the on state, the two switch tubes are all conducted, and the switch tube is burnt due to the fact that the current is large.

In the scheme, the isolation structure arranged between the first well region and the second well region is provided with 2M +1 well regions, and M is greater than or equal to 1. In an embodiment, the first conductivity type is P-type, the second conductivity type is N-type, that is, the semiconductor substrate is a P-type substrate, the first well region is a first N-well, the second well region is a second N-well, and the isolation structure includes M + 1N-wells and M P-wells, wherein M + 1P-wells in the isolation structure are all grounded, and M N-wells in the isolation structure are all connected to a positive voltage. Taking M ═ 1 as an example, as shown in fig. 3, the isolation structure includes 3 well regions, which are the first isolation P well 131A, the second isolation N well 131B, and the third isolation P well 131C, respectively, wherein the first isolation P well 131A and the third isolation P well 131C in the isolation structure are grounded, and the second isolation N well 131B in the isolation structure is connected to the positive voltage V1. At this time, the first well region 111, the second well region 121 and the isolation structure form two parasitic NPN-type triodes, and as shown in fig. 4, the first parasitic triode T1 is composed of the first well region 111, the second isolation N well 131B, and the first isolation P well 131A and the P-type substrate portion sandwiched therebetween, and the second parasitic triode T2 is composed of the first well region 111, the second well region 121, and the third isolation P well 131C and the P-type substrate portion sandwiched therebetween. When the electrode VB of the first well region 111 is connected to a negative voltage and the electrode VCC of the second well region 121 is connected to a positive voltage, the emitters of the first parasitic transistor T1 and the second parasitic transistor T2 are both biased positively, the collectors of the first parasitic transistor T1 and the second parasitic transistor T2 are both biased negatively, the first parasitic transistor T1 and the second parasitic transistor T2 are both turned on, and the electron flow in the first well region 111 flows to the second isolation N-well 131B and the second well region 121 in the isolation structure (as shown by the dotted arrows in fig. 3). Because the second isolation N-well 131B in the isolation structure is closer to the first well region 111, most electrons in the first well region 111 flow to the second isolation N-well 131B in the isolation structure, and only a few electrons flow to the second well region 121, so that the working state of the second region cannot be interfered, namely, the isolation effect of the first region and the second region is better, and even if a parasitic triode is turned on, the two regions cannot be interfered with each other. It should be noted that, in terms of process design, each well region in the isolation structure in this embodiment may be an independent well region, or may be a combined well region formed by a plurality of sub-well regions having the same conductivity type that are adjacently disposed side by side. For example, a certain N well in the isolation structure may be an independent N well, or may be a combined well region formed by two or more sub N well regions arranged adjacently and side by side, and a certain P well in the isolation structure may be an independent P well, or may be a combined well region formed by two or more sub P well regions arranged adjacently and side by side.

In another embodiment, the isolation structure 130 may also include 5 well regions, as shown in fig. 5, the first conductivity type is P-type, the second conductivity type is N-type, the first well region 111 is a first N-well, the second well region 121 is a second N-well, the well regions in the isolation structure sequentially include a first isolation P-well 131A, a second isolation N-well 131B, a third isolation P-well 131C, a fourth isolation N-well 131D, and a fifth isolation P-well 131E, the N-wells in the isolation structure are connected to a positive voltage, and the P-wells in the isolation structure are connected to ground. The first well region 111, the second well region 121 and the isolation structure form 3 parasitic triodes, wherein the first parasitic triode is composed of the first well region 111, a second isolation N-well 131B in the isolation structure, a first isolation P-well 131A and a P-type substrate portion which are clamped in the middle, the second parasitic triode is composed of the first well region 111, a fourth isolation N-well 131D in the isolation structure, a third isolation P-well 131C and a P-type substrate portion which are clamped in the middle, and the third parasitic triode is composed of the first well region 111, the second well region 121, a fifth isolation P-well 131E and a P-type substrate portion which are clamped in the middle. When VB is connected with a negative voltage, and VCC is connected with a positive voltage, the parasitic triodes are all turned on, electrons in the first well region respectively flow to the second isolation N-well 131B, the fourth isolation N-well 131D and the second well region 121 in the isolation structure, and because the N-well in the isolation structure is closer to the first well region 111, most of electrons in the first well region 111 are absorbed by the N-well in the isolation structure, and only few electrons flow into the second well region 121 (as shown by a dotted arrow in fig. 5), so that the isolation effect of the first region and the second region is good, and the two regions do not interfere with each other. In this embodiment, the first conductivity type is P-type, the second conductivity type is N-type, the parasitic triode is NPN-type triode, the isolation structure has a collector of the parasitic triode to absorb most conduction electrons in an emitter of the parasitic triode, in other embodiments, the first conductivity type may also be N-type, the second conductivity type is P-type, the parasitic triode is PNP-type, and the isolation structure has a collector of the parasitic triode to absorb most conduction electrons in an emitter of the parasitic triode.

In one embodiment, as shown in fig. 6, in order to improve the device withstand voltage, a buried layer 140 is further formed between the isolation structure 130 and the substrate 100, and may also be formed between the first region and the substrate and between the second region and the substrate. An N-type buried layer is formed between the N well in the isolation structure and the substrate, and a P-type buried layer is formed between the P well in the isolation structure and the substrate. In an embodiment, a shallow junction 132 is further formed in the well region of the isolation structure, wherein the shallow junction in the P-type well region is a P-type shallow junction, the shallow junction in the N-type well region is an N-type shallow junction, a doping concentration of the shallow junction 132 is greater than a doping concentration of the well region, and an electrode is led out from the shallow junction by each well region in the isolation structure. By arranging the shallow junction, the doping concentration of the well region can be improved, so that the absorption capacity of the isolation structure to electrons is enhanced.

In one embodiment, as shown in fig. 7, the isolation structure 130 is a ring-shaped structure, the first region 110 is located inside the ring-shaped structure, and the second region 120 is located outside the ring-shaped structure, i.e. the first region 110 and the second region 120 are separated by the isolation structure 130. The ring structure 130 includes at least 3 well regions, and in one embodiment, the width of the well region in each ring structure at the bend is increased, i.e., the width of the well region 131A at the bend is at most D1, the width of the well region 131B at the bend is at most D2, and the width of the well region 131C at the bend is at most D3. The four corners of each well region of the isolation structure are widened, so that the isolation structure can absorb electron current more uniformly. In an embodiment, the first conductivity type is P-type, the second conductivity type is N-type, and the width of the innermost N well 131A in the ring structure 130 is greater than or equal to 10 μm, and experiments show that when the width of the inner ring N well is greater than or equal to 10 μm, the N well satisfies a withstand voltage of 60V, i.e., can withstand high voltage. In consideration of the size of the semiconductor structure, the size is reduced as much as possible while satisfying the withstand voltage, and therefore the width of the inner ring well region may be selected to be 10 μm. In one embodiment, to satisfy the P-well withstand voltage of 60V, the width of the P-well in the isolation structure is greater than 8.5 μm.

Above-mentioned semiconductor structure, through set up isolation structure in the middle of first region and second region and be formed with a plurality of well regions in isolation structure, first region, the second region forms a plurality of parasitic triodes with isolation structure and has the collecting electrode of parasitic triode in isolation structure inside, when parasitic triode switches on, the collecting electrode in the accessible isolation structure absorbs most electron flow, only few electron circulates each other between first region and the second region, consequently first region and the regional mutual noninterference of second, isolation structure's isolation effect is better in this scheme.

The invention also discloses a motor driving device, as shown in fig. 8, the motor driving device comprises a first switch tube Q1 and a second switch tube Q2, and further comprises a first control unit 210 for controlling the on and off of the first switch tube Q1 and a second control unit 220 for controlling the on and off of the second switch tube Q2, the output end of the first switch tube Q1 is connected with the input end of the second switch tube Q2, and the output end of the motor driving device is led out from the connecting end, the first control unit 210 and the second control unit 220 control the working time sequence of the first switch tube Q1 and the second switch tube Q2 to enable the output end to output a PWM signal, and the output end is used for being connected with the motor M. In this embodiment, the first control unit and the second control unit are integrated in the semiconductor structure, wherein the first region of the semiconductor structure forms the first control unit, the second region of the semiconductor structure forms the second control unit, and the first control unit and the second control unit are isolated from each other by an isolation structure and do not interfere with each other.

In a specific embodiment, a circuit diagram of the motor driving apparatus is shown in fig. 9, wherein the first control unit 210 outputs the electrode VB corresponding to the first well region output electrode VB in the semiconductor structure, the second control unit 220 outputs the electrode VCC corresponding to the second well region output electrode VCC in the semiconductor structure, the first switch tube and the second switch tube are alternately conducted to output the PWM signal under normal conditions, VCC and VB are both connected to a positive voltage, but in the motor dead zone time sequence, that is, when the first switch tube and the second switch tube are both closed, because the motor inductance is large, even if the first switch tube and the second switch tube are both closed, the motor current will not immediately become 0, and will continue to maintain the original current within a certain time, that is, the inductance will pull the current from the second switch tube to maintain the original current, so that the voltage of the VS terminal in the circuit diagram is negative, and the VS terminal is connected to the VB terminal through the bootstrap capacitor, when VS decreases to a negative value, VB also decreases to a negative value, such as-5V, and when the isolation structure has only one P-well and the P-well is grounded, the NPN parasitic transistor will turn on as described above. The parasitic triode is conducted, the second well region receives the electron current brought by the first well region, the working state of the second well region receives interference, if the control time sequence of the second control unit changes, the second switch tube controlled by the second control unit may be changed from the off state to the on state, at the moment, if the first switch tube is also in the on state, the two switch tubes are all conducted, and the switch tube is burnt due to the fact that the current is large. This scheme is through setting up the isolation structure of many well regions, and isolation structure can absorb the electron current of parasitic triode, only very few electron flow in the second well region from first well region, and the very few electron that flows in the second well region can not cause the interference to the operating condition in second region, consequently adds this isolation structure after, first control unit and second control unit's isolation effect is better. The semiconductor structure including the isolation structure is described in detail above, and is not described herein again.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above examples only show some embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.