阅读说明：本技术 集成电路器件 (Integrated circuit device ) 是由 姜明吉 朴范琎 裵金钟 金洞院 梁正吉 于 2019-06-28 设计创作，主要内容包括：一种集成电路(IC)器件可以包括：鳍型有源区,从衬底突出并沿第一水平方向延伸；第一纳米片,设置在鳍型有源区的上表面之上,其间具有第一分离空间；第二纳米片,设置在第一纳米片之上,其间具有第二分离空间；栅极线,在与第一水平方向交叉的第二水平方向上在衬底上延伸,栅极线的至少一部分设置在第二分离空间中；和底部绝缘结构,设置在第一分离空间中。(An Integrated Circuit (IC) device may include: a fin-type active region protruding from the substrate and extending in a first horizontal direction; the first nanometer sheet is arranged on the upper surface of the fin-shaped active region, and a first separation space is arranged between the first nanometer sheet and the fin-shaped active region; a second nanosheet disposed above the first nanosheet with a second separation space therebetween; a gate line extending on the substrate in a second horizontal direction crossing the first horizontal direction, at least a portion of the gate line being disposed in the second separated space; and a bottom insulation structure disposed in the first separation space.)

1. An integrated circuit device, comprising:

a fin-type active region protruding from the substrate and extending in a first horizontal direction;

a first nanosheet disposed above an upper surface of the fin-shaped active region with a first separation space therebetween;

a second nanosheet disposed above the first nanosheet with a second separation space therebetween;

a gate line extending on the substrate in a second horizontal direction crossing the first horizontal direction, at least a portion of the gate line being disposed in the second separated space; and

a bottom insulation structure disposed in the first separation space.

2. The integrated circuit device of claim 1, further comprising a pair of source/drain regions disposed on the fin-type active region on either side of the gate line,

wherein a width of the first nanoplate in the first horizontal direction is defined by the pair of source/drain regions.

3. The integrated circuit device of claim 1, wherein a width of the bottom insulating structure in the first horizontal direction is less than or equal to a width of the second nanoplatelets in the first horizontal direction.

4. The integrated circuit device of claim 1, wherein the bottom insulating structure has a variable thickness in the second horizontal direction.

5. The integrated circuit device of claim 1 further comprising an isolation layer on the substrate covering both sidewalls of the fin-type active region,

wherein the bottom insulating structure includes a first insulating portion filling the first separation space between the upper surface of the fin-type active region and the first nanosheet, and a second insulating portion extending from the first insulating portion in the second horizontal direction and interposed between the isolation layer and the gate line, and

wherein a thickness of the first insulating portion is greater than a thickness of the second insulating portion.

6. The integrated circuit device of claim 1, further comprising source/drain regions disposed on the fin-type active region and in contact with the first and second nanoplatelets,

wherein the bottom insulating structure includes a first insulating portion filling the first separation space and a second insulating portion extending from the first insulating portion in the first horizontal direction and interposed between the fin-type active region and the source/drain region.

7. The integrated circuit device of claim 1, wherein a thickness of the first nanoplatelet in a vertical direction is different than a thickness of the second nanoplatelet in a vertical direction.

8. The integrated circuit device of claim 1, further comprising:

a source/drain region disposed on the fin-shaped active region and covering respective sidewalls of the first and second nanoplates;

a first insulating spacer covering a sidewall of the gate line and between the gate line and the source/drain region; and

a second insulating spacer interposed between the bottom insulating structure and the source/drain region.

9. The integrated circuit device of claim 1, further comprising source/drain regions in contact with the first nanoplatelet and the second nanoplatelet,

wherein an upper surface of the bottom insulating structure is in contact with the source/drain regions.

10. The integrated circuit device of claim 1, further comprising a gate dielectric layer disposed between the first nanoplate and the gate line and between the second nanoplate and the gate line,

wherein a thickness of the bottom insulating structure is greater than a thickness of the gate dielectric layer.

11. The integrated circuit device according to claim 1, wherein no portion of the gate line is disposed in the first separated space.

12. An integrated circuit device, comprising:

a fin-type active region protruding from the substrate and extending in a first horizontal direction;

a pair of source/drain regions disposed on the fin-shaped active region;

a nanosheet stack structure facing an upper surface of the fin-type active region, wherein there is a first separation space between the nanosheet stack structure and the upper surface, the nanosheet stack structure comprising a plurality of nanosheets having a width in the first horizontal direction defined by the pair of source/drain regions;

a gate line including at least one sub-gate portion extending over the fin-shaped active region in a second horizontal direction crossing the first horizontal direction and disposed within a second separation space between the plurality of nanoplatelets;

a gate dielectric layer interposed between the plurality of nanosheets and the gate line; and

a bottom insulation structure filling the first separation space and having a thickness greater than a thickness of the gate dielectric layer.

13. The integrated circuit device of claim 12, wherein a width of the bottom insulating structure in the first horizontal direction is less than or equal to a width of the nanosheet stack structure in the first horizontal direction.

14. The integrated circuit device of claim 12, wherein the plurality of nanoplatelets have different thicknesses in the vertical direction.

15. The integrated circuit device of claim 12, wherein the pair of source/drain regions are disposed on the fin-shaped active region on both sides of the gate line and in contact with respective sidewalls of the plurality of nanoplatelets,

wherein a lower surface level of the pair of source/drain regions is lower than a lower surface level of the bottom insulating structure.

16. The integrated circuit device of claim 12, wherein the pair of source/drain regions are disposed on the fin-shaped active region on both sides of the gate line and in contact with respective sidewalls of the plurality of nanoplatelets,

wherein an upper surface of the bottom insulating structure is in contact with the pair of source/drain regions.

17. The integrated circuit device of claim 16, wherein the bottom insulating structure comprises a first insulating portion and a pair of second insulating portions,

wherein the first insulating portion fills the first separation space, and the pair of second insulating portions extend from both sides of the first insulating portion in the first horizontal direction and are interposed between the fin-type active region and the pair of source/drain regions, and

wherein lower surfaces of the pair of source/drain regions are in contact with the pair of second insulating portions.

18. The integrated circuit device of claim 12, wherein the bottom insulating structure comprises a first insulating portion and a second insulating portion, and

wherein the first insulating portion fills the first separation space, and the second insulating portion extends from the first insulating portion in the second horizontal direction and has a thickness smaller than that of the first insulating portion.

19. The integrated circuit device of claim 12, wherein the bottom insulating structure comprises an air gap, a width of the air gap in the second horizontal direction being defined by the gate line.

20. An integrated circuit device, comprising:

a fin-type active region extending in a first horizontal direction on the substrate;

at least one source/drain region disposed in a row on the fin-type active region along the first horizontal direction;

at least one nanosheet stacking structure disposed on the fin-type active region, including a first nanosheet closest to the fin-type active region and a second nanosheet disposed above the first nanosheet;

at least one gate line covering the nanosheet stack structure and on the fin-shaped active area and extending in a second horizontal direction that intersects the first horizontal direction;

a gate dielectric layer disposed between the nanosheet stack and the gate line; and

a bottom insulating structure interposed between the fin-type active region and the nanosheet stack structure and integrally connected to the gate dielectric layer.

Technical Field

The present inventive concept relates to Integrated Circuit (IC) devices, and more particularly, to IC devices including horizontal nanoplate field effect transistors.

Background

As the size of IC devices decreases, it is necessary to increase the integration degree of electric field effect transistors on a substrate, and therefore, a horizontal nanosheet field effect transistor hNSFET comprising a plurality of horizontal nanosheets stacked on the same layout area has been developed. However, as the integration degree of semiconductor devices increases and the size of the devices decreases to an extreme state, the electrical characteristics of the nanosheet electric field effect transistor may deteriorate due to unwanted parasitic transistors. Therefore, the nanosheet electric field effect transistor requires a new structure capable of improving its electrical characteristics by suppressing the formation of unwanted parasitic transistors.

Disclosure of Invention

Exemplary embodiments of the inventive concept provide an Integrated Circuit (IC) device having a structure by which formation of an unnecessary parasitic capacitor can be suppressed and electrical characteristics can be improved.

According to an aspect of the inventive concept, there is provided an IC device, which may include: a fin-type active region protruding from the substrate and extending in a first horizontal direction; the first nanometer sheet is arranged on the upper surface of the fin-shaped active region, and a first separation space is arranged between the first nanometer sheet and the fin-shaped active region; a second nanosheet disposed above the first nanosheet with a second separation space therebetween; a gate line extending on the substrate in a second horizontal direction crossing the first horizontal direction, at least a portion of the gate line being disposed in the second separated space; and a bottom insulation structure disposed in the first separation space.

According to another aspect of the inventive concept, there is provided an IC device, which may include: a fin-type active region protruding from the substrate and extending in a first horizontal direction; a pair of source/drain regions disposed on the fin-shaped active region; a nanosheet stack structure facing an upper surface of the fin-type active region with a first separation space therebetween, the nanosheet stack structure including a plurality of nanosheets having a width in a first horizontal direction defined by the pair of source/drain regions; a gate line including at least one sub-gate portion extending over the fin-shaped active region in a second horizontal direction crossing the first horizontal direction and disposed within second separation spaces between the plurality of nano-sheets; a gate dielectric layer interposed between the plurality of nanosheets and the gate line; and a bottom insulation structure filling the first separation space and having a thickness greater than that of the gate dielectric layer.

According to another aspect of the inventive concept, there is provided an IC device, which may include: a fin-type active region extending in a first horizontal direction on the substrate; at least one source/drain region disposed in a row on the fin-type active region along a first horizontal direction; the nano-sheet stacking structure is arranged on the fin-type active region and comprises a first nano-sheet closest to the fin-type active region and a second nano-sheet arranged on the first nano-sheet; at least one gate line covering the nanosheet stacked structure and on the fin-shaped active area, and extending in a second horizontal direction crossing the first horizontal direction; a gate dielectric layer disposed between the nanosheet stack structure and the gate line; and a bottom insulating structure interposed between the fin-type active region and the nanosheet stacked structure and integrally connected to the gate dielectric layer.

Drawings

Exemplary embodiments of the inventive concept will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a plan view of an Integrated Circuit (IC) device according to an embodiment;

FIG. 2A is a sectional view taken along line X-X 'of FIG. 1, and FIG. 2B is a sectional view taken along line Y-Y' of FIG. 1;

fig. 3A is an enlarged cross-sectional view of a partial region denoted by "X1" of fig. 2A, and fig. 3B is an enlarged cross-sectional view of a partial region denoted by "Y1" of fig. 2B;

fig. 4A and 4B are sectional views for explaining an IC device according to an embodiment;

fig. 5A and 5B are sectional views for explaining an IC device according to an embodiment;

fig. 6 to 10 are sectional views for explaining an IC device according to an embodiment, respectively;

fig. 11 to 28B are sectional views for explaining a method of manufacturing an IC device according to an embodiment, in which fig. 11, 12A, 13A, 14A, 15A, 16A, 17 to 22, 23A, 24A, 25A, 26A, 27A and 28A are sectional views for explaining a method of manufacturing a part of an IC device, which correspond to a section taken along line X-X 'of fig. 1, and fig. 12B, 13B, 14B, 15B, 16B, 23B, 24B, 25B, 26B, 27B and 28B are sectional views for explaining a method of manufacturing a part of an IC device, which correspond to a section taken along line Y-Y' of fig. 1;

fig. 29A to 29C are sectional views for explaining a method of manufacturing an IC device according to the embodiment;

fig. 30A to 30D are sectional views for explaining a method of manufacturing an IC device according to the embodiment; and

fig. 31A to 31D are sectional views for explaining a method of manufacturing an IC device according to an embodiment.

Detailed Description

The present inventive concept will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the inventive concept are shown. It should be understood that all of the embodiments presented herein are exemplary and do not limit the scope of the inventive concept. Like reference numerals in the drawings denote like elements, and thus the description thereof will be omitted. The embodiments provided in the following description do not preclude association with one or more features of another example or another embodiment also provided herein or not provided herein but consistent with the inventive concept. For example, even if things described in a particular example or embodiment are not described in a different example or embodiment, those things can be understood to relate to or combine with the different example or embodiment unless otherwise mentioned in the description thereof.

It will be understood that when an element or layer is referred to as being "on … …," "over," "on … …," "connected to" or "coupled to" another element or layer, it can be directly on, over, on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly over … …," "directly on … …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. Like reference numerals refer to like elements throughout. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Spatial relationship terms such as "below … …", "below … …", "below", "above … …", "above … …", "above", and the like may be used herein to facilitate description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the term "below … …" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Fig. 1 is a plan view of an Integrated Circuit (IC) device 100 according to an embodiment. Fig. 2A is a sectional view taken along line X-X 'of fig. 1, and fig. 2B is a sectional view taken along line Y-Y' of fig. 1. Fig. 3A is an enlarged cross-sectional view of a partial region denoted by "X1" of fig. 2A, and fig. 3B is an enlarged cross-sectional view of a partial region denoted by "Y1" of fig. 2B.

Referring to fig. 1 to 3B, the IC device 100 includes a plurality of fin active regions FA each protruding from the substrate 102 and extending in the first horizontal direction (X direction) and a plurality of nanosheet stacked structures NSS facing respective upper surfaces FT of the plurality of fin active regions FA at positions separated from the plurality of fin active regions FA.

The substrate 102 may include a semiconductor such as Si or Ge, or a compound semiconductor such as SiGe, SiC, GaAs, InAs, or InP. Trenches T1 defining the plurality of fin-type active areas FA may be formed in the substrate 102 and may be filled with the isolation layer 114. The isolation layer 114 may be formed of an oxide layer, a nitride layer, or a combination thereof.

On the plurality of fin-type active regions FA, each of the plurality of gate lines 160 extends in a second horizontal direction (Y direction) perpendicular to the first horizontal direction (X direction).

In a region where the plurality of fin active regions FA intersect the plurality of gate lines 160, a plurality of nanosheet stack structures NSS may be disposed on each of respective upper surfaces of the plurality of fin active regions FA. The plurality of nanosheet stack structures NSS face the upper surface FT of the fin-type active region FA and are separated from the upper surface FT of the fin-type active region FA by a separation space having a first height H11. The term "height" as used herein means, unless otherwise defined, the dimension in the Z direction, i.e., the thickness in the vertical direction. Each of the plurality of nanosheet stacked structures NSS may comprise a plurality of nanosheets N1, N2, N3 and N4, wherein each nanosheet extends parallel to the upper surface FT of the fin-shaped active region FA.

As shown in fig. 1, each of the plurality of nanosheet stack structures NSS may have a planar area, in the XY plane on the substrate 102, that is greater than the planar area of the area where each fin-type active region FA and each gate line 160 overlap each other. Although the planar shape of each nanosheet stacked structure NSS is approximately rectangular in fig. 1, the embodiments are not limited thereto. Each nanosheet stacked structure NSS may have various planar shapes depending on the planar shape of each fin-type active region FA and the planar shape of each gate line 160.

The plurality of nanosheets N1, N2, N3 and N4 may include first, second, third and fourth nanosheets N1, N2, N3 and N4 sequentially stacked on the upper surface FT of the fin-type active region FA. The first nanosheet N1, which is closest to the fin-type active area FA, among the plurality of nanosheets N1, N2, N3, and N4 may face the upper surface FT of the fin-type active area FA and may be separated from the upper surface with a separation space of the first height H11 disposed therebetween. The second nanosheet N2 may face the upper surface FT of the fin-type active region FA with the first nanosheet N1 disposed therebetween, and may be separated from the first nanosheet N1 by a separation space of a second height H12, the second height H12 being greater than the first height H11. The height of the separation space between the second nanoplatelet N2 and the third nanoplatelet N3 and the height of the separation space between the third nanoplatelet N3 and the fourth nanoplatelet N4 may each be equal or similar to the second height H12.

The present embodiment shows a structure in which a plurality of nanosheet stack structures NSS and a plurality of gate lines 160 are formed on a single fin-type active region FA, and the plurality of nanosheet stack structures NSS are arranged in one row along the first horizontal direction (X-direction) on the single fin-type active region FA. However, according to the present inventive concept, the number of the nanosheet stacked structure NSS disposed on the single fin-type active region FA is not particularly limited. For example, one nanosheet stacked structure NSS may be formed on one fin-type active region FA. Although the present embodiment shows the case where each of the plurality of nanosheet stacked structures NSS includes four nanosheets N1, N2, N3 and N4, the inventive concept is not limited thereto. For example, each of the plurality of nanosheet stacked structures NSS may include at least two nanosheets, and the number of nanosheets included in each nanosheet stacked structure NSS is not particularly limited.

Each of the plurality of nanoplatelets N1, N2, N3, and N4 may have a channel region. Channels may be formed around upper and lower surfaces of each of the second to fourth nanosheets N2, N3 and N4, excluding the first nanosheet N1, among the plurality of nanosheets N1, N2, N3 and N4. The channels may be formed around the upper surface of the first nanoplate N1, but no channels are formed around the lower surface of the first nanoplate N1 facing the fin-type active region FA.

According to some embodiments, each of the plurality of nanoplatelets N1, N2, N3, and N4 may have a thickness in the vertical direction in the range of about 4.5nm to about 5.5 nm. According to some embodiments, the plurality of nanoplatelets N1, N2, N3, and N4 may have substantially the same thickness. The plurality of nanosheets N1, N2, N3, and N4 may be formed of the same material. According to some embodiments, the plurality of nanoplatelets N1, N2, N3, and N4 may be formed from the same material as used to form substrate 102.

The plurality of gate lines 160 may surround at least a portion of the plurality of nanosheets N1, N2, N3 and N4 while overlapping the plurality of nanosheet stack structures NSS on the fin-type active area FA. Each of the plurality of gate lines 160 may include a main gate portion 160M covering an upper surface of each nanosheet stacked structure NSS and extending in the second horizontal direction (Y-direction), and a plurality of sub-gate portions 160S integrally connected to the main gate portion 160M and disposed in the separation spaces between the plurality of nanosheets N1, N2, N3, and N4. In the vertical direction (Z direction), the thickness of each of the plurality of sub-gate portions 160S may be smaller than the thickness of the main gate portion 160M. The plurality of gate lines 160 do not extend to the space between the fin-type active region FA and the first nano-sheet N1, and thus, each of the plurality of gate lines 160 does not have a sub-gate portion disposed between the fin-type active region FA and the first nano-sheet N1. Accordingly, as shown in fig. 2B and 3B, as seen from a cross section in the Y direction, the second to fourth nanosheets N2, N3 and N4, among the plurality of nanosheets N1, N2, N3 and N4, other than the first nanosheet N1, may have a gate-all-around (GAA) structure surrounded by the gate line 160. In contrast, the first nanoplatelets N1 may not have a GAA structure. In more detail, the lower surface of the first nanosheet N1 facing the fin-type active region FA may not be covered by the gate line 160, and only the upper surface of the first nanosheet N1 facing the second nanosheet N2 and both sidewalls thereof in the Y direction may be covered by the gate line 160. Therefore, the region around the upper surface of the first nanosheet N1 facing the second nanosheet N2 and the regions around the two side walls of the first nanosheet N1 in the Y direction may serve as channel regions, but the region around the lower surface of the first nanosheet N1 facing the fin-type active region FA may not serve as channel regions. The space between the first nanoplate N1 and the fin-type active region FA may be filled with a relatively thick bottom insulating structure, so the first nanoplate N1 may constitute a fully depleted device.

The gate line 160 may be formed of metal, metal nitride, metal carbide, or a combination thereof. The metal may be selected from Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er and Pd. The metal nitride may be selected from TiN and TaN. The metal carbide may be TiAlC.

A gate dielectric layer 152 is formed between the nanosheet stack structure NSS and the gate line 160. The gate dielectric layer 152 may cover a surface of each of the plurality of nanosheets N1, N2, N3, and N4 to have a first thickness TH 11. The first thickness TH11 of the gate dielectric layer 152 may be less than the first height H11 of the separation space between the fin-type active region FA and the first nanosheet N1. According to some embodiments, the first thickness TH11 may be less than the first height H11, and may be less than or equal to 1/2 of the first height H11. According to an embodiment, the first thickness TH11 may be greater than 1/2 of the first height H11.

According to some embodiments, gate dielectric layer 152 may be a stack of an interfacial layer and a high-k dielectric layer. The interface layer may be formed of a low dielectric material layer having a dielectric constant of about 9 or less, for example, a silicon oxide layer, a silicon oxynitride layer, or a combination thereof. According to some embodiments, the interfacial layer may not be formed. The high-k dielectric layer may include a material having a dielectric constant greater than that of the silicon oxide layer. For example, the high-k dielectric layer may have a dielectric constant of about 10 to about 25. The high-k dielectric layer may be, but is not limited to being, formed of hafnium oxide.

As shown in fig. 2B and 3B, as seen in a cross section in the Y direction, the second to fourth nanosheets N2, N3 and N4, except for the first nanosheet N1, among the plurality of nanosheets N1, N2, N3 and N4, may be completely surrounded by the gate dielectric layer 152. Only the upper surface of the first nanoplate N1 facing the second nanoplate N2 and both sidewalls of the first nanoplate N1 in the Y direction may be covered by the gate dielectric layer 152.

A plurality of source/drain regions 130 may be formed on the fin-type active region FA. As shown in fig. 2A and 3A, both sidewalls of each of the plurality of nanoplatelets N1, N2, N3, and N4 in the X direction may contact the source/drain region 130. A width of each of the plurality of nanosheets N1, N2, N3 and N4 in the X direction may be defined by a pair of source/drain regions 130 present on either side of the plurality of nanosheets N1, N2, N3 and N4. A lower surface level LV11 of each of the plurality of source/drain regions 130 may be lower than a level LV12 of an upper surface FT of fin-type active region FA. The plurality of source/drain regions 130 may be formed of an epitaxially grown semiconductor layer. For example, the plurality of source/drain regions 130 may be formed of a Si layer, a SiGe layer, or a SiC layer.

The separation space between the lower surface of the first nanosheet N1 and the fin-type active area FA may be filled with a bottom insulating structure 154. The bottom insulating structure 154 may have a structure integrally connected with the gate dielectric layer 152. At least a portion of the bottom insulating structure 154 may include the same material as that included in the gate dielectric layer 152. For example, the bottom insulating structure 154 may include a silicon oxide layer, a high-k dielectric layer having a higher dielectric constant than that of the silicon oxide layer, an air gap, or a combination thereof. The term "air" as used herein may mean atmospheric air or other gases that may be present during the manufacturing process.

The bottom insulating structure 154 may include a first insulating portion 154A filling a separation space between the lower surface of the first nanosheet N1 and the fin-type active area FA, and a second insulating portion 154B extending from the first insulating portion 154A in the second horizontal direction (Y-direction) and interposed between the isolation layer 114 and the gate line 160. The second insulating portion 154B may be formed at both sides of the first insulating portion 154A in the Y direction. The thickness of the second insulating portion 154B in the vertical direction may be smaller than the thickness of the first insulating portion 154A in the vertical direction. The first insulating portion 154A may have a second thickness TH12, the second thickness TH12 being greater than the first thickness TH11 of the gate dielectric layer 152. The second thickness TH12 may be substantially equal to the first height H11. The thickness of the second insulating portion 154B may be substantially equal to the first thickness TH11 of the gate dielectric layer 152. As shown in fig. 2B and 3B, the bottom insulating structure 154 may extend in the Y direction between the substrate 102 and the gate line 160, and may have a variable thickness in the Y direction.

A metal silicide layer 182 may be formed on an upper surface of each of the plurality of source/drain regions 130. The metal silicide layer 182 may be formed of titanium silicide, but the embodiment is not limited thereto. The metal silicide layer 182 may not be formed.

A plurality of first insulating spacers 118 covering sidewalls of the gate line 160 are formed on the plurality of nanosheet stack structures NSS. The plurality of first insulating spacers 118 and the plurality of source/drain regions 130 may be covered by a protective insulating layer 142. The first insulating spacer 118 and the protective insulating layer 142 may cover sidewalls of the main gate portion 160M. Each of the first insulating spacer 118 and the protective insulating layer 142 may be made of SiN, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, SiO₂Or a combination thereof. According to some embodiments, the protective insulating layer 142 may not be formed.

Second insulating spacers 120 in contact with the source/drain regions 130 are formed in the spaces between the plurality of nanosheets N1, N2, N3 and N4. Some second insulating spacers 120 may be interposed between the sub-gate portion 160S and the source/drain regions 130. As shown in fig. 2A, both sidewalls of each of the three sub-gate portions 160S in the IC device 100 may be covered by the second insulating spacer 120 with the gate dielectric layer 152 disposed therebetween. Both sidewalls of the first insulating portion 154A of the bottom insulating structure 154 in the X direction may be covered by the second insulating spacer 120B closest to the fin-type active area FA among the second insulating spacers 120. A second insulating spacer 120B may be interposed between the bottom insulating structure 154 and the source/drain region 130. The thickness of each second insulating spacer 120B in the vertical direction may be less than the thickness of each of the other second insulating spacers 120 in the vertical direction.

The width of the bottom insulating structure 154 in the X direction may be defined by a pair of second insulating spacers 120B covering both sidewalls of the bottom insulating structure 154. The width of the bottom insulating structure 154 in the X direction may be smaller than the width of each of the plurality of nanosheets N1, N2, N3, and N4 in the X direction.

According to some embodiments, the first insulating spacer 118 and the second insulating spacer 120 may be formed of the same material. According to an embodiment, the first insulating spacer 118 and the second insulating spacer 120 may be formed of different materials. According to some embodiments, the second insulating spacer 120 may be made ofSiN、SiCN、SiBN、SiON、SiOCN、SiBCN、SiOC、SiO₂Or a combination thereof. According to an embodiment, the second insulation spacer 120 may include an air gap.

As shown in fig. 2A, an inter-gate insulating layer 144 and an interlayer insulating layer 174 are sequentially formed on the plurality of source/drain regions 130. The inter-gate insulating layer 144 and the interlayer insulating layer 174 may each be formed of a silicon oxide layer.

A plurality of contact plugs 184 may be connected to the plurality of source/drain regions 130 via the plurality of metal silicide layers 182. The plurality of contact plugs 184 may penetrate the interlayer insulating layer 174, the inter-gate insulating layer 144, and the protective insulating layer 142, and may be connected to the plurality of metal silicide layers 182. The plurality of contact plugs 184 may be formed of metal, conductive metal nitride, or a combination thereof. For example, the plurality of contact plugs 184 may each be formed of W, Cu, Al, Ti, Ta, TiN, TaN, an alloy thereof, or a combination thereof.

In the IC device 100 described above with reference to fig. 1 to 3B, a space between the first nanosheet N1, which is closest to the fin-type active region FA, and the fin-type active region FA among the plurality of nanosheets N1, N2, N3, and N4 is filled with the bottom insulating structure 154, and no sub-gate portion is formed between the first nanosheet N1 and the fin-type active region FA. Therefore, formation of an unnecessary channel around the upper surface FT of the fin-type active region FA facing the lower surface of the first nanosheet N1 can be suppressed, and no unnecessary parasitic transistor can be formed around the upper surface FT of the fin-type active region FA. Accordingly, deterioration of electrical characteristics, such as an increase in parasitic capacitance, an increase in leakage current, and an increase in subthreshold swing, which may be caused by parasitic transistors, can be prevented.

Fig. 4A and 4B are sectional views for explaining an IC device 200 according to an embodiment. Fig. 4A is an enlarged cross-sectional view of a region corresponding to the partial region denoted by "X1" of fig. 2A, and fig. 4B is an enlarged cross-sectional view of a region corresponding to the partial region denoted by "Y1" of fig. 2B. The same reference numerals and numerals in fig. 4A and 4B as those in fig. 1 to 3B denote the same elements, and thus their description will be omitted here.

Referring to fig. 4A and 4B, the IC device 200 has almost the same structure as the IC device 100 described above with reference to fig. 1 to 3B. However, the IC device 200 includes a bottom insulating structure 254 instead of the bottom insulating structure 154. The bottom insulating structure 254 may include an air gap 254AG existing in a separation space between the first nanosheets N1 and the fin-type active area FA, a first insulating portion 254A disposed in the separation space and defining the air gap 254AG, and second insulating portions 254B extending from both sides of the first insulating portion 254A in the Y direction. The upper and lower limits of the air gap 254AG may be defined by the first insulating portion 254A.

In the IC device 200, the separation space between the lower surface of the first nanosheet N1 and the fin-type active area FA may have a first height H21. The second nanoplatelets N2 can be separated from the first nanoplatelets N1 by a separation space of a second height H22 that is greater than the first height H21. The first height H21 may be greater than twice the first thickness TH11 of the gate dielectric layer 152.

The first insulating portion 254A may have a second thickness TH22, the second thickness TH22 being greater than the first thickness TH11 of the gate dielectric layer 152. The second thickness TH22 may be substantially equal to the first height H21. Height AH22 of air gap 254AG may be less than or equal to first thickness TH11 of gate dielectric layer 152. The second insulating portion 254B may be interposed between the isolation layer 114 and the gate line 160. The first insulating portion 254A may be integrally connected with the gate dielectric layer 152.

The gate line 160 may include a protrusion 160P protruding toward the air gap 254AG of the bottom insulating structure 254. The width of the air gap 254AG in the Y direction may be defined by the protrusion 160P of the gate line 160. The detailed description of the bottom insulating structure 254 is substantially the same as the detailed description of the bottom insulating structure 154 fabricated above with reference to fig. 1-3B.

Fig. 5A and 5B are sectional views for explaining an IC device 300 according to an embodiment. Fig. 5A is an enlarged cross-sectional view of a region corresponding to the local region denoted by "X1" in fig. 2A, and fig. 5B is an enlarged cross-sectional view of a region corresponding to the local region denoted by "Y1" in fig. 2B. The same reference numerals and numerals in fig. 5A and 5B as those in fig. 1 to 3B denote the same elements, and thus their description will be omitted here.

Referring to fig. 5A and 5B, the IC device 300 has almost the same structure as the IC device 100 described above with reference to fig. 1 to 3B. However, the IC device 300 includes the nanosheet stack configuration NSS3 instead of the nanosheet stack configuration NSS. The nanosheet stacked structure NSS3 may include a plurality of nanosheets N31, N2, N3 and N4. At least some of the plurality of nanoplatelets N31, N2, N3, and N4 can have different thicknesses. For example, a thickness of a first nanosheet N31, which is closest to the fin-type active region FA, among the plurality of nanosheets N31, N2, N3, and N4 in the vertical direction may be less than a thickness of each of the second to fourth nanosheets N2, N3, and N4 in the vertical direction. For example, the first nanoplatelets N31 may have a thickness in the vertical direction that is in the range of about 1nm to about 3 nm. The detailed description of the first nanosheet N31 is substantially the same as that described above with reference to fig. 1-3B for the first nanosheet N1.

Fig. 6 is a sectional view for explaining an IC device 400 according to an embodiment. Fig. 6 shows a cross-sectional structure of a portion of the IC device 400, which corresponds to a cross-section taken along line X-X' of fig. 1. The same reference numerals and numerals in fig. 6 as those in fig. 1 to 3B denote the same elements, and thus their description will be omitted here.

Referring to fig. 6, the IC device 400 has almost the same structure as that of the IC device 100 described above with reference to fig. 1 to 3B. However, the IC device 400 does not include the second insulating spacer 120 included in the IC device 100, and includes a plurality of gate lines 460 instead of the plurality of gate lines 160, and includes a gate dielectric layer 452 instead of the gate dielectric layer 152.

Each of the plurality of gate lines 460 may include a main gate portion 460M covering an upper surface of each nanosheet stacked structure NSS and extending in the Y direction, and a plurality of sub-gate portions 460S integrally connected with the main gate portion 460M thereof and disposed within the partitioned spaces between the plurality of nanosheets N1, N2, N3 and N4. In the vertical direction, the thickness of each of the plurality of sub-gate portions 460S may be smaller than the thickness of the main gate portion 460M. Each of the plurality of gate lines 460 does not include a sub-gate portion disposed between the fin-type active region FA and the first nanosheet N1.

In the X direction, a width SGW of each of the plurality of sub-gate portions 460S may be greater than a width MGW of the main gate portion 460M. Each of the plurality of sub-gate portions 460S may be separated from the source/drain regions 130 with the gate dielectric layer 452 disposed therebetween.

The space between the lower surface of the first nanosheet N1 and the fin-type active region FA may be filled with a bottom insulating structure 454. The bottom insulation structure 454 may have a structure integrally connected with the gate dielectric layer 452. The width of the bottom insulating structure 454 in the X direction may be equal to or similar to the width of each of the plurality of nanosheets N1, N2, N3, and N4 in the X direction. In the X direction, both sidewalls of the bottom insulating structure 454 may contact a pair of source/drain regions 130 disposed at both sides of the gate line 460. A width 454W of the bottom insulating structure 454 in the X direction may be defined by a pair of source/drain regions 130. A width 454W of the bottom insulating structure 454 in the X direction may be greater than a width SGW of each of the plurality of sub-gate portions 460S. The detailed description of the gate line 460, the gate dielectric layer 452, and the bottom insulating structure 454 is substantially the same as the detailed description of the gate line 160, the gate dielectric layer 152, and the bottom insulating structure 154 described above with reference to fig. 1 through 3B.

Fig. 7 is a sectional view for explaining an IC device 500 according to an embodiment. Fig. 7 shows a cross-sectional structure of a portion of the IC device 500, which corresponds to a cross-section taken along line X-X' in fig. 1. The same reference numerals and numerals in fig. 7 as those in fig. 1 to 3B denote the same elements, and thus their description will be omitted here.

Referring to fig. 7, the IC device 500 has almost the same structure as that of the IC device 100 described above with reference to fig. 1 to 3B. However, in the IC device 500, a plurality of source/drain regions 530 are formed on the fin-type active region FA.

Two sidewalls of each of the second to fourth nanosheets N2, N3 and N4 among the plurality of nanosheets N1, N2, N3 and N4 included in each nanosheet stacked structure NSS may contact the plurality of source/drain regions 530. An upper surface of the first nanoplate N1 may contact a lower surface of each of the plurality of source/drain regions 530. The first nanoplate N1 may include portions that vertically overlap the plurality of source/drain regions 530. The thickness of the portion of the first nanoplate N1 vertically overlapped by the plurality of source/drain regions 530 may be less than the thickness of the portion of the first nanoplate N1 vertically overlapped by each gate line 160. According to some embodiments, the thickness of the first nanoplatelet N1 may be different from the thickness of each of the second to fourth nanoplatelets N2, N3 and N4. For example, the thickness of the first nanoplatelet N1 may be less than the thickness of each of the second to fourth nanoplatelets N2, N3 and N4. For example, each of the second to fourth nanoplatelets N2, N3, and N4 may have a thickness in the range of about 4.5nm to about 5.5nm, and the first nanoplatelet N1 may have a thickness in the range of about 1nm to about 3 nm. According to an embodiment, the thickness of the first nanoplatelet N1 may be substantially equal to or similar to the thickness of each of the second to fourth nanoplatelets N2, N3 and N4.

The IC device 500 may include a bottom insulating structure 554 extending in the X-direction on the upper surface FT of the fin-type active region FA. The bottom insulating structure 554 may include a first insulating portion 554A filling a space between the first nanosheet N1 and the fin-type active region FA, second insulating portions 154B (see fig. 2B) extending from both sides of the first insulating portion 554A in the Y-direction and interposed between the isolation layer 114 and the gate line 160, and third insulating portions 554C extending from both sides of the first insulating portion 554A in the X-direction and interposed between the fin-type active region FA and the source/drain region 530. The first and third insulating portions 554A and 554C may be integrally connected to each other and may have substantially the same thickness as each other. The thickness of each of the first and third insulating portions 554A and 554C may be greater than the thickness of the second insulating portion 154B (see fig. 2B), and may be greater than the thickness of the gate dielectric layer 152. The bottom insulating structure 554 may have a structure integrally connected with the gate dielectric layer 152.

The lower surface level of each of the plurality of source/drain regions 530 may be higher than the upper surface level of the bottom insulating structure 554. The bottom insulating structure 554 may be separated from the source/drain regions 530 with the first nanoplate N1 disposed therebetween. One bottom insulating structure 554 may be disposed on one fin-type active region FA, and a plurality of nanosheet stack structures NSS, a plurality of gate lines 160, and a plurality of source/drain regions 530 may be disposed on a single bottom insulating structure 554 on a single fin-type active region FA. Reference may be made to the description of bottom insulating structure 154 and source/drain regions 130 above with reference to fig. 1-3B in order to describe the materials used to form bottom insulating structure 554 and source/drain regions 530.

Similar to the IC device 100 described above with reference to fig. 1-3B, the IC device 500 may include a second insulating spacer 120 formed in the space between the plurality of nanoplatelets N1, N2, N3, and N4 and contacting the source/drain regions 530. However, in contrast to the IC device 100, the IC device 500 may not include the second insulating spacer 120B disposed between the fin-type active region FA and the first nanoplate N1.

Fig. 8 is a sectional view for explaining an IC device 500 according to an embodiment. Fig. 8 shows a cross-sectional structure of a portion of the IC device 600, which corresponds to a cross-section taken along line X-X' in fig. 1. The same reference numerals and numerals in fig. 8 as those in fig. 1 to 3B denote the same elements, and thus their description will be omitted here.

Referring to fig. 8, an IC device 600 has almost the same structure as the IC device 500 described above with reference to fig. 7. However, the IC device 600 may include a bottom insulating structure 654. The bottom insulating structure 654 may include first insulating portions 654A filling spaces between the first nanosheets N1 and the fin-type active regions FA, second insulating portions 154B (see fig. 2B) extending from both sides of the first insulating portions 654A in the Y-direction and interposed between the isolation layer 114 and the gate lines 160, and third insulating portions 654C extending from both sides of the first insulating portions 654A in the X-direction and interposed between the fin-type active regions FA and the source/drain regions 530. The first and third insulating portions 654A and 654C may be integrally connected to each other and may have substantially the same thickness as each other. The thickness of each of the first and third insulating portions 654A and 654C may be greater than the thickness of the second insulating portion 154B (see fig. 2B), and may be greater than the thickness of the gate dielectric layer 152. The bottom insulating structure 654 may have a structure integrally connected with the gate dielectric layer 152.

A lower surface level of each of the plurality of source/drain regions 530 may be higher than an upper surface level of the bottom insulating structure 654. The bottom insulating structure 654 may be separated from the source/drain regions 530 with the first nanoplate N1 disposed therebetween. A plurality of bottom insulating structures 654 may be disposed on the single fin active region FA. One nanosheet stack structure NSS and one gate line 160 may be disposed on a single bottom insulating structure 654 on a single fin-type active region FA. Reference may be made to the detailed description of the bottom insulating structure 154 made above with reference to fig. 1-3B to illustrate the material used to form the bottom insulating structure 654.

The semiconductor pattern 604 may be interposed between the upper surface FT of the fin-type active region FA and the source/drain region 530. The width of the bottom insulating structure 654 in the X direction may be defined by the semiconductor pattern 604. Each source/drain region 530 may be separated from the fin-type active region FA with the semiconductor pattern 604 and the first nanosheet N1 disposed therebetween. Semiconductor pattern 604 may be formed of a material different from the material used to form first nanoplatelets N1. According to some embodiments, the semiconductor pattern 604 may be formed of SiGe.

Fig. 9 is a sectional view for explaining an IC device 700 according to an embodiment. Fig. 9 shows a cross-sectional structure of a portion of the IC device 700, which corresponds to a cross-section taken along line X-X' in fig. 1. The same reference numerals and numerals in fig. 9 as those in fig. 1 to 3B denote the same elements, and thus their description will be omitted here.

Referring to fig. 9, the IC device 700 has almost the same structure as the IC device 100 described above with reference to fig. 1 to 3B. However, in the IC device 700, a plurality of source/drain regions 730 are formed on the fin-type active region FA. Both sidewalls of each of the plurality of nanoplatelets N1, N2, N3, and N4 may contact the plurality of source/drain regions 730.

According to some embodiments, the thickness of the first nanoplatelet N1 may be different from the thickness of each of the second to fourth nanoplatelets N2, N3 and N4. For example, the thickness of the first nanoplatelet N1 may be less than the thickness of each of the second to fourth nanoplatelets N2, N3 and N4. According to an embodiment, the thickness of the first nanoplatelet N1 may be substantially equal to or similar to the thickness of each of the second to fourth nanoplatelets N2, N3 and N4.

The IC device 700 may include a bottom insulating structure 754 extending in the X-direction on the upper surface FT of the fin-type active region FA. The bottom insulating structure 754 may include first insulating portions 754A filling spaces between the first nanosheets N1 and the fin-type active regions FA, second insulating portions 154B (see fig. 2B) extending from both sides of the first insulating portions 754A in the Y-direction and interposed between the isolation layer 114 and the gate lines 160, and third insulating portions 754C extending from both sides of the first insulating portions 754A in the X-direction and interposed between the fin-type active regions FA and the source/drain regions 730. The first and third insulating portions 754A and 754C may be integrally connected to each other, and a thickness of the third insulating portion 754C may be less than a thickness of the first insulating portion 754A. The bottom insulation structure 754 may have a structure integrally connected with the gate dielectric layer 152.

An upper surface of bottom insulating structure 754 may contact a lower surface of each of the plurality of source/drain regions 730. A thickness of a portion of the bottom insulating structure 754 vertically overlapped by the plurality of source/drain regions 730 may be less than a thickness of a portion of the bottom insulating structure 754 vertically overlapped by each gate line 160. A lower surface level of each of the plurality of source/drain regions 730 may be higher than a level of an upper surface FT of the fin-type active region FA. One bottom insulating structure 754 may be disposed on one fin-type active region FA, and a plurality of nanosheet stack structures NSS, a plurality of gate lines 160, and a plurality of source/drain regions 730 may be disposed on a single bottom insulating structure 754 on a single fin-type active region FA. Reference may be made to the description of bottom insulating structure 154 and source/drain regions 130 above with reference to fig. 1-3B to illustrate the materials used to form bottom insulating structure 754 and source/drain regions 730.

Similar to the IC device 100 described above with reference to fig. 1-3B, the IC device 700 may include a second insulating spacer 120 formed in the space between the plurality of nanoplatelets N1, N2, N3, and N4 and contacting the source/drain regions 730. However, in contrast to the IC device 100, the IC device 700 may not include the second insulating spacer 120B disposed between the fin-type active region FA and the first nanoplate N1.

Fig. 10 is a sectional view for explaining an IC device 800 according to other embodiments. Fig. 10 shows a cross-sectional structure of a portion of the IC device 800, which corresponds to a cross-section taken along line X-X' in fig. 1. The same reference numerals and numerals in fig. 10 as those in fig. 1 to 3B denote the same elements, and thus their description will be omitted here.

Referring to fig. 10, an IC device 800 has almost the same structure as the IC device 700 described above with reference to fig. 9. However, the IC device 800 may include a bottom insulating structure 854 extending in the X direction on the upper surface FT of the fin-type active area FA. The bottom insulating structure 854 may include first insulating portions 854A filling spaces between the first nanosheets N1 and the fin-type active regions FA, second insulating portions 154B (see fig. 2B) extending from both sides of the first insulating portions 854A in the Y-direction and interposed between the isolation layer 114 and the gate lines 160, and third insulating portions 854C extending from both sides of the first insulating portions 854A in the X-direction and interposed between the fin-type active regions FA and the source/drain regions 730. The first and third insulating portions 854A and 854C may be integrally connected to each other, and a thickness of the third insulating portion 854C may be less than a thickness of the first insulating portion 854A. The bottom insulating structure 854 may have a structure integrally connected with the gate dielectric layer 152.

A lower surface level of each of the plurality of source/drain regions 730 may be higher than a level of an upper surface FT of the fin-type active region FA. The bottom insulating structure 854 may contact the source/drain regions 730. A plurality of bottom insulating structures 854 may be disposed on the single fin-type active region FA. One nanosheet stack structure NSS and one gate line 160 may be disposed on a single bottom insulating structure 854 on a single fin-type active area FA. Reference may be made to the detailed description of the bottom insulating structure 154 made above with reference to fig. 1-3B to illustrate the material used to form the bottom insulating structure 854.

The semiconductor pattern 804 may be interposed between the upper surface FT of the fin-type active region FA and the source/drain region 730. A width of the bottom insulating structure 854 in the X direction may be defined by the semiconductor pattern 804. Each of the source/drain regions 730 may be separated from the fin-type active region FA with the semiconductor pattern 804 disposed therebetween. The semiconductor pattern 804 may be formed of a material different from that used to form the first nanosheet N1. According to some embodiments, the semiconductor pattern 804 may be formed of SiGe.

In the IC devices 200, 300, 400, 500, 600, 700, and 800 described above with reference to fig. 4A to 10, spaces between the fin-type active regions FA and the first nanosheets N1 and N31, which are closest to the fin-type active regions FA, among the plurality of nanosheets N1, N2, N3, and N4 and among the plurality of nanosheets N31, N2, N3, and N4, are filled with the bottom insulating structures 154, 254, 454, 554, 654, 754, and 854, and the gate lines 160 and 460 do not include the sub-gate portions disposed between the first nanosheets N1 and N31 and the fin-type active regions FA. Therefore, it is possible to suppress formation of an unnecessary channel around the upper surface FT of the fin-type active region FA facing the first nanosheets N1 and N31, and thus unnecessary parasitic transistors are not formed. Therefore, deterioration of electrical characteristics due to the parasitic transistor can be prevented.

Fig. 11 to 28B are sectional views for explaining a method of manufacturing an IC device according to the embodiment. A method of manufacturing the IC device 100 of fig. 1 to 3B will now be described with reference to fig. 11 to 28B. Fig. 11, fig. 12A, fig. 13A, fig. 14A, fig. 15A, fig. 16A, fig. 17 to 22, fig. 23A, fig. 24A, fig. 25A, fig. 26A, fig. 27A, and fig. 28A are sectional views for explaining a method of manufacturing a part of the IC device 100, which correspond to sectional views taken along the X-X 'line of fig. 1, and fig. 12B, fig. 13B, fig. 14B, fig. 15B, fig. 16B, fig. 23B, fig. 24B, fig. 25B, fig. 26B, fig. 27B, and fig. 28B are sectional views for explaining a method of manufacturing a part of the IC device 100, which correspond to sectional views taken along the Y-Y' line in fig. 1. The same reference numerals and numerals in fig. 11 to 28B as those in fig. 1 to 3B denote the same elements, and thus their description will be omitted here.

Referring to fig. 11, a plurality of sacrificial semiconductor layers 104 and a plurality of nanosheet semiconductor layers NS are alternately stacked on a substrate 102.

A height of the sacrificial semiconductor layer 104B closest to the substrate 102 among the plurality of sacrificial semiconductor layers 104 may be less than a height of each other sacrificial semiconductor layer 104. According to an embodiment, the height of the sacrificial semiconductor layer 104B closest to the substrate 102 may be less than or equal to 1/2 of each other sacrificial semiconductor layer 104.

According to an embodiment, the semiconductor material forming the plurality of sacrificial semiconductor layers 104 may be the same as or different from the semiconductor material forming the plurality of nanosheet semiconductor layers NS. According to an embodiment, the plurality of sacrificial semiconductor layers 104 may be formed of SiGe and the plurality of nanosheet semiconductor layers NS may be formed of Si. According to an embodiment, the sacrificial semiconductor layer 104B closest to the substrate 102 among the plurality of sacrificial semiconductor layers 104 may be formed of a material having an etch selectivity different from that of each other sacrificial semiconductor layer 104. For example, each of the plurality of sacrificial semiconductor layers 104 may be formed of a SiGe layer, but the Ge content ratio of the sacrificial semiconductor layer 104B closest to the substrate 102 may be different from the Ge content ratios of the other sacrificial semiconductor layers 104.

Referring to fig. 12A and 12B, a mask pattern MP is formed on the stack of the plurality of sacrificial semiconductor layers 104 and the plurality of nanosheet semiconductor layers NS. The mask pattern MP may be formed of a plurality of line patterns, each of which extends parallel to each other in the X direction. The mask pattern MP may include a pad oxide layer pattern 512 and a hard mask pattern 514. The hard mask pattern 514 may be formed of silicon nitride, polysilicon, a spin-on hard mask (SOH) material, or a combination thereof. The SOH material may be formed from hydrocarbon compounds having a relatively high carbon content of about 85 to about 99 weight ratios based on the total weight of the SOH material.

Referring to fig. 13A and 13B, a trench T1 is formed by partially etching the plurality of sacrificial semiconductor layers 104, the plurality of nanosheet semiconductor layers NS, and the substrate 102 using the mask pattern MP as an etching mask. As a result, the plurality of fin-type active regions FA defined by the trenches T1 are formed, and the stack of the plurality of sacrificial semiconductor layers 104 and the plurality of nanosheet semiconductor layers NS remains on each of the plurality of fin-type active regions FA.

Referring to fig. 14A and 14B, an isolation layer 114 is formed within the trench T1.

Referring to fig. 15A and 15B, the mask pattern MP is removed from the resultant structure of fig. 14A and 14B, and a recess process for partially removing the isolation layer 114 is performed such that the upper surface of the isolation layer 114 may be at a level substantially the same as or similar to that of the upper surface FT of the fin-type active region FA.

Referring to fig. 16A and 16B, a plurality of dummy gate structures DGS are formed on the plurality of fin-type active regions FA. Each of the plurality of dummy gate structures DGS may extend in a direction crossing a direction in which each of the plurality of fin active areas FA extends. Each of the plurality of dummy gate structures DGS may have a structure in which an oxide layer D112, a dummy gate layer D114, and a capping layer D116 are sequentially stacked. According to some embodiments, the dummy gate layer D114 may be formed of polysilicon and the capping layer D116 may be formed of a silicon nitride layer.

Referring to fig. 17, first insulating spacers 118 are formed to cover respective two sidewalls of the plurality of dummy gate structures DGS. The first insulating spacer 118 may be formed of a single layer or a plurality of layers of SiN, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, SiO₂Or a combination thereof.

A plurality of recess regions R1 exposing the upper surface of the fin-type active region FA are formed by partially etching away the plurality of sacrificial semiconductor layers 104 and the plurality of nanosheet semiconductor layers NS using the plurality of dummy gate structures DGS and the plurality of first insulating spacers 118 as an etch mask. A lower surface level of each of the plurality of recess regions R1 may be lower than a level of an upper surface FT of the fin-type active region FA.

After forming the plurality of recessed regions R1, the plurality of nanosheet semiconductor layers NS may be separated into the plurality of nanosheet stacked structures NSs each including the plurality of nanosheets N1, N2, N3, and N4.

Referring to fig. 18, recessed (indexed) regions 104D are formed between the plurality of nanosheets N1, N2, N3 and N4 of each nanostructure NSS by partially removing portions of the plurality of sacrificial semiconductor layers 104 exposed on respective sides of the plurality of nanosheet stack structures NSS via isotropic etching. The height (dimension in the Z direction) of the recessed area 104D closest to the fin-type active area FA among the plurality of recessed areas 104D may be smaller than the height of each of the other recessed areas 104D.

According to some embodiments, the difference between the etch selectivity of the plurality of sacrificial semiconductor layers 104 and the etch selectivity of the plurality of nanoplatelets N1, 2, N3, and N4 may be utilized during the isotropic etch process for forming the plurality of recessed regions 104D. The isotropic etching process may be performed in a dry or wet manner.

Referring to fig. 19, the plurality of second insulating spacers 120 are formed to fill the plurality of recessed regions 104D of fig. 18. The height of the second insulating spacer 120B closest to the fin active area FA among the plurality of second insulating spacers 120 may be less than the height of each of the other plurality of second insulating spacers 120.

The plurality of second insulation spacers 120 may be formed by Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), oxidation, or a combination thereof.

Referring to fig. 20, the plurality of source/drain regions 130 are formed by epitaxially growing a semiconductor material from the respective exposed two sidewalls of the plurality of nanosheets N1, N2, N3, and N4 and the exposed surface of the fin-type active region FA.

Referring to fig. 21, a protective insulating layer 142 is formed to cover the resultant structure in which the plurality of source/drain regions 130 have been formed, and an inter-gate insulating layer 144 is formed on the protective insulating layer 142, and then, the protective insulating layer 142 and the inter-gate insulating layer 144 are planarized to expose the upper surface of the capping layer D116.

Referring to fig. 22, by removing the capping layer D116 from the resultant structure of fig. 21, the dummy gate layer D114 is exposed, and the protective insulating layer 142 and the inter-gate insulating layer 144 are partially removed such that the upper surface of the inter-gate insulating layer 144 is at substantially the same level as the upper surface of each dummy gate layer D114.

Referring to fig. 23A and 23B, a gate space GS is provided by removing the dummy gate layer D114 and the oxide layer D112 under the dummy gate layer D114 from the resultant structure of fig. 22, and the plurality of nanosheet-stacked structures NSS are exposed through the gate space GS.

Referring to fig. 24A and 24B, the plurality of sacrificial semiconductor layers 104 remaining on the fin-type active region FA are removed via the gate spaces GS, and thus the gate spaces GS are extended to spaces between the plurality of nanosheets N1, N2, N3 and N4. The plurality of nanosheets N1, N2, N3 and N4 may be exposed via the extended gate space GS. The insulating space INS may be formed between the lower surface of the first nanosheet N1 and the upper surface FT of the fin-type active area FA.

Referring to fig. 25A and 25B, a gate dielectric layer 152 and a bottom insulating structure 154 are formed to cover the plurality of nanosheets N1, N2, N3 and N4 and the exposed surfaces of the fin-type active area FA.

According to an embodiment, the gate dielectric layer 152 and the bottom insulation structure 154 may be formed simultaneously. At least a portion of the bottom insulating structure 154 may be formed of the same material used to form the gate dielectric layer 152. The gate dielectric layer 152 and the bottom insulating structure 154 may be formed by ALD.

When the vertical separation distance between the upper surface of the fin-type active region FA and the first nanosheet N1 is less than or equal to 1/2 the vertical separation distance between the first to fourth nanosheets N1, N2, N3 and N4, the separation space between the upper surface FT of the fin-type active region FA and the first nanosheet N1 may be filled with the bottom insulating structure 154 while the gate dielectric layer 152 is formed between the first to fourth nanosheets N1, N2, N3 and N4. As shown in fig. 25B, the bottom insulating structure 154 may be formed to include a first insulating portion 154A filling the space between the fin-type active region FA and the first nanosheet N1, and a second insulating portion 154B covering the isolation layer 114.

Referring to fig. 26A and 26B, a gate-forming conductive layer 160L is formed to cover the upper surface of the inter-gate insulating layer 144 while filling the gate space GS on the gate dielectric layer 152 and the bottom insulating structure 154 (see fig. 25A and 25B).

The gate forming conductive layer 160L may be formed of metal, metal nitride, metal carbide, or a combination thereof. The gate electrode may be formed via ALD to form the conductive layer 160L.

Referring to fig. 27A and 27B, the plurality of gate lines 160 are formed by partially removing the gate-forming conductive layer 160L from the upper surface thereof until the upper surface of the inter-gate insulating layer 144 is exposed, starting from the resultant structure of fig. 26A and 26B. The plurality of gate lines 160 may include a main gate portion 160M and the plurality of sub-gate portions 160S. Since the space between the fin-type active region FA and the first nanosheet N1 is filled with the bottom insulating structure 154, the gate line 160 may not extend to the space between the upper surface FT of the fin-type active region FA and the first nanosheet N1. Since the planarization is performed while the plurality of gate lines 160 are formed, the respective heights of the protective insulating layer 142 and the inter-gate insulating layer 144 may be reduced.

Referring to fig. 28A and 28B, a plurality of contact holes 180 exposing the plurality of source/drain regions 130 are formed by forming an interlayer insulating layer 174 covering the plurality of gate lines 160 and then partially etching the interlayer insulating layer 174 and the inter-gate insulating layer 144. A metal silicide layer 182 is formed on respective upper surfaces of the plurality of source/drain regions 130 exposed through the plurality of contact holes 180, and contact plugs 184 are formed to fill the contact holes 180. In this way, the IC device 100 of fig. 1 to 3B can be formed.

According to the IC device manufacturing method described above with reference to fig. 11 to 28B, when the gate dielectric layer 152 is being formed on the respective surfaces of the first to fourth nanosheets N1, N2, N3 and N4, the bottom insulating structure 154 having a thickness greater than the gate dielectric layer 152 in the vertical direction can be easily formed within the space between the fin-type active region FA and the first nanosheet N1. Therefore, formation of an unnecessary channel around the upper surface FT of the fin-type active region FA facing the lower surface of the first nanosheet N1 can be suppressed, and hence deterioration of electrical characteristics can be suppressed.

The IC device 200 of fig. 4A and 4B may be fabricated according to the method described above with reference to fig. 11-28B. However, in the process of fig. 11, the sacrificial semiconductor layer 104B closest to the substrate 102 among the plurality of sacrificial semiconductor layers 104 may be formed to have a height smaller than that of each other sacrificial semiconductor layer 104 and larger than twice the first thickness TH11 of the gate dielectric layer 152. In addition, in the process of fig. 25A and 25B, the bottom insulating structure 254 of fig. 4A and 4B may be formed instead of the bottom insulating structure 154. The first and second insulating portions 254A and 254B may be formed simultaneously with the formation of the gate dielectric layer 152. While the first insulating portions 254A are formed, air gaps 254AG whose upper and lower limits are defined by the first insulating portions 254A may be formed in the spaces between the first nanosheets N1 and the fin-type active regions FA. Thereafter, the gate line 160 may be formed according to the method described above with reference to fig. 26A to 27B. While each gate line 160 is formed, a portion of the material for forming the gate line 160 flows to an empty space between the lower surface of the first nanosheet N1 and the fin-type active region FA, thus forming the protrusion 160P of the gate line 160. Accordingly, the Y-direction width of air gap 254AG may be defined by protrusion 160P.

The IC device 300 of fig. 5A and 5B may be fabricated according to the method described above with reference to fig. 11-28B. However, in the process of fig. 11, the nanosheet semiconductor layer NS, which is closest to the substrate 102, among the plurality of nanosheet semiconductor layers NS, may be formed to have a height (dimension in the Z direction) that is greater than the height of each of the other nanosheet semiconductor layers NS.

Fig. 29A to 29C are sectional views for explaining a method of manufacturing an IC device according to the embodiment. A method of manufacturing the IC device 400 of fig. 6 will now be described with reference to fig. 29A to 29C. Fig. 29A to 29C show a cross-sectional structure of a part of an IC device 400 according to a manufacturing process, which corresponds to a cross section taken along the line X-X' of fig. 1. The same reference numerals and numerals in fig. 29A to 29C as those in fig. 1 to 28B denote the same elements, and thus their description will be omitted here.

Referring to fig. 29A, the first insulating spacers 118 covering the respective both sidewalls of the plurality of dummy gate structures DGS are formed according to the method described above with reference to fig. 11 to 17, the plurality of recess regions R1 are formed to expose the upper surface of the fin-type active region FA, and then the plurality of source/drain regions 130 are formed on the fin-type active region FA within the plurality of recess regions R1 according to the method described above with reference to fig. 20. The plurality of source/drain regions 130 may be formed to contact sidewalls of the plurality of sacrificial semiconductor layers 104, respectively.

Referring to fig. 29B, a gate space GS4 is formed by performing the process described above with reference to fig. 21 to 24B with respect to the resultant structure of fig. 29A, and the plurality of nanosheets N1, N2, N3 and N4 are exposed through the gate space GS 4. An insulating space INS4 may be formed between the first nanosheet N1 and the fin-type active region FA.

Referring to fig. 29C, the bottom insulating structure 454 and the gate dielectric layer 452 filling the insulating space INS4 of fig. 29B are simultaneously formed and the plurality of gate lines 460 are formed by performing the processes described above with reference to fig. 25A to 27B with respect to the resultant structure of fig. 29B. Thereafter, the IC device 400 of fig. 6 may be fabricated according to the process described above with reference to fig. 28A and 28B.

Fig. 30A to 30D are sectional views for explaining a method of manufacturing an IC device according to an embodiment of the inventive concept. A method of manufacturing the IC device 500 of fig. 7 will now be described with reference to fig. 30A to 30D. Fig. 30A to 30D show a cross-sectional structure of a part of an IC device 500 according to a manufacturing process, which corresponds to a cross section taken along the line X-X' of fig. 1. The same reference numerals and numerals in fig. 30A to 30D as those in fig. 1 to 28B denote the same elements, and thus their description will be omitted here.

Referring to fig. 30A, first insulating spacers 118 covering respective both sidewalls of the plurality of dummy gate structures DGS are formed according to a method similar to that described above with reference to fig. 11 to 17, and a plurality of recess regions R5 are formed to expose an upper surface of the fin-type active region FA. However, as compared with the plurality of recess regions R1 of fig. 17, the lower surface level of each of the plurality of recess regions R5 may be higher than the lower surface level of the first nanosheet N1, which is closest to the fin-type active region FA, among the plurality of nanosheets N1, N2, N3, and N4. First nanoplatelets N1 may be exposed on a lower surface of each of the plurality of recessed regions R5.

Referring to fig. 30B, the plurality of second insulating spacers 120 are formed according to a method similar to the method described above with reference to fig. 18 and 19. However, the second insulating spacers 120B are not formed between the fin-type active region FA and the first nanosheets N1.

Referring to fig. 30C, the plurality of source/drain regions 530 are formed within the plurality of recessed regions R5 on the first nanoplate N1 according to a method similar to that described above with reference to fig. 20.

Referring to fig. 30D, the IC device 500 of fig. 7 may be fabricated by performing processes similar to those described above with reference to fig. 21 through 28B with respect to the resulting structure of fig. 30C. Specifically, when the plurality of sacrificial semiconductor layers 104 remaining on the fin-type active region FA are removed via the gate spaces GS according to the process described in fig. 24A and 24B above, the sacrificial semiconductor layers 104B remaining in the resulting structure of fig. 30C are removed. An insulating space (not shown) exposing the upper surface FT of the fin-type active region FA may be formed. The insulating space may extend to a portion of the area between the fin-shaped active region FA and the first nanosheet N1, which vertically overlaps each of the source/drain regions 530. Bottom insulating structures 554 may be formed within the insulating spaces while forming gate dielectric layer 152 according to the process described above with reference to fig. 25A and 25B. The bottom insulating structure 554 may be formed to extend to the portion of the region between the fin-type active region FA and the first nanosheet N1, which vertically overlaps each of the source/drain regions 530.

The IC device 600 of fig. 8 may be fabricated according to the process described above with reference to fig. 30A-30D. However, the bottom insulating structure 654 may be formed instead of the bottom insulating structure 554 in the process described above with reference to fig. 30D. For this reason, while the plurality of sacrificial semiconductor layers 104 remaining on the fin-type active region FA are removed via the gate spaces GS according to the process described above in fig. 24A and 24B, only a portion of the sacrificial semiconductor layer 104B remaining in the resultant structure of fig. 30C may be removed, and the remaining portion of the sacrificial semiconductor layer 104B may remain as the semiconductor pattern 604 between the fin-type active region FA and the source/drain region 530. As a result, a plurality of insulating spaces (not shown) whose width in the X direction is defined by the plurality of semiconductor patterns 604 may be formed between the fin-type active region FA and the first nanosheet N1. The insulating space may extend to a portion of the region between the fin-type active region FA and the first nanosheet N1, which vertically overlaps the source/drain region 530. A plurality of bottom insulating structures 654 may be formed within the plurality of insulating spaces while forming the gate dielectric layer 152 according to the process described above with reference to fig. 25A and 25B.

Fig. 31A to 31D are sectional views for explaining a method of manufacturing an IC device according to an embodiment. A method of manufacturing the IC device 700 of fig. 9 will now be described with reference to fig. 31A to 31D. Fig. 31A to 31D show a cross-sectional structure of a part of the IC device 500 according to the manufacturing process, which corresponds to a cross section taken along the line X-X' of fig. 1. The same reference numerals and numerals in fig. 31A to 31D as those in fig. 1 to 28B denote the same elements, and thus their description will be omitted here.

Referring to fig. 31A, first insulating spacers 118 covering respective both sidewalls of the plurality of dummy gate structures DGS are formed according to a method similar to that described above with reference to fig. 11 to 17, and a plurality of recess regions R7 are formed to expose upper surfaces of the fin-type active regions FA. However, in comparison with the plurality of recess regions R1 of fig. 17, a lower surface level of each of the plurality of recess regions R7 may be higher than a level of an upper surface FT of the fin-type active region FA. The sacrificial semiconductor layer 104B closest to the substrate 102 among the plurality of sacrificial semiconductor layers 104 may be exposed on the lower surface of each of the plurality of recess regions R7.

Referring to fig. 31B, the plurality of second insulating spacers 120 are formed according to a method similar to the method described above with reference to fig. 18 and 19. However, the second insulating spacer 120B is not formed between the fin-type active region FA and the first nanosheet N1.

According to an embodiment, the sacrificial semiconductor layer 104B closest to the substrate 102 among the plurality of sacrificial semiconductor layers 104 may be formed of a material having an etch selectivity different from that of each other sacrificial semiconductor layer 104. In this case, while the plurality of recessed regions 104D are formed between the plurality of nanosheets N1, N2, N3 and N4 to form the plurality of second insulating spacers 120 as described above with reference to fig. 18, the consumption of the sacrificial semiconductor layer 104B exposed on the lower surface of each recessed region R7 may be minimized, and thus, the fin-type active region FA may not be exposed on the lower surface of each recessed region R7.

According to an embodiment, the sacrificial semiconductor layer 104B closest to the substrate 102 among the plurality of sacrificial semiconductor layers 104 may be formed of the same material as that used to form the other sacrificial semiconductor layers 104. In this case, while the plurality of recessed regions 104D are formed between the plurality of nanosheets N1, N2, N3 and N4 as described above with reference to fig. 18, the sacrificial semiconductor layer 104B exposed on the lower surface of each recessed region R7 may also be etched, and thus the fin-type active region FA may be exposed on the lower surface of each recessed region R7. In this case, in a process which will be described later with reference to fig. 31C, a source/drain region (not shown) having a lower surface in contact with the fin-type active region FA may be obtained instead of the source/drain region 730.

Referring to fig. 31C, the plurality of source/drain regions 730 are formed in the plurality of recessed regions R7 on the sacrificial semiconductor layer 104B by performing a method similar to that described above with reference to fig. 20 with respect to the resulting structure of fig. 31B.

Referring to fig. 31D, the IC device 700 of fig. 9 may be fabricated by performing a process similar to that described above with reference to fig. 21 through 28B with respect to the resulting structure of fig. 31C. Specifically, while the plurality of sacrificial semiconductor layers 104 remaining on the fin-type active region FA are removed through the gate spaces GS according to the process of fig. 24A and 24B described above, the sacrificial semiconductor layer 104B remaining in the resultant structure of fig. 31C is removed, and thus an insulating space (not shown) exposing the upper surface FT of the fin-type active region FA may be formed. The insulation space may extend to an area between the source/drain region 730 and the fin active region FA. Bottom insulating structure 754 may be formed within the insulating space while gate dielectric layer 152 is formed according to the processes described above with reference to fig. 25A and 25B. The bottom insulating structure 754 may be formed to extend to a portion of the area between the source/drain region 730 and the fin-type active area FA, which vertically overlaps the source/drain region 730.

The IC device 800 of fig. 10 may be fabricated according to the process described above with reference to fig. 31A-31D. However, bottom insulating structure 854 may be formed in the process described above with reference to fig. 31D instead of bottom insulating structure 754. For this reason, while the plurality of sacrificial semiconductor layers 104 remaining on the fin-type active region FA are removed through the gate spaces GS according to the process of fig. 24A and 24B described above, only a portion of the sacrificial semiconductor layer 104B remaining in the resultant structure of fig. 31C may be removed, and the remaining portion of the sacrificial semiconductor layer 104B may remain as the semiconductor pattern 804 between the upper surface FT of the fin-type active region FA and the source/drain regions 730. As a result, a plurality of insulating spaces (not shown) whose width in the X direction is defined by the plurality of semiconductor patterns 804 may be formed between the fin-type active region FA and the first nanosheet N1. The insulation space may extend to a portion of the region between the source/drain region 730 and the fin active region FA. While the gate dielectric layer 152 is formed according to the process described above with reference to fig. 25A and 25B, a plurality of bottom insulating structures 854 may be formed within the plurality of insulating spaces.

According to the IC device manufacturing method described above with reference to fig. 29A to 31B, it is possible to provide a structure capable of suppressing deterioration of electrical characteristics by suppressing formation of an unnecessary channel around the upper surface of the fin-type active region.

Although the method of manufacturing the IC devices 100 to 700 of fig. 1 to 10 has been described above with reference to fig. 11 to 31D, various modifications may be made within the technical spirit of the inventive concept to manufacture other IC devices having various structures.

While the present inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.

The present application claims priority from korean patent application No. 10-2018-0107892, filed by the korean intellectual property office at 10.9.2018, the disclosure of which is incorporated herein by reference in its entirety.