阅读说明：本技术 半导体器件及其制造方法 (Semiconductor device and method for manufacturing the same ) 是由 金东铉 朴成哲 于 2019-09-11 设计创作，主要内容包括：可以提供一种半导体器件和制造半导体器件的方法,该半导体器件包括：基板,具有多个有源鳍,所述多个有源鳍中的每个有源鳍沿第一方向延伸；第一栅极结构和第二栅极结构,跨过所述多个有源鳍,第一栅极结构和第二栅极结构沿不同于第一方向的第二方向延伸,第一栅极结构和第二栅极结构在第二方向上彼此间隔开；至少一个绝缘阻挡物,沿第一方向延伸并在所述多个有源鳍之间,绝缘阻挡物使第一栅极结构的下部和第二栅极结构的下部彼此分隔；以及栅极隔离层,连接到绝缘阻挡物的一部分,栅极隔离层使第一栅极结构的上部和第二栅极结构的上部彼此分隔。(A semiconductor device and a method of manufacturing a semiconductor device may be provided, the semiconductor device including: a substrate having a plurality of active fins, each of the plurality of active fins extending along a first direction; first and second gate structures spanning the plurality of active fins, the first and second gate structures extending in a second direction different from the first direction, the first and second gate structures being spaced apart from each other in the second direction; at least one insulation barrier extending in the first direction and between the plurality of active fins, the insulation barrier separating a lower portion of the first gate structure and a lower portion of the second gate structure from each other; and a gate isolation layer connected to a portion of the insulation barrier, the gate isolation layer separating an upper portion of the first gate structure and an upper portion of the second gate structure from each other.)

1. A semiconductor device, comprising:

a substrate having a plurality of active fins, each of the plurality of active fins extending in a first direction;

first and second gate structures spanning the plurality of active fins, the first and second gate structures extending in a second direction different from the first direction, the first and second gate structures being spaced apart from each other in the second direction;

at least one insulating barrier extending along the first direction and between the plurality of active fins, the insulating barrier separating a lower portion of the first gate structure and a lower portion of the second gate structure from each other; and

a gate isolation layer connected to a portion of the insulation barrier, the gate isolation layer separating an upper portion of the first gate structure and an upper portion of the second gate structure from each other.

2. The semiconductor device of claim 1, wherein the insulation barrier extends to a length corresponding to a length of an adjacent active fin of the plurality of active fins.

3. The semiconductor device of claim 1, wherein the insulating barrier has a height greater than a height of the active fin.

4. The semiconductor device of claim 1, wherein a width of the insulation barrier in the second direction is less than a width of the gate isolation layer in the second direction.

5. The semiconductor device of claim 1, wherein each of the insulation barrier and the gate isolation layer has a width at a bottom surface that is less than a width at a top surface.

6. The semiconductor device of claim 1, wherein the plurality of active fins are arranged at a plurality of different spacings, and the at least one insulation barrier comprises a plurality of insulation barriers having different widths according to respective spacings between respective adjacent pairs of the plurality of active fins.

7. The semiconductor device of claim 6, wherein none of the plurality of insulation barriers is present between two adjacent active fins among the plurality of active fins arranged at a smallest spacing of the plurality of different spacings.

8. The semiconductor device of claim 6, wherein the plurality of insulation barriers comprises two insulation barriers arranged in the second direction, and each of the two insulation barriers is at an area between two adjacent ones of the plurality of active fins arranged at a largest spacing of the plurality of different spacings.

9. The semiconductor device of claim 1, wherein the at least one insulation barrier comprises a plurality of insulation barriers, and the plurality of insulation barriers have a height greater than a height of the plurality of active fins.

10. The semiconductor device of claim 1, wherein

Each of the first and second gate structures includes a gate dielectric film on a portion of each of the plurality of active fins and a gate electrode on the gate dielectric film, and

the gate dielectric film extends to a side surface of the insulation barrier in contact with the gate electrode and a side surface of the gate isolation layer in contact with the gate electrode.

11. The semiconductor device of claim 10, wherein each of the first and second gate structures further comprises a gate spacer on both a side surface of each of the first and second gate structures and a side surface of the gate isolation layer and extending along the second direction.

12. A semiconductor device, comprising:

a substrate having a plurality of active fins, each active fin extending along a first direction, the plurality of active fins arranged at a first spacing or a second spacing, the second spacing being greater than the first spacing;

first and second gate structures spanning the plurality of active fins and extending in a second direction different from the first direction, the first and second gate structures being spaced apart from each other in the second direction;

at least one insulation barrier between two adjacent ones of the plurality of active fins arranged at the second spacing, the insulation barrier extending along the first direction and between the first gate structure and the second gate structure; and

a gate isolation layer on a portion of an upper surface of the insulating barrier and between the first gate structure and the second gate structure.

13. The semiconductor device of claim 12, wherein the insulation barrier has a length corresponding to a length of an adjacent active fin of the plurality of active fins and has a height greater than a height of the active fin.

14. The semiconductor device of claim 12, wherein a width at a top surface of the insulation barrier is less than a width at a bottom surface of the gate isolation layer.

15. The semiconductor device of claim 12, wherein each of the insulation barrier and the gate isolation layer has a width at a bottom surface that is less than a width at a top surface.

16. The semiconductor device of claim 12, wherein the second spacing comprises a plurality of different spacings and the at least one insulation barrier comprises a plurality of insulation barriers having different widths proportional to sizes of the plurality of different spacings.

17. The semiconductor device of claim 12, wherein the insulating barrier is absent between the active fins arranged at the first spacing.

18. The semiconductor device of claim 12, wherein some of the plurality of active fins are spaced apart from each other in the first direction, and

the semiconductor device further includes at least one additional insulation barrier extending along the second direction and provided at spaces between the some of the plurality of active fins.

19. The semiconductor device of claim 18, wherein the at least one additional insulation barrier comprises two insulation barriers arranged in the first direction.

20. A semiconductor device, comprising:

a substrate having a plurality of active fins, each of the plurality of active fins extending in a first direction;

a first gate structure and a second gate structure spanning the plurality of active fins and extending in a second direction different from the first direction; and

a gate cut structure between the first and second gate structures such that the first and second gate structures are separated, the gate cut structure including an insulation barrier extending in the first direction between the plurality of active fins and a gate isolation layer on a portion of an upper surface of the insulation barrier.

21. A method of manufacturing a semiconductor device, the method comprising:

forming a plurality of active fins extending in a first direction on a substrate, the plurality of active fins having a structure protruding beyond a device isolation layer;

forming a first dummy gate material layer on the device isolation layer to cover the plurality of active fins;

removing some of the first dummy gate material layer between the plurality of active fins to expose a portion of the device isolation layer, the exposed portion of the device isolation layer defining a bottom surface of a space surrounded by the first dummy gate material layer;

forming an insulating barrier on the exposed portion of the device isolation layer such that the space surrounded by the first dummy gate material layer is filled;

forming a second dummy gate material layer on the first dummy gate material layer;

forming at least one dummy gate pattern by patterning the first dummy gate material layer and the second dummy gate material layer;

forming an isolation hole in a portion of the dummy gate pattern such that the dummy gate pattern is divided into two parts and a portion of the insulation barrier is exposed through the isolation hole; and

forming a gate isolation layer in the isolation hole of the dummy gate pattern.

22. The method of manufacturing a semiconductor device according to claim 21, further comprising:

forming a gate insulating film on surfaces of the plurality of active fins prior to forming the first dummy gate material layer.

23. The method of manufacturing a semiconductor device according to claim 21, wherein the forming an insulation barrier comprises:

depositing the insulating barrier on the first dummy gate material layer such that the space surrounded by the first dummy gate material layer is filled; and

polishing the insulation barrier such that the first dummy gate material layer is exposed in areas corresponding to the plurality of active fins.

24. The method of manufacturing a semiconductor device according to claim 21, wherein the forming at least one dummy gate pattern comprises:

forming a plurality of dummy gate patterns extending in a second direction crossing the first direction by patterning the first dummy gate material layer and the second dummy gate material layer, an

Forming gate spacers extending in the second direction on side surfaces of each of the plurality of dummy gate patterns.

25. The method of manufacturing a semiconductor device according to claim 21, further comprising,

after forming the gate isolation layer, exposing a portion of the active fin by removing the dummy gate pattern, forming a gate dielectric film on at least a portion of the active fin, and filling the space in which the dummy gate pattern is removed with a gate electrode material.

Technical Field

The inventive concept relates to semiconductor devices and/or methods of manufacturing semiconductor devices.

Background

As demands for higher performance, faster speed, and/or versatility of semiconductor devices increase, the integration degree of semiconductor devices tends to increase. In manufacturing such a highly integrated semiconductor device, it is desirable to realize a pattern having a fine width or a fine spacing distance. Furthermore, as semiconductor devices become more highly integrated, planar metal oxide semiconductor fets (mosfets) tend to be replaced by finfets having channels with three-dimensional (3D) structures.

Disclosure of Invention

At least one or more aspects of the inventive concept are to provide a semiconductor device and/or a method of manufacturing the same, in which an integration degree is improved.

According to an example embodiment, a semiconductor device includes: a substrate having a plurality of active fins, each of the plurality of active fins extending in a first direction; first and second gate structures spanning the plurality of active fins, the first and second gate structures extending in a second direction different from the first direction, the first and second gate structures being spaced apart from each other in the second direction; at least one insulation barrier extending in the first direction and between the plurality of active fins, the insulation barrier separating a lower portion of the first gate structure and a lower portion of the second gate structure from each other; and a gate isolation layer connected to a portion of the insulation barrier, the gate isolation layer separating an upper portion of the first gate structure and an upper portion of the second gate structure from each other.

According to an example embodiment, a semiconductor device includes: a substrate having a plurality of active fins, each active fin extending along a first direction, the plurality of active fins arranged at a first spacing or a second spacing, the second spacing being greater than the first spacing; first and second gate structures spanning the plurality of active fins and extending in a second direction different from the first direction, the first and second gate structures being spaced apart from each other in the second direction; at least one insulating barrier between two adjacent ones of the plurality of active fins arranged at a second spacing, the insulating barrier extending in the first direction and between the first gate structure and the second gate structure; and a gate isolation layer on a portion of an upper surface of the insulating barrier and between the first gate structure and the second gate structure.

According to an example embodiment, a semiconductor device includes: a substrate having a plurality of active fins, each of the plurality of active fins extending in a first direction; first and second gate structures spanning the plurality of active fins and extending in a second direction different from the first direction; and a gate cut structure between the first and second gate structures such that the first and second gate structures are separated, the gate cut structure including an insulation barrier extending in the first direction between the plurality of active fins and a gate isolation layer on a portion of an upper surface of the insulation barrier.

According to an example embodiment, a method of manufacturing a semiconductor device includes: forming a plurality of active fins extending in a first direction on a substrate, the plurality of active fins having a structure protruding beyond a device isolation layer; forming a first dummy gate material layer on the device isolation layer to cover the plurality of active fins; removing some of the first dummy gate material layer between the plurality of active fins to expose a portion of the device isolation layer, the exposed portion of the device isolation layer defining a bottom surface of a space surrounded by the first dummy gate material layer; forming an insulating barrier on the exposed portion of the device isolation layer such that a space surrounded by the first dummy gate material layer is filled; forming a second dummy gate material layer on the first dummy gate material layer; forming at least one dummy gate pattern by patterning the first dummy gate material layer and the second dummy gate material layer; forming an isolation hole in a portion of the dummy gate pattern such that the dummy gate pattern is separated into two parts and a portion of the insulating barrier is exposed through the isolation hole; and forming a gate isolation layer in the isolation hole of the dummy gate pattern.

Drawings

The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

fig. 1 is a plan view illustrating a semiconductor device according to an example embodiment;

fig. 2 is a partial perspective view showing a portion a of the semiconductor device shown in fig. 1;

fig. 3 is a cross-sectional view of the semiconductor device shown in fig. 1 taken along line III-III';

fig. 4A to 4C are cross-sectional views of the semiconductor device shown in fig. 1 taken along lines IVA-IVA ', IVB-IVB ', and IVC-IVC ', respectively;

fig. 5 is an enlarged view of a two-level gate cut structure for the semiconductor device shown in fig. 2, according to some example embodiments;

fig. 6 is a cross-sectional view illustrating a gate cutting structure employed in a semiconductor device according to an example embodiment;

fig. 7 to 11 are sectional views illustrating processes of a method of manufacturing a semiconductor device according to an example embodiment, and correspond to sections taken along the line III-III' of fig. 1;

fig. 12 and 13 are plan views illustrating a semiconductor device according to an example embodiment;

fig. 14 is a cross-sectional view of the semiconductor device shown in fig. 12 taken along line XIV-XIV';

fig. 15A and 15B are cross-sectional views of the semiconductor device shown in fig. 11 taken along lines XVA-XVA 'and lines XVB-XVB', respectively;

fig. 16A, 17A, 18A and 19A are plan views illustrating processes of a method of manufacturing the semiconductor device (forming an insulating barrier) shown in fig. 12 according to an example embodiment;

fig. 16B, 17B, 18B and 19B correspond to the sectional views taken along the line XIV-XIV' of fig. 12 of fig. 16A, 17A, 18A and 19A, respectively;

fig. 20 and 21 are plan views illustrating processes (replacement processes) of a method of manufacturing a semiconductor device according to an example embodiment;

fig. 22 is a sectional view taken along line XXII-XXII' of fig. 20;

fig. 23A and 23B are cross-sectional views taken along lines XXIIIA-XXIIIA 'and lines XXIIIB-XXIIIB' of fig. 21;

fig. 24 is a block diagram illustrating an electronic apparatus including a semiconductor device according to an example embodiment;

and

fig. 25 is a schematic diagram illustrating a system including a semiconductor device according to an example embodiment.

Detailed Description

Fig. 1 is a plan view illustrating a semiconductor device according to an example embodiment, and fig. 2 is a partial perspective view of a portion a of the semiconductor device illustrated in fig. 1.

Referring to fig. 1 and 2, a semiconductor device 100 according to an example embodiment may include a substrate 101, a device isolation layer 105 disposed on the substrate 101, and a first active fin AF1 and a second active fin AF2 disposed on the substrate 101 and protruding beyond the device isolation layer 105.

The substrate 101 may include a semiconductor material (e.g., a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor). For example, the group IV semiconductor may comprise silicon, germanium, or silicon germanium. The substrate 101 may be provided as a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SOI) layer, or the like.

The substrate 101 may include an active region, and the first and second active fins AF1 and AF2 may be formed on the active region. For example, the first and second active fins AF1 and AF2 may be formed in an N-type well for a P-MOS transistor or a P-type well for an N-MOS transistor.

The device isolation layer 105 may define an active region on the substrate 101, wherein the first active fin AF1 and the second active fin AF2 are formed on the active region. The device isolation layer 105 may be formed, for example, by a Shallow Trench Isolation (STI) process. According to some example embodiments, the device isolation layer 105 may include a region extending deeper into the lower portion of the substrate 101 between the first and second active fins AF1 and AF 2. The device isolation layer 105 may have a curved upper surface, but the shape of the upper surface of the device isolation layer 105 is not limited thereto. The device isolation layer 105 may be made of an insulating material. For example, the device isolation layer 105 may include an oxide, a nitride, or a combination thereof.

The first and second active fins AF1 and AF2 may extend in the first direction D1 and may be arranged in the second direction D2 crossing the first direction D1. The first and second active fins AF1 and AF2 may be provided as active regions (e.g., source, channel, and drain) of a transistor.

As shown in fig. 1, the first and second active fins AF1 and 2 are each shown as including two active fins, but are not limited thereto and may be provided as one active fin or three or more active fins in some example embodiments.

The plurality of gate structures GS may cross the first active fin AF1 and the second active fin AF 2. The plurality of gate structures GS may extend in the second direction D2, respectively, and may be arranged in the first direction D1.

Fig. 4A to 4C are cross-sectional views of the semiconductor device shown in fig. 1 taken along lines IVA-IVA ', IVB-IVB ', and IVC-IVC ', respectively.

As shown in fig. 4A through 4C, the gate structure GS may include sidewall spacers 133, a gate dielectric layer 134 disposed between the sidewall spacers 133, and a gate electrode 135. In some example embodiments, the gate structure GS may further include a gate capping layer on the gate dielectric layer 134 and the gate electrode 135.

The gate electrode 135 may include a conductive material such as a metal nitride (e.g., a titanium nitride film TiN, a tantalum nitride film TaN, or a tungsten nitride film WN) and/or a metal material (e.g., aluminum Al, tungsten W, or molybdenum Mo), or a semiconductor material (e.g., doped polysilicon). In some example embodiments, the gate electrode 135 may include two or more multilayer structures.

A gate capping layer may be formed in a region in which a portion of the gate dielectric film 134 and a portion of the gate electrode 135 are etched back. For example, the gate capping layer may be an insulating material, such as silicon nitride.

The sidewall spacers 133 may be formed of, for example, an insulating material (e.g., SiOCN, SiON, SiCN, or SiN). The gate dielectric film 134 may include a silicon oxide film, a silicon oxynitride film, or a high dielectric constant film having a higher dielectric constant than silicon oxide. The high dielectric constant material can be expressed as SiO, which is a material having a specific dielectric constant to silicon oxide₂Having a high dielectric constantA material. For example, the high dielectric constant material may be aluminum oxide Al₂O₃Tantalum oxide Ta₂O₃Titanium oxide TiO₂Yttrium oxide Y₂O₃Zirconium oxide ZrO₂Zirconium silicon oxide ZrSi_xO_yHafnium oxide HfO₂Hafnium silicon oxide HfSi_xO_yLanthanum oxide La₂O₃Lanthanum aluminum oxide LaAl_xO_yLanthanum hafnium oxide LaHf_xO_yHafnium aluminum oxide HfAl_xO_yOr praseodymium oxide Pr₂O₃At least one of (1).

The interlayer insulating layer 115 may be disposed between the plurality of gate structures GS while covering the device isolation layer 105 and the first and second active fins AF1 and AF 2. An additional interlayer (not shown) insulating layer may be disposed to cover the plurality of gate structures GS. For example, the interlayer insulating layer 115 may be at least one of an oxide, a nitride, or an oxynitride, or may include a material having a lower dielectric constant than silicon oxide.

Some of the gate structures GS may be divided into a plurality of portions by the gate cutting structure 150. As shown in fig. 1 and 2, in the present example embodiment, both gate structures GS may be divided into a first gate structure GS1 and a second gate structure GS2 in the second direction D2 by the gate cut structure 150. The first gate structure GS1 and the second gate structure GS2 may extend and may be arranged in the second direction D2.

As in the present example embodiment, two or more gate cutting structures 150 may be formed in the first direction through two or more adjacent gate structures GS, respectively. Accordingly, a plurality of (e.g., two) gate structures GS may be separated in the second direction D2. In some example embodiments, the gate cut structure 150 may be provided to separate only one gate structure GS.

The gate cutting structure 150 employed in the present exemplary embodiment includes a two-layer insulating structure separating the first gate structure GS1 and the second gate structure GS 2. Fig. 3 is a cross-sectional view of the semiconductor device shown in fig. 1 taken along line III-III' and illustrates a two-layer gate cutting structure employed in the present exemplary embodiment.

Referring to fig. 3 and 2, the gate cutting structure 150 includes an insulating barrier (insulating barrier)151 disposed between the first and second active fins AF1 and AF2, and a gate isolation layer 155 disposed on a portion of an upper surface of the insulating barrier 151.

The insulation barrier 151 and the gate isolation layer 155 are formed through different processes at different stages (refer to fig. 7 to 11) and thus may have different shapes.

As shown in fig. 1 and 2, the insulating barrier 151 may have a structure extending in the first direction D1 between the first and second active fins AF1 and AF 2. The insulating barrier 151 may extend to a length substantially corresponding to the extension length of the adjacent active fins AF1 and AF 2. The insulating barrier 151 may have a shape similar to the first active fin AF1 or the second active fin AF 2.

It should be noted that the insulating barrier 151 may also be located in an area other than a desired (or alternatively, a predetermined) gate cutting area. For example, as shown in fig. 2, the insulation barrier 151 may include a portion connected to the gate isolation layer 155 in a desired (or alternatively, a predetermined) gate cutting region, and the insulation barrier 151 may further include other portions extending in the first direction D1 without being connected to the gate isolation layer 155.

Further, referring to fig. 1 and 3, the insulating barrier 151 may be additionally provided in an area between other active fins AF1 and/or AF2 where the gate isolation layer 155 is not provided. It is understood that this insulating barrier 151 is provided only as a dummy element.

The height L2 of the insulating barrier 151 may be greater than the height L1 of the first and second active fins AF1 and AF 2. In this specification, the height comparison may be described based on the level of the upper surface of each configuration rather than the height of each configuration itself. The plurality of insulation barriers 151 disposed between the other active fins AF1 and AF2 may also have the same or substantially similar height as the height L2 (refer to fig. 3). For example, the upper surfaces of the plurality of insulation barriers 151 may be obtained through a polishing process.

The insulating barrier 151 may not be provided in an area in which the interval between the active fins is less than any interval (or threshold interval). As shown in fig. 1 to 3, the insulating barrier 151 may not be disposed between some of the active fins (e.g., not disposed between some of the first active fins AF1 and not disposed between some of the second active fins AF 2). For example, the insulation barrier 151 may not be formed between some of the active fins arranged at the smallest interval among the plurality of different intervals. In some example embodiments, adjacent active fins AF1 and/or AF2 that are not separated by insulating barrier 151 may be connected by epitaxial regrowth to provide one common source or one common drain.

Referring to fig. 1 to 3, a gate isolation layer 155 may be provided to be connected to a portion of the insulation barrier 151. The insulating barrier 151 separates a lower portion of the first gate structure GS1 and a lower portion of the second gate structure GS2, and the gate isolation layer 155 separates an upper portion of the first gate structure GS1 and an upper portion of the second gate structure GS 2.

The gate isolation layer 155 may be formed before the gate structure GS is completed. For example, before performing the replacement process for forming the gate structure GS, the dummy gate layer (e.g., polysilicon) located in the gate isolation region may be removed, and the removed region may be filled with an insulating material, thereby forming the gate isolation layer 155 (see fig. 23A and 23B).

In the present example embodiment, a gate isolation layer 155 may be formed at an upper surface of the insulation barrier 151 to form a desired gate cutting structure 150. Since the gate isolation layer 155 does not have to be formed deep so that the gate isolation layer 155 contacts the device isolation layer 105, the limitation of the photolithography and etching processes caused by the failure to completely remove the dummy gate material can be overcome and the variation of the threshold voltage Vth can be prevented or mitigated.

As described above, each gate structure GS may include the gate dielectric film 134 disposed on a portion of the first and second active fins AF1 and AF2 and the gate electrode 135 disposed on the gate dielectric film 134.

As shown in fig. 3, the gate dielectric film 134 may extend to a side surface of the insulation barrier 151 contacting the gate electrode 135 and a side surface of the gate isolation layer 155 contacting the gate electrode 135 (as viewed in a cross-section along line III-III').

Furthermore, as shown in fig. 4A, the gate structure GS may further include a gate spacer 133 disposed on both side surfaces (which are elongated side surfaces thereof), and the gate spacer 133 may extend to the other side surfaces of the gate isolation layer 155 except the side surface contacting the gate electrode 135, in other words, to the side surface not contacting the gate electrode 135 (as viewed in a cross section along line IVA-IVA'). The gate spacers 133 are not formed on the surface of the insulating barrier 151.

Fig. 5 is an enlarged view of a two-layer gate cutting structure 150 for the semiconductor device shown in fig. 2 according to an example embodiment.

Referring to fig. 5, the gate cut structure 150 includes the insulating barrier 151 separating the lower portion of the first gate structure GS1 and the lower portion of the second gate structure GS2 from each other as described above, and the gate isolation layer 155 connected to a portion of the insulating barrier 151 and separating the upper portion of the first gate structure GS1 and the upper portion of the second gate structure GS2 from each other.

The insulation barrier 151 and the gate isolation layer 155 may be formed through a series of different processes (self-aligned process, photo/etching process) before and after a replacement process (e.g., replacement poly gate RPG process) to have different shapes from each other and a discontinuous interface therebetween.

Although not limited thereto, the width of the insulation barrier 151 may be less than the width of the gate isolation layer 155. For example, a bottom width D at a lower end (e.g., bottom surface) of the gate isolation layer 155_BMay be greater than a top width d at an upper end (e.g., top surface) of the insulation barrier 151_T。

The insulation barrier 151 may have a recessed lower portion r in the device isolation layer 105 to ensure complete insulation between the lower portion of the first gate structure GS1 and the lower portion of the second gate structure GS 2. In the case where the insulation barrier 151 is formed through a self-alignment process, a bottom width d of the insulation barrier 151_BMay be less than the top width d of the insulation barrier 151_T. Here, the width of the insulation barrier 151 denotes a distance in the second direction D2. In addition, the bottom width D of the gate isolation layer 155_BOr less than the top width D of the gate isolation layer 155_T。

Fig. 6 is a cross-sectional view illustrating a gate cutting structure employed in a semiconductor device according to another example embodiment.

Referring to fig. 6, the gate cutting structure 150' employed in the present exemplary embodiment has a two-layer structure similar to the gate cutting structure shown in fig. 5. For example, the gate cut structure 150 'includes an insulation barrier 151' separating a lower portion of the first gate structure GS1 and a lower portion of the second gate structure GS2 from each other, and a gate isolation layer 155 'connected to a portion of the insulation barrier 151' and separating an upper portion of the first gate structure GS1 and an upper portion of the second gate structure GS2 from each other. Bottom width D of gate isolation layer 155_B' may be smaller than the top width D of the gate isolation layer 155_T'. In addition, the bottom width d of the insulating barrier 151_B' may be smaller than the top width d of the insulation barrier 151_T'. However, unlike the previous example embodiment, the bottom width D of the gate isolation layer 155_B' less than the top width d of the insulating barrier 151_T'。

As such, the gate cutting structure that may be employed in some example embodiments may have various profiles depending on the widths of the gate isolation layer and the insulation barrier.

As described above, the gate cutting structures 150 and 150' employed in the present exemplary embodiment are formed using various processes (e.g., a self-aligned process or a photolithography process) before and after the replacement process. Various features of the inventive concept will be more readily understood in describing some exemplary manufacturing methods.

Fig. 7 to 11 are sectional views illustrating processes of a method of manufacturing a semiconductor device according to an example embodiment, and correspond to sections taken along line III-III' of fig. 1.

Referring to fig. 7, a first active fin AF1 and a second active fin AF2 extending in the first direction D1 are formed on the substrate 101.

By using the recess process, the first active fin AF1 and the second active fin AF2 may protrude beyond the device isolation layer 105 to a desired height. The first active fin AF1 and the second active fin AF2 may be arranged at different intervals. In the present example embodiment, the interval between the first active fins AF1 and the interval between the second active fins AF2 is a first interval d1, and the interval between the first active fins AF1 and the second active fins AF2 is a second interval d2 greater than d 1. Here, each adjacent pair of the first active fin AF1 and the second active fin AF2 may be connected by epitaxial regrowth to provide a source and a drain in a subsequent process.

Referring to fig. 8, a first dummy gate material DG1' is formed on the device isolation layer 105.

Before forming the first dummy gate material DG1, the gate insulating film 131 may be formed on the surface of the first active fin AF1 and the surface of the second active fin AF 2. For example, the gate insulating film 131 may be an oxide. The gate insulating film 131 may be conformally formed in a deposition process. If the gate insulating film 131 is formed using an oxidation process, the gate insulating film 131 may be formed only on the surface of the first active fin AF1 and the surface of the second active fin AF 2. The gate insulating film 131 may be used as a gate dielectric film in a peripheral circuit, may be used together with another dielectric film in a circuit (e.g., an SRAM cell circuit), or may be replaced with another dielectric film.

In an example embodiment, the dummy gate is formed by performing a two-step process, the process shown in fig. 8 corresponding to a first deposition step to form the first dummy gate material DG 1'. The first step may be performed until the plurality of active fins AF1 and AF2 are covered. For example, the first dummy gate material DG1' may be polysilicon.

In the first step, the space between the active fins may be filled or left depending on the spacing of the active fins. For example, the space between the first active fin AF1 arranged at the first interval d1 and the space between the second active fin AF2 arranged at the first interval d1 may be almost completely filled, and the space between the first active fin AF1 arranged at the second interval d2 and the second active fin AF2 may be partially filled, thereby leaving an empty space S. The space S between the first and second active fins AF1 and AF2 may be controlled by the spacing between the first and second active fins AF1 and AF2 and the thickness of the first dummy gate material DG 1'.

Referring to fig. 9, the first dummy gate material DG1 'may be partially removed from the space S between the first and second active fins AF1 and AF2 to expose the device isolation layer 105, thereby forming a modified first dummy gate material DG1 ″, and an insulating barrier layer 151' may be formed on the modified first dummy gate material layer DG1 ″.

The first dummy gate material DG1' may be etched to a desired thickness by applying a spacer etch (e.g., an isotropic etch) to form a modified first dummy gate material DG1 ". The etching may be performed until a portion of the device isolation layer 105 is exposed in the space S between the first active fin AF1 and the second active fin AF2 arranged at the second interval d 2. In this process, the exposed region of the device isolation layer 105 may have a recessed portion r. Then, the exposed portion of the device isolation layer 105 may be provided between the modified first dummy gate material DG1 "or between the bottom surfaces of the spaces surrounded by the modified first dummy gate material layer DG 1".

Then, the insulation barrier layer 151' may fill the space S between the modified first dummy gate materials DG1 "or the space S surrounded by the modified first dummy gate materials DG 1". According to the present example embodiment, the insulation barrier layer 151' is not provided to contact the device isolation layer 105 between the first active fins AF1 and between the second active fins AF 2. For example, the insulating barrier layer 151' may not be provided to contact the device isolation layer 105 at a position where a space between a pair of adjacent first active fins AF1 and between a pair of adjacent second active fins AF2 is almost completely filled, and the insulating barrier layer 151' may be filled in the space S between the first active fin AF1 and the second active fin AF2 such that the insulating barrier layer 151' contacts an exposed region of the device isolation layer 105. The insulating material may be, for example, a nitride (e.g., silicon nitride).

Referring to fig. 10, the resulting structure of fig. 9 is polished to expose the modified first dummy gate material DG1 "in the areas corresponding to the first and second active fins AF1 and AF2 to provide a first dummy gate material layer DG1, and then a second dummy gate material layer DG2 is formed on the first dummy gate material layer DG 1.

The upper surface of the resulting structure of fig. 9 may be planarized by polishing the modified first dummy gate material DG1 "and the insulating barrier 151. In this process, the top surface of the modified first dummy gate material DG1 ″ may be exposed in the areas corresponding to the first and second active fins AF1 and AF 2. In order to prevent the first and second active fins AF1 and 2 from being damaged during the polishing process, the insulating barrier 151 between the first and second active fins AF1 and 2 may be formed higher than the active fins AF1 and AF 2. The planarization process may be performed by a chemical mechanical polishing CMP process or a dry etch back process.

The height of the final dummy gate structure DG may be adjusted by forming a second dummy gate material layer DG2 on the polished first dummy gate material layer (e.g., first dummy gate material layer pattern) DG1 through a second deposition process. In this way, the final dummy gate structure DG may be formed by a two-step process including a first deposition step to form the first dummy gate material layer DG1' and a second deposition step to form the second dummy gate material layer DG 2. The planarized surface of the first dummy gate material layer DG1 may be cleaned before the second deposition process is performed. For example, the second dummy gate material layer DG2 may include the same material (e.g., polysilicon) as the first dummy gate material layer DG 1.

Referring to fig. 11, a gate isolation layer 155 is formed in a desired isolation region of the dummy gate structure DG.

The process for forming the gate isolation layer 155 may be performed after patterning the dummy gate structure DG to have a pattern (hereinafter, referred to as "dummy gate pattern") corresponding to the final gate structure (GS of fig. 1). As shown in fig. 11, an isolation hole may be formed in one region of the dummy gate structure DG such that the dummy gate structure DG is divided into two dummy gate structures, and the isolation hole may be filled with an isolation material to form a gate isolation layer 155. Here, a portion of the insulation barrier 151 is exposed through the isolation hole such that the gate isolation layer 155 is connected to the portion of the insulation barrier 151. The insulation barrier 151 and the gate isolation layer 155 may form the gate cutting structure 150. For example, the insulating material for the gate isolation layer 155 may be a nitride (e.g., silicon nitride). The gate isolation layer 155 may include the same insulating material as the insulating barrier 151.

Fig. 12 and 13 are plan views illustrating a semiconductor device according to an example embodiment, and fig. 14 is a cross-sectional view of the semiconductor device illustrated in fig. 12 taken along line XIV-XIV'.

Referring to fig. 12 and 14, the semiconductor device 100A according to the present example embodiment may include first and second active fins AF1 and AF2 and a device isolation layer 105 disposed in a substrate 101, and a gate structure GS. The description of the same components as the above-described exemplary embodiments may not be repeated.

The device isolation layer 105 defines the first and second active fins AF1 and AF2 in the substrate 101 and between the first and second active fins AF1 and AF 2. Further, the first and second active fins AF1 and AF2 include portions protruding beyond the device isolation layer 105. The first and second active fins AF1 and AF2 may be conductive semiconductor structures doped with impurities. In the present example embodiment, although not limited thereto, the first active fin AF1 may be an n-type semiconductor for a PMOS transistor, and the second active fin AF2 may be a p-type semiconductor for an NMOS transistor.

As shown in fig. 12, the first and second active fins AF1 and AF2 may extend in the first direction D1. Each of the first and second active fins AF1 and AF2 provides an active region of each transistor. In addition, the plurality of gate structures GS may extend in the second direction D2 crossing the first direction D1. The plurality of gate structures GS may overlap respective areas of the first and second active fins AF1 and AF2, and each overlapping area may provide one transistor. A semiconductor device according to an example embodiment constitutes an SRAM circuit.

Fig. 13 is a plan view showing only the first and second active fins AF1 and AF2 and the gate structure GS to easily understand the circuit configuration of the semiconductor device of fig. 12.

Referring to fig. 12 and 13, the SRAM cell labeled "SR" includes: a first inverter including a first pull-up transistor PU1 and a first pull-down transistor PD1 connected in series; and a second inverter including a second pull-up transistor PU2 and a second pull-down transistor PD2 connected in series; and a first transfer transistor PS1 and a second transfer transistor PS2 (not shown) connected to output nodes of the first inverter and the second inverter, respectively. Here, the first pull-up transistor PU1 and the second pull-up transistor PU2 may be PMOS transistors, and the first pull-down transistor PD1 and the second pull-down transistor PD2 may be NMOS transistors.

To implement the SRAM cell circuits as shown in fig. 12 and 13, the first active fin AF1 and the second active fin AF2 may be arranged at different intervals.

Referring to fig. 12 to 14, the first and second active fins AF1 and AF2 are arranged at a plurality of different intervals d1, d2a, d2b, and d2 c. The plurality of intervals may be set to d2a > d2b > d2c > d 1.

For example, two pairs of first active fins AF1 in the SRAM cell SR may be arranged at a first interval d1 (shortest interval), and a certain pair of first active fins AF1 may be arranged at a second interval d2a (largest interval) from an adjacent pair of first active fins AF 1. The first active fin AF1 and the second active fin AF2 may be arranged at a third interval d2b, and the adjacent second active fin AF2 may be arranged at a fourth interval d2 c.

When the interval of the adjacent active fins is narrow, the insulating barrier may not be formed. In the present example embodiment, the insulation barrier may not exist in the space S1 between the first active fins AF1 arranged at the first interval d 1.

In the case where the insulation barrier is provided in the space between a pair of adjacent active fins, the width of the insulation barrier may vary depending on the interval between the pair of adjacent active fins. In particular, a width of the insulating barrier in the space may be proportional to a spacing between the pair of adjacent active fins.

In the present example embodiment, the first insulating barrier 151A having the first width w1 is formed in the space S2a of the first active fin AF1 arranged at the second interval d2a, and the second insulating barrier 151B having the second width w2 smaller than the first width w1 is formed in the space S2B between the first active fin AF1 and the second active fin AF2 arranged at the third interval d 2B. Further, third insulation barriers 151C having a third width w3 smaller than the second width are formed in the spaces S2C between the second active fins AF2 arranged at the third interval d 2C.

As described above, the first to third insulation barriers 151A, 151B and 151C having different widths may be formed by differently setting the intervals of the active fins using the above-described self-alignment process.

Referring to fig. 12 and 15B, the semiconductor device 100A according to some example embodiments may further include a fourth insulation barrier 151D formed on the second direction D2, in addition to the first to third insulation barriers 151A, 151B, and 151C extending in the first direction D1.

The second active fins AF2 are separated by a relatively wide interval D3 in the first direction D1. In the present example embodiment, the separation space S2 between the second active fins AF2 adjacent to each other in the first direction D1 may have the widest space (D3> D2 a). In this case, the fourth insulation barrier 151D may be formed to include, for example, two separate insulation barriers.

As described in the above example embodiment, only some (not all) of the insulation barriers 151A, 151B, 151C, and 151D may be used as the gate cutting structure 150. For example, only a portion of each of the first and second insulating barriers 151A and 151B may be used as a portion of the gate cutting structure 150.

As shown in fig. 14 and 15A, the gate cutting structure 150 employed in the present example embodiment includes first and second insulating barriers 151A and 151B extending in the first direction D1 and a gate isolation layer 155 disposed on a portion of each of an upper surface of the first insulating barrier 151A and an upper surface of the second insulating barrier 151B. The gate isolation layer 155 may separate upper regions of the gate structures GS from each other, and the first and second insulation barriers 151A and 151B may separate lower regions of the gate structures GS from each other.

The insulation barriers (such as the third insulation barrier 151C and the fourth insulation barrier 151D) that are not used as constituent elements of the gate cut structure 150 may remain as dummy elements.

Further, as shown in fig. 14, although the widths of the first to fourth insulation barriers 151A, 151B, 151C, and 151D are different from each other, the heights L2 thereof may be the same or substantially similar to each other and may be greater than the heights L1 of the first and second active fins AF1 and 2. The upper surfaces of the first to fourth insulation barriers 151A, 151B, 151C and 151D may be obtained by a polishing process.

Similar to the previous example embodiment, each gate structure GS includes a gate dielectric film 134 disposed on a portion of the first and second active fins AF1 and AF2 and a gate electrode 135 disposed on the gate dielectric film 134.

As shown in fig. 14, gate dielectric film 134 may extend to side surfaces of first and second insulating barriers 151A and 151B that are in contact with gate electrode 135 and side surfaces of gate isolation layer 155 that are in contact with gate electrode 135 (as viewed in a cross section along line XIV-XIV').

In addition, as shown in fig. 15A, the gate structure GS may further include a gate spacer 133, and the gate spacer 133 is disposed on both side surfaces of the structure including the gate dielectric film 134 and the gate electrode 135. Furthermore, gate spacers 133 may be provided on both side surfaces of gate isolation layer 155 that are in contact with gate electrode 135 and on both side surfaces of gate isolation layer 155 that are not in contact with gate electrode 135 (as viewed in a cross-section along line XVA-XVA'). The gate spacers 133 may not be formed on the surfaces of the first and second insulation barriers 151A and 151B.

Fig. 16A, 17A, 18A, and 19A are plan views illustrating processes of a method of manufacturing the semiconductor device illustrated in fig. 12 according to an example embodiment. Fig. 16B, 17B, 18B, and 19B correspond to the sectional views taken along the line XIV-XIV' of fig. 12 of fig. 16A, 17A, 18A, and 19A, respectively.

Referring to fig. 16A and 16B, first and second active fins AF1 and AF2 are formed, the first and second active fins AF1 and AF2 extending in the first direction D1 on the substrate 101 and arranged at different intervals.

With the recess process, the first active fin AF1 and the second active fin AF2 may protrude beyond the device isolation layer 105 to a desired height. The first active fin AF1 and the second active fin AF2 may be arranged at different intervals (d2a > d2b > d2c > d 1). For example, two pairs of first active fins AF1 in the SRAM cell SR may be arranged at a first interval d1 (shortest interval), and a certain pair of first active fins AF1 may be arranged at a second interval d2a (largest interval) from an adjacent pair of first active fins AF 1. The first active fin AF1 and the second active fin AF2 may be arranged at a third interval d2b, and the adjacent second active fin AF2 may be arranged at a fourth interval d2 c. Further, the second active fin AF2 is separated in the first direction D1 by a space S3, and the space S3 may have a relatively wide spacing D3(D3> D2 a).

Referring to fig. 17A and 17B, a first dummy gate material (not shown) may be deposited and etched using a spacer etch to form a first dummy gate material layer DG1 such that the device isolation layer 105 between the first and second active fins AF1, AF2 is exposed through the first dummy gate material layer DG 1.

Before forming the first dummy gate material, the gate insulating film 131 may be formed on the surface of the first active fin AF1 and the surface of the second active fin AF 2. The deposition of the first dummy gate material may be performed until completely covering the plurality of active fins AF1 and AF 2. For example, the first dummy gate material may be polysilicon. The spaces S1' between the first active fins AF1 arranged at the first interval d1 (see fig. 14) may be substantially completely filled with the first dummy gate material layer.

The present spacer etch may be performed by applying an isotropic etch to etch the first dummy gate material to a particular thickness. In this process, a portion of the device isolation layer 105 may be exposed in spaces S2a, S2b, and S2c between some active fins, and the exposed region of the device isolation layer 105 may be recessed to a certain degree.

The widths of the final spaces between the active fins obtained after the etching may be different from each other depending on the intervals of the active fins. For example, space S2a 'between first active fin AF1 may have a first width w1, and space S2b' between first active fin AF1 and second active fin AF2 may have a second width w2 that is less than first width w 1. In addition, the space S2c' between the second active fins AF2 may have a third width w3 that is less than the second width w 2. However, the spaces S1' between the first active fins AF1 arranged at the interval d1 may be filled with the first dummy gate material layer DG 1.

Referring to fig. 18A and 18B, an insulating barrier material is deposited on the first dummy gate material layer DG1, and the resulting structure is polished.

The deposition of the insulating barrier material may be performed such that the respective spaces S2a ', S2b ' and S2c ' surrounded by the first dummy gate material layer DG1 are filled with the insulating barrier material. Then, the first dummy gate material layer DG1 and the insulation barrier 151 may be polished down to the line CP to planarize an upper surface of the resulting structure. Accordingly, the insulation barrier 151 may be formed to contact the exposed region of the device isolation layer 105.

The first dummy gate material layer DG1 may be exposed in regions corresponding to the first and second active fins AF1 and AF2 through a polishing process (or a planarization process). Accordingly, the first to third insulation barriers 151A, 151B, and 151C may be provided in the respective spaces S2a ', S2B ', and S2C '. The first to third insulation barriers 151A, 151B, and 151C may have different widths w1, w2, and w3, and may have the same height. As such, the width of the insulating barrier may be determined by the spacing of adjacent active fins.

Referring to fig. 19A and 19B, a second dummy gate material layer DG2 is formed on the first dummy gate material layer DG 1.

By forming a second dummy gate material layer DG2 on the first dummy gate material layer DG1 through a second deposition process, the height of the final dummy gate structure DG may be adjusted. In this way, the final dummy gate structure DG may be formed by more than two deposition processes that form the first dummy gate material layer DG1 and the second dummy gate material layer DG2, respectively. Prior to the second deposition process, the planarized surface of the first dummy gate material layer DG1 may be cleaned. In some example embodiments, the second dummy gate material layer DG2 may be the same material as the first dummy gate material layer DG 1. For example, the second dummy gate material layer DG2 may be polysilicon.

Fig. 20 and 21 are plan views illustrating a process (replacement process) of a method of manufacturing a semiconductor device according to an example embodiment, fig. 22 is a sectional view taken along line XXII-XXII ' of fig. 20, and fig. 23A and 23B are sectional views taken along line XXIIIA-XXIIIA ' and line XXIIIB-XXIIIB ' of fig. 21.

Referring to fig. 20 and 22, a plurality of dummy gate patterns DGPs are formed by patterning the dummy gate structures DG, and an interlayer dielectric layer 115 is provided between the dummy gate patterns such that upper surfaces of the dummy gate patterns DGPs are exposed through a polishing process.

The first dummy gate material layer DG1 and the second dummy gate material layer DG2 are patterned to form a plurality of dummy gate patterns DGP extending in the second direction D2. The gate spacers 133 may be formed on side surfaces of the plurality of dummy gate patterns DGPs and extend in the second direction D2. For example, the gate spacer 133 may include silicon oxide or silicon nitride (e.g., SiN, SiCN, SiON, or SiOCN).

The interlayer insulating layer 115 may be formed to fill the space between the dummy gate patterns DGP, with the gate spacers 133 provided on the side surfaces of the dummy gate patterns DGP. For example, the inter-level dielectric layer 115 may include a low dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride SiON, SiOCN, or fluorine-doped silicate glass FSG). In some example embodiments, the interlayer dielectric layer 115 may include the same material as an insulating material for the device isolation layer 105.

A planarization process, such as an etch-back or a chemical mechanical polishing process, is performed to planarize an upper surface of the dummy gate pattern DGP having the gate spacers 133 and an upper surface of the interlayer insulating layer 115. Accordingly, the upper surface of the dummy gate pattern DGP may be exposed.

Referring to fig. 23A and 23B and fig. 21, a gate isolation layer 155 is formed in one region of the dummy gate pattern DGP such that the dummy gate pattern DGPs are separated.

The present process may be performed using a mask in which the gate cutting region is not blocked, so that an isolation hole is formed in the adjacent dummy gate pattern DGP. The isolation holes may separate the dummy gate pattern DGP into a plurality of dummy gate patterns (e.g., first and second dummy gate patterns). A portion of the first insulation barrier 151A and a portion of the second insulation barrier 151B may be exposed through the isolation hole. The gate isolation layer 155 may be formed by filling the isolation hole with an insulating material. The gate isolation layer 155 may be connected to exposed regions of each of the first and second insulation barriers 151A and 151B to form the gate cutting structure 150. For example, the insulating material for the gate isolation layer 155 may be nitride, such as silicon nitride, and may be formed of the same insulating material as that for the first and second insulating barriers 151A and 151B.

After the gate isolation layer 155 is formed, a replacement process may be performed. For example, the dummy gate pattern may be removed to expose a portion of the active fin, a gate dielectric film may be formed along at least a portion of the active fin, and the space in which the dummy gate pattern is removed may be filled with a gate electrode material, thereby manufacturing the semiconductor device shown in fig. 12 to 15B.

In addition, an additional interlayer insulating layer may be formed on the interlayer insulating layer to cover an upper surface of the gate structure. Adjacent active fin regions of the gate structure may then be exposed, and source/drain regions may be formed. For example, a selective epitaxial SEG process may be used to form source/drain regions from the active fin. Next, a desired semiconductor device may be manufactured by forming contact plugs connected to these source/drain regions and gate electrodes of the gate structures.

Fig. 24 is a block diagram illustrating an electronic apparatus including a semiconductor device according to an example embodiment.

Referring to fig. 24, the electronic device 1000 according to the present exemplary embodiment may include a communication unit 1010, an input unit 1020, an output unit 1030, a memory 1040, and a processor 1050.

The communication unit 1010 may include a wired/wireless communication module, a wireless internet module, a short-range module, a GPS module, a mobile communication module, and the like. The wired/wireless communication module included in the communication unit 1010 may be connected to an external network according to various communication standards to transmit and receive data.

The input unit 1020 may include a mechanical switch, a touch screen, a voice recognition module, etc., provided by a user to control the operation of the electronic device 1000. In addition, the input unit 1020 may include a mouse operated by a trackball method, a laser pointer, or the like, or a finger mouse device, and may further include various sensor modules through which a user may input data.

The output unit 1030 may output information processed in the electronic device 1000 in the form of voice or images, and the memory 1040 may store programs, data, and the like for processing and control of the processor 1050. Processor 1050 can transfer commands to memory 1040 according to the desired operation to store or retrieve data.

The memory 1040 may be embedded in the electronic device 1000 or in communication with the processor 1050 via a separate interface. When communicating with the processor 1050 via a separate interface, the processor 1050 can store data to the memory 1040 or retrieve data via various interface standards such as SD, SDHC, SDXC, MICRO SD, USB, and the like.

The processor 1050 controls the operation of each unit included in the electronic device 1000. The processor 1050 may perform control and processing related to voice calls, video calls, data communications, etc., or may perform control and processing for multimedia playback and management. In addition, the processor 1050 may process an input transmitted from a user through the input unit 1020 and output the result through the output unit 1030. Further, the processor 1050 can store data required to control the operation of the electronic device 1000 in the memory 1040 or retrieve data from the memory 1040 as described above. At least one of the processor 1050 and the memory 1040 may include a semiconductor device according to various example embodiments as described above with reference to fig. 1-5 and 12-15B.

Fig. 25 is a schematic diagram illustrating a system including a semiconductor device according to an example embodiment.

Referring to fig. 25, the system 2000 may include a controller 2100, an input/output unit 2200, a memory 2300, and an interface 2400. System 2000 may be a mobile system or a system that transmits or receives information. The mobile system may be a PDA, portable computer, web tablet, wireless telephone, mobile telephone, digital music player or memory card.

The controller 2100 may execute programs and control the system 2000. The controller 2100 may be, for example, a microprocessor, digital signal processor, microcontroller, or similar device as described above.

Input/output unit 2200 may be used to input or output data to system 2000. The system 2000 may be connected to an external device (e.g., a personal computer or a network) using the input/output unit 2200 to exchange data with the external device. The input/output unit 2200 may be, for example, a keypad, a keyboard, or a display.

The memory 2300 may store code and/or data for the operation of the controller 2100 and/or may store data processed in the controller 2100.

The interface 2400 may be a data transmission path between the system 2000 and other external devices. The controller 2100, the input/output unit 2200, the memory 2300, and the interface 2400 may communicate with each other via a bus 2500.

At least one of the controller 2100 or the memory 2300 may include a semiconductor device according to various example embodiments of the inventive concept as described above with reference to fig. 1 through 5 and 12 through 15B.

As described above, according to some example embodiments of the inventive concepts, a self-aligned process may be used to form an insulation barrier between active fins before patterning dummy gate structures, which may be introduced into an undercut structure. The two-layer gate cut structure may be provided by forming an upper cut structure connected to a portion of the insulating barrier after patterning the dummy gate structure. Accordingly, the limitation of patterning in the dummy gate cutting process in the related art can be overcome, and the yield and characteristics can be greatly improved.

Various advantages and effects of the inventive concept are not limited to the above description, and some additional advantages and effects may be determined in understanding the example embodiments described herein.

Although a few example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept as defined by the appended claims.

This application claims the benefit of priority from korean patent application No. 10-2018-0108143, filed in the korean intellectual property office at 11/9/2018, the disclosure of which is incorporated herein by reference in its entirety.