阅读说明：本技术 竖向延伸存储器单元串的阵列及用于形成竖向延伸存储器单元串的阵列的方法 (Array of vertically-extending memory cell strings and method for forming array of vertically-extending memory cell strings ) 是由 J·D·霍普金斯 G·A·哈勒 T·J·约翰 A·A·汉德卡 C·拉森 K·舍罗特瑞 于 2019-09-06 设计创作，主要内容包括：本申请案涉及竖向延伸存储器单元串的阵列及用于形成竖向延伸存储器单元串的阵列的方法。一种用于形成竖向延伸存储器单元串的阵列的方法包括形成包括垂直交替绝缘层及字线层的堆叠。堆叠包括堆叠的第一层与第二层之间的蚀刻停止层。蚀刻停止层具有与绝缘层及字线层的组合物不同的组合物。进行到蚀刻停止层上方的绝缘层及字线层中直到蚀刻停止层的蚀刻,以形成具有包括蚀刻停止层的个别基底的沟道开口。穿透蚀刻停止层以使沟道开口中的个别者延伸穿过蚀刻停止层。在使个别沟道开口延伸穿过蚀刻停止层之后,进行到蚀刻停止层下方的绝缘层及字线层中且穿过绝缘层及字线层的蚀刻,以使个别沟道开口更深地延伸到蚀刻停止层下方的堆叠中。(The present application relates to arrays of vertically extending memory cell strings and methods for forming arrays of vertically extending memory cell strings. A method for forming an array of vertically extending memory cell strings includes forming a stack including vertically alternating layers of insulation and word lines. The stack includes an etch stop layer between the first and second layers of the stack. The etch stop layer has a composition different from the composition of the insulating layer and the word line layer. Etching is performed into the insulating layer and the word line layer above the etch stop layer to form channel openings with respective substrates including the etch stop layer. The etch stop layer is penetrated such that individual of the trench openings extend through the etch stop layer. After extending the individual channel openings through the etch stop layer, an etch into and through the insulating layer and the word line layer below the etch stop layer is performed to extend the individual channel openings deeper into the stack below the etch stop layer.)

1. A method for forming an array of vertically extending memory cell strings, comprising:

forming a stack comprising vertically alternating layers of insulation and word line, the stack comprising an etch stop layer between first and second layers of the stack, the etch stop layer having a composition different from a composition of the layers of insulation and word line;

etching into the insulating layer and the word line layer above the etch stop layer until the etch stop layer to form channel openings with individual substrates including the etch stop layer;

penetrating the etch stop layer to extend individual of the channel openings through the etch stop layer;

after extending the individual channel openings through the etch stop layer, etching into and through the insulating layer and the word line layer below the etch stop layer to extend the individual channel openings deeper into the stack below the etch stop layer; and

transistor channel material is formed vertically in the individual channel openings along the etch stop layer and along the insulating layer and the word line layer above and below the etch stop layer.

2. The method of claim 1, wherein the first layer is a top layer of the stack and the second layer is a bottom layer of the stack.

3. The method of claim 1, wherein the etch stop layer is insulating.

4. The method of claim 1, wherein the etch stop layer comprises an oxide comprising at least one of Mg and Hf.

5. The method of claim 4, wherein the oxide comprises Mg.

6. The method of claim 4, wherein the oxide comprises Hf.

7. The method of claim 4, wherein the oxide comprises Mg and Hf.

8. The method of claim 4, wherein the oxide comprises Al.

9. The method of claim 4, wherein the oxide comprises Si.

10. The method of claim 1, comprising forming a liner layer along sidewalls of the respective channel openings prior to the penetrating, and at least a portion of the liner layer persists during the penetrating.

11. The method of claim 10, comprising removing the liner after the penetrating.

12. The method of claim 11, comprising removing the liner layer before the etching into and through the insulating layer and the word line layer below the etch stop layer to extend the individual channel openings deeper into the stack below the etch stop layer.

13. The method of claim 10, comprising:

forming the liner layer across the individual etch stop layer bases prior to the penetrating; and

removing the liner layer across a central portion of the individual etch stop layer bases prior to the penetrating.

14. The method of claim 1, wherein the etching into the etch stop layer partially overetches into the etch stop layer.

15. The method of claim 14, wherein the etching into the etch stop layer overetches into less than half of a vertical thickness of the etch stop layer.

16. The method of claim 1, wherein the penetrating comprises a dry anisotropic etch of the etch stop layer.

17. The method of claim 1, wherein the penetrating comprises wet etching of the etch stop layer.

18. The method of claim 1, wherein the penetrating comprises etching the etch stop layer radially outward relative to the individual channel openings to form annular recesses protruding radially outward relative to the individual channel openings.

19. The method of claim 18, further comprising forming transistor charge storage material in the individual channel openings, portions of the charge storage material being formed within the annular recess.

20. The method of claim 18, further comprising forming transistor charge blocking material in the individual channel openings, portions of the charge blocking material being formed within the annular recess.

21. The method of claim 18, further comprising forming a transistor charge blocking material and a transistor charge storage material in the individual channel openings, portions of the charge blocking material and portions of the transistor charge storage material being formed within the annular recess.

22. The method of claim 1, comprising:

providing the word line layer to include a control gate material having terminal ends corresponding to control gate regions of individual memory cells, a charge storage material between the transistor channel material and the control gate regions, an insulating charge transport material between the transistor channel material and the charge storage material, and a charge blocking region between the charge storage material and individual of the control gate regions; and

the control gate material is provided after forming the transistor channel material.

23. The method of claim 22, wherein the etch stop layer is one of the word line layers, and further comprising replacing the etch stop layer with the control gate material after forming the transistor channel material.

24. The method of claim 1, comprising:

providing the word line layer to include a control gate material having terminal ends corresponding to control gate regions of individual memory cells, a charge storage material between the transistor channel material and the control gate regions, an insulating charge transport material between the transistor channel material and the charge storage material, and a charge blocking region between the charge storage material and individual of the control gate regions; and

the control gate material is provided prior to forming the transistor channel material.

25. The method of claim 1, wherein the etch stop layer is one of the insulating layers.

26. A method for forming an array of vertically extending memory cell strings, comprising:

forming upper and lower stacks individually comprising vertically alternating insulating layers and word line layers;

forming a lower channel opening in the lower stack;

forming upper channel openings into the upper stack to individual ones of the lower channel openings to form interconnected channel openings individually comprising one of the individual ones of the lower channel openings and one of the individual ones of the upper channel openings;

at least one of the upper and lower stacks comprises an in-stack etch stop layer between a top layer and a bottom layer of the respective upper or lower stack, the in-stack etch stop layer having a composition different from a composition of the insulating layer and the word line layer of the respective upper or lower stack;

the forming of at least one of all of the lower channel openings and all of the upper channel openings comprises:

etching into the insulating layer and the word line layer above the in-stack etch stop layer until the in-stack etch stop layer to form the respective lower channel opening or the upper channel opening to have a respective substrate comprising the in-stack etch stop layer;

penetrating the intra-stack etch stop layer to extend individual ones of the respective lower channel openings or the upper channel openings through the intra-stack etch stop layer; and

after extending the individual channel openings through the in-stack etch stop layer, etching into and through the insulating layer and the word line layer within the stack etch stop layer to extend the respective individual upper or lower channel openings deeper into the respective upper or lower stack within the stack etch stop layer; and

transistor channel material is formed vertically in the respective upper and lower channel openings along the in-stack etch stop layer and along the insulating layer and the wordline layer above and below the in-stack etch stop layer.

27. An array of vertically extending memory cell strings, comprising:

a vertical stack of alternating layers of insulation and word line layers, a majority of the insulation layers comprising silicon dioxide, at least one of the insulation layers between a top layer and a bottom layer of the stack having a different composition than the majority of insulation layers, the at least one different composition insulation layer comprising an oxide comprising at least one of Mg and Hf, the word line layers having terminal ends corresponding to control gate regions of individual memory cells, the control gate regions individually comprising portions of word lines in individual of the word line layers;

charge blocking regions of the individual memory cells extending vertically along the individual control gate regions;

charge storage material of the individual memory cells extending vertically along individual ones of the charge blocking regions;

a string of channel material extending vertically through the word line layer, the majority of insulating layers, and the at least one insulating layer comprising the oxide including at least one of Mg and Hf; and

an insulating charge transport material transverse between the channel material and the charge storage material.

28. The array of claim 27, wherein the etch stop layer comprises an oxide comprising at least one of Mg and Hf.

29. The array of claim 28, wherein the oxide comprises Mg.

30. The array of claim 28, wherein the oxide comprises Hf.

31. The array of claim 28, wherein the oxide comprises Mg and Hf.

32. The array of claim 28, wherein the oxide comprises Al.

33. The array of claim 28, wherein the oxide comprises Si.

34. An array of vertically extending memory cell strings, comprising:

a vertical stack of alternating layers of insulation and word line layers, a majority of the insulation layers comprising a first insulation composition, at least one of the insulation layers between a top layer and a bottom layer of the stack comprising a second insulation composition different from the first insulation composition, the word line layers having terminal ends corresponding to control gate regions of individual memory cells, the control gate regions individually comprising portions of word lines in individual of the word line layers;

charge blocking regions of the individual memory cells extending vertically along the individual control gate regions;

charge storage material of the individual memory cells extending vertically along individual ones of the charge blocking regions;

a string of channel material extending vertically through the word line layer, the insulating layer comprising the first insulating composition, and the at least one insulating layer comprising the second insulating composition;

an insulating charge transport material transverse between the channel material and the charge storage material; and

the at least one insulating layer comprising the second insulating composition having an annular recess projecting radially outward relative to an individual one of the strings of the channel material, a portion of the charge storage material being within the annular recess.

35. The array of claim 34, wherein the first insulating composition comprises silicon dioxide.

36. The array of claim 34, wherein the second insulating composition comprises an oxide comprising at least one of Mg and Hf.

37. The array of claim 34, wherein the charge blocking region comprises a charge blocking material of a different composition than the charge storage material, a portion of the charge blocking material being within the annular recess radially outward of the charge storage material.

Technical Field

Embodiments disclosed herein relate to arrays of vertically extending memory cell strings and methods for forming arrays of vertically extending memory cell strings.

Background

Memory is one type of integrated circuit and is used in computer systems to store data. The memory may be fabricated in one or more arrays of individual memory cells. The memory cells can be written to or read from using digit lines (which can also be referred to as bit lines, data lines, or sense lines) and access lines (which can also be referred to as word lines). Sense lines can conductively interconnect memory cells along columns of the array, and access lines can conductively interconnect memory cells along rows of the array. Each memory cell is uniquely addressable by a combination of a sense line and an access line.

The memory cells may be volatile, semi-volatile, or nonvolatile. Non-volatile memory cells may store data for extended periods in the absence of power. Non-volatile memory is conventionally designated as memory having a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed/rewritten to maintain data storage. Volatile memory may have a retention time of milliseconds or less. Regardless, the memory cells are configured to hold or store memory in at least two different selectable states. In a binary system, the state is considered to be "0" or "1". In other systems, at least some individual memory cells may be configured to store more than two layers or states of information.

A field effect transistor is one type of electronic component that may be used in a memory cell. These transistors include a pair of conductive source/drain regions with a semiconductive channel region therebetween. A conductive gate is adjacent to the channel region and separated therefrom by a thin gate insulator. Applying an appropriate voltage to the gate allows current to flow from one of the source/drain regions to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. The field effect transistor may also include additional structures, such as a reversibly programmable charge storage region as part of the gate construction between a gate insulator and a conductive gate.

Flash memory is one type of memory and has numerous uses in modern computers and devices. For example, modern personal computers may have a BIOS stored on a flash memory chip. As another example, it is becoming increasingly common for computers and other devices to utilize flash memory in solid state drives instead of conventional hard drives. As yet another example, flash memory is popular in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized and provides the ability to remotely update devices for enhanced features.

NAND can be the infrastructure of integrated flash memory. A NAND cell unit includes at least one select device coupled in series to a series combination of memory cells (where a series combination is commonly referred to as a NAND string). The NAND architecture may be configured in a three-dimensional arrangement including vertically stacked memory cells comprising vertical transistors that can be programmed in reverse. Control or other circuitry may be formed below the vertically stacked memory cells.

Disclosure of Invention

One aspect of the invention provides a method for forming an array of vertically extending memory cell strings, comprising: forming a stack comprising vertically alternating layers of insulation and word line, the stack comprising an etch stop layer between first and second layers of the stack, the etch stop layer having a composition different from a composition of the layers of insulation and word line; etching into the insulating layer and the word line layer above the etch stop layer until the etch stop layer to form channel openings with individual substrates including the etch stop layer; penetrating the etch stop layer to extend individual of the channel openings through the etch stop layer; after extending the individual channel openings through the etch stop layer, etching into and through the insulating layer and the word line layer below the etch stop layer to extend the individual channel openings deeper into the stack below the etch stop layer; and vertically forming transistor channel material in the individual channel openings along the etch stop layer and along the insulating layer and the wordline layer above and below the etch stop layer.

Another aspect of the invention provides a method for forming an array of vertically extending memory cell strings, comprising: forming upper and lower stacks individually comprising vertically alternating insulating layers and word line layers; forming a lower channel opening in the lower stack; forming upper channel openings into the upper stack to individual ones of the lower channel openings to form interconnected channel openings individually comprising one of the individual ones of the lower channel openings and one of the individual ones of the upper channel openings; at least one of the upper and lower stacks comprises an in-stack etch stop layer between a top layer and a bottom layer of the respective upper or lower stack, the in-stack etch stop layer having a composition different from a composition of the insulating layer and the word line layer of the respective upper or lower stack; the forming of at least one of all of the lower channel openings and all of the upper channel openings comprises: etching into the insulating layer and the word line layer above the in-stack etch stop layer until the in-stack etch stop layer to form the respective lower channel opening or the upper channel opening to have a respective substrate comprising the in-stack etch stop layer; penetrating the intra-stack etch stop layer to extend individual ones of the respective lower channel openings or the upper channel openings through the intra-stack etch stop layer; and after extending the individual channel openings through the in-stack etch stop layer, etching into and through the insulating layer and the word line layer below the in-stack etch stop layer to extend the respective individual upper or lower channel openings deeper into the respective upper or lower stack below the in-stack etch stop layer; and vertically forming transistor channel material in the respective upper and lower channel openings along the in-stack etch stop layer and along the insulating layer and the wordline layer above and below the in-stack etch stop layer.

Another aspect of the invention provides an array of vertically extending memory cell strings, comprising: a vertical stack of alternating layers of insulation and word line layers, a majority of the insulation layers comprising silicon dioxide, at least one of the insulation layers between a top layer and a bottom layer of the stack having a different composition than the majority of insulation layers, the at least one different composition insulation layer comprising an oxide comprising at least one of Mg and Hf, the word line layers having terminal ends corresponding to control gate regions of individual memory cells, the control gate regions individually comprising portions of word lines in individual of the word line layers; charge blocking regions of the individual memory cells extending vertically along the individual control gate regions; charge storage material of the individual memory cells extending vertically along individual ones of the charge blocking regions; a string of channel material extending vertically through the word line layer, the majority of insulating layers, and the at least one insulating layer comprising the oxide including at least one of Mg and Hf; and an insulating charge transport material transverse between the channel material and the charge storage material.

Another aspect of the invention provides an array of vertically extending memory cell strings, comprising: a vertical stack of alternating layers of insulation and word line layers, a majority of the insulation layers comprising a first insulation composition, at least one of the insulation layers between a top layer and a bottom layer of the stack comprising a second insulation composition different from the first insulation composition, the word line layers having terminal ends corresponding to control gate regions of individual memory cells, the control gate regions individually comprising portions of word lines in individual of the word line layers; charge blocking regions of the individual memory cells extending vertically along the individual control gate regions; charge storage material of the individual memory cells extending vertically along individual ones of the charge blocking regions; a string of channel material extending vertically through the word line layer, the insulating layer comprising the first insulating composition, and the at least one insulating layer comprising the second insulating composition; an insulating charge transport material transverse between the channel material and the charge storage material; and the at least one insulating layer comprising the second insulating composition having an annular recess projecting radially outward relative to an individual of the string of the channel material, a portion of the charge storage material being within the annular recess.

Drawings

FIG. 1 is a diagrammatic, cross-sectional view of a portion of a substrate in process in accordance with an embodiment of the invention.

Fig. 2 is a view of the fig. 1 substrate at a processing step subsequent to that shown by fig. 1 and taken through line 2-2 in fig. 3.

Fig. 3 is a view taken through line 3-3 in fig. 2.

Fig. 4 is a view of the fig. 3 substrate at a processing step subsequent to that shown by fig. 3.

Fig. 5 is a view of the fig. 4 substrate at a processing step subsequent to that shown by fig. 4.

Fig. 6 is a view of the fig. 5 substrate at a processing step subsequent to that shown by fig. 5 and taken through line 6-6 in fig. 7.

Fig. 7 is a view taken through line 7-7 in fig. 6.

Fig. 8 is a view of the fig. 7 substrate at a processing step subsequent to that shown by fig. 7.

Fig. 9 is a view of the fig. 8 substrate at a processing step subsequent to that shown by fig. 8.

Fig. 10 is a view of the fig. 9 substrate at a processing step subsequent to that shown by fig. 9 and taken through line 10-10 in fig. 11.

Fig. 11 is a view taken through line 11-11 in fig. 10.

Fig. 11A is an enlarged view of a portion of the substrate shown in fig. 11.

Fig. 12 is a view of the fig. 11 substrate at a processing step subsequent to that shown by fig. 11.

FIG. 13 is a diagrammatic, cross-sectional view of a portion of a substrate in process in accordance with an embodiment of the invention.

Fig. 14 is a view of the fig. 13 substrate at a processing step subsequent to that shown by fig. 13.

Fig. 15 is a view of the fig. 14 substrate at a processing step subsequent to that shown by fig. 14.

Fig. 16 is a view of the fig. 15 substrate at a processing step subsequent to that shown by fig. 15.

FIG. 17 is a diagrammatic, cross-sectional view of a portion of a substrate in process in accordance with an embodiment of the invention.

Fig. 18 is a view of the fig. 17 substrate at a processing step subsequent to that shown by fig. 17.

Fig. 19 is a view of the fig. 18 substrate at a processing step subsequent to that shown by fig. 18.

Fig. 20 is a view of the fig. 19 substrate at a processing step subsequent to that shown by fig. 19.

Fig. 21 is a view of the fig. 20 substrate at a processing step subsequent to that shown by fig. 20.

FIG. 22 is a diagrammatic, cross-sectional view of a portion of a substrate in process in accordance with an embodiment of the invention.

FIG. 23 is a diagrammatic, cross-sectional view of a portion of a substrate in process in accordance with an embodiment of the invention.

Fig. 24 is a view of the fig. 23 substrate at a processing step subsequent to that shown by fig. 23.

Detailed Description

Embodiments of the present invention encompass methods for forming an array of vertically extending transistors and/or memory cell strings, such as a NAND or other memory cell array having peripheral control circuitry under the array (e.g., CMOS under the array). Embodiments of the present invention encompass so-called "gate last" or "replacement gate" processes, so-called "gate first" processes, and other processes that are either now existing or developed in the future independent of when the transistor gates are formed. Embodiments of the present invention also contemplate vertically extending memory cell (e.g., NAND or other memory cell) string arrays independent of the method of fabrication. A first example method embodiment is described with reference to fig. 1-12, which may be considered a "gate last" or "replacement gate" process.

Fig. 1 shows a substrate construction 10 in the course of a method of forming an array 12 of vertically extending strings of transistors and/or memory cells. The substrate construction 10 includes a base substrate 11 having any one or more of conductive/conductor/conductive (i.e., electrically conductive herein), semi-conductive/semiconductor/semi-conductive, or insulative/insulator/insulative (i.e., electrically insulative herein). Various materials have been formed vertically above the base substrate 11. The material may be beside, vertically inward, or vertically outward of the material depicted in fig. 1. For example, other partially or fully fabricated components of the integrated circuit may be provided somewhere over, around, or within the base substrate 11. Control and/or other peripheral circuitry for operating components within an array of vertically extending strings of memory cells (e.g., array 12) may also be fabricated and may or may not be entirely or partially within the array or sub-array. Furthermore, multiple sub-arrays may also be fabricated and operated independently, in series, or otherwise with respect to each other. In this document, "subarrays" may also be considered as arrays.

The substrate construction 10 includes a stack 18, the stack 18 including vertically alternating layers of insulation 20 and word line layers 22 directly over an example conductively-doped semiconductor material 16 (e.g., conductively-doped polysilicon). Conductive material 16 may comprise a portion of control circuitry (e.g., array bottom peripheral circuitry) for controlling read and write access to transistors and/or memory cells to be formed within array 12. The insulating layer 20 includes an insulating first material 24 (e.g., silicon dioxide). Word line layer 22 includes a second material 26 (e.g., silicon nitride, and whichever may be fully or partially sacrificial) having a different composition than the first material 24. Only a small number of layers 20 and 22 are shown, with it being more likely that the stack 18 includes tens, hundreds, or more, etc. of layers 20 and 22.

The stack 18 includes an etch stop layer 14 between a top layer 20 or 22 and a bottom layer 20 or 22 (e.g., a first layer and a second layer) of the stack 18, and which has a different composition than the composition of the insulating layer 20 and the word line layer 22. The etch stop layer 14 may have the same or different vertical thickness as any one or more of the insulating layer 20 and/or the word line 22. The etch stop layer may be one of the insulating layers 20 (e.g., one of the insulating layers 20 is entirely composed of an etch stop material, as described below and not shown). The etch stop layer may be one of word line layers 22 (not shown), e.g., it is entirely composed of an etch stop material, as described below, e.g., as may occur in a back gate or replacement gate process. Regardless, in one embodiment, the etch stop layer is insulating. In one embodiment, the etch stop layer is conductive. In one embodiment, the etch stop layer comprises an oxide comprising at least one of Mg and Hf (e.g., Mg)_xO_y、Hf_xO_y、Mg_xHf_yO_zAt least one of an oxide having one or more metals (other than at least one of Mg and Hf, etc.), and which may or may not be stoichiometric, in one such embodiment including Al (e.g., Al)_wMg_xHf_yO_z、Al_xMg_yO_z、Al_xHf_yO_zEtc., and which may or may not be stoichiometric), and in one such embodiment comprises Si (e.g., Si)_xMg_yO_z、Si_xHf_yO_z、Si_wMg_xHf_yO_z、Si_wAl_xMg_yO_z、Si_wAl_xHf_yO_z、Si_vAl_wMg_xHf_yO_zEtc., and which may or may not be stoichiometric).

Referring to fig. 2 and 3, etching has been performed into the insulating layer 20 and the word line layer 22 above the etch stop layer 14 to form channel openings 25 having respective substrates 21 including the etch stop layer 14. In one embodiment and as shown, the etch to the etch stop layer 14 partially overetches into the etch stop layer 14, and in one embodiment and as shown overetch into less than half of the vertical thickness of the etch stop layer 14. Etching partially into the etch stop layer 14 may improve critical dimension control of the trench opening, and it may be facilitated by creating a more square (right angle) between the sidewalls of the trench opening and the substrate. This may also control (reduce) undesirable radially inward tapering of the channel opening deeper into the stack. Regardless, and by way of example only, the channel openings 25 are shown arranged in groups or columns of staggered rows of four openings 25 per row. Any alternative existing or future developed arrangements and configurations may be used. To facilitate distinguishing one series or orientation of features from another series or orientation of features, "rows" and "columns" are used in this document, and components have been or may be formed therealong. Independent of function, "rows" and "columns" are used synonymously with respect to any series of regions, components, and/or features. Regardless, the rows can be straight and/or curved and/or parallel and/or non-parallel with respect to each other, as can the columns. Further, the rows and columns may intersect at 90 ° relative to each other or at one or more other angles. Other circuitry, which may or may not be part of the peripheral circuitry, may be between the conductively doped semiconductor material 16 and the stack 18.

Referring to fig. 4, the etch stop layer 14 has been penetrated such that the respective channel openings 25 extend through the etch stop layer 14. Thereafter, etching has proceeded into insulating layer 20 and word line layer 22 below etch stop layer 14 and through insulating layer 20 and word line layer 22 below etch stop layer 14 to further open respective trenches 25Extending deep into the stack 18 below the etch stop layer 14. Example methods of penetrating the etch stop layer 14 include one or both of dry anisotropic etching or wet etching of the etch stop layer 14. This etch may be performed selectively with respect to materials 24 and 26, for example as shown. The skilled artisan will be able to select one or more suitable etch chemistries depending on the composition of the material of etch stop layer 14, and compare the compositions of materials 24 and 26 depending on the desired selectivity of the etch, if any, when exposing materials 24 and 26. By way of example, in materials/layers 24, 26 and 14 are silicon dioxide, silicon nitride and Mg, respectively_xHf_yO_zThe dry chemistry used to etch layer 14 selectively to materials 24 and 26 is Cl₂And the wet chemical is a mixture of hydroxide and ammonia. Usually Mg_xHf_yO_zThe larger the amount of Hf in (1), the more Cl₂And the slower the rate at which the mixture of hydroxide and ammonia etches, and the slower the selectivity to silicon dioxide and/or silicon nitride.

The stack 18 is shown to include only a single etch stop layer 14. Alternatively, more than one etch stop layer may be used in a single stack (e.g., vertically spaced from each other), with the etching of the channel opening 25 stopping on top of or within the respective etch stop layer before etching through the respective etch stop layer and etching under the respective etch stop layer to the next lower etch stop layer.

Transistor channel material is ultimately formed vertically in the respective channel openings along the etch stop layer and along the insulating and word line layers above and below the etch stop layer. In addition, a word line layer is provided that includes control gate material having terminal ends corresponding to control gate regions of individual memory cells. Charge storage material (e.g., floating gate material, such as doped or undoped silicon, or charge trapping material, such as silicon nitride, metal dots, etc.) is provided between the transistor channel material and the control gate region. An insulating charge transport material (e.g., a band gap engineered fabricated structure having a nitrogen-containing material [ e.g., silicon nitride ] sandwiched between two insulator oxides [ e.g., silicon dioxide ]) is provided between the transistor channel material and the charge storage material, and a charge blocking region is provided between the charge storage material and an individual one of the control gate regions.

Figure 5 shows one embodiment in which the charge blocking material 30, charge storage material 32, and charge transport material 34 have been formed vertically in the respective channel openings 25 along the etch stop layer 14 and along the insulating layer 20 and word line layer 22 above and below the etch stop layer 14. Transistor materials 30, 32, and 34 may be formed by depositing their respective thin layers over stack 18 and within respective lower channel openings 25, followed by, for example, planarizing such thin layers at least back to the vertically outermost surface of stack 18. Transistor channel material 36 has then been formed vertically in the respective channel openings 25 along the etch stop layer 14 and along the insulating layer 20 and word line layer 22 above and below the etch stop layer 14. Example channel material 36 includes appropriately doped crystalline semiconductor material such as one or more of silicon, germanium, and so-called III/V semiconductor materials (e.g., GaAs, InP, GaP, and GaN). An example thickness for each of materials 30, 32, 34, and 36 is 25-100 angstroms. The channel opening 25 is shown as comprising a radially central solid dielectric material 38 (e.g., spin-on dielectric, silicon dioxide, and/or silicon nitride). Alternatively, and by way of example only, the radially central portion within the channel opening 25 may include void space (not shown) and/or lack of solid material (not shown).

Referring to fig. 6 and 7, horizontally elongated (fig. 6) trenches 40 have been formed (e.g., by anisotropic etching) into the stack 18, and in one embodiment, to the conductively doped semiconductor material 16 (i.e., at least to the material 16). The lateral edges of the trenches 40 may be used, at least in part, to define the lateral edges of subsequently formed word lines (e.g., access or control gate lines, and not shown in fig. 6 and 7), as described below.

Referring to fig. 8, second material 26 (not shown) of word line layer 22 is selectively etched relative to insulating first material 24 (and in one embodiment, as shown relative to etch stop material 14). The etch chemistry, wherein second material 26 comprises silicon nitride, first material 24 comprises silicon dioxide, and etch stop material 14 comprises an oxide comprising at least one of Mg and Hf, is with H₃PO₄AsLiquid or vapor phase etching of the main etchant.

Referring to fig. 9, control gate material 48 (i.e., conductive material) has been formed through trench 40 to word line layer 22 to be vertically between insulating first material 24. Any suitable conductive material may be used, such as one or both of a metallic material and/or a conductively-doped semiconductor material.

Referring to fig. 10, 11 and 11a, control gate material 48 has been removed from the respective trenches 40. This has resulted in the formation of vertically extending strings 49 of word lines 29 and individual transistors and/or memory cells 56. In one embodiment and as shown, the string 49 is formed to be vertical or within 10 ° of vertical. The approximate locations of transistors and/or memory cells 56 are indicated by brackets in fig. 11A, and partially by dashed outlines in fig. 10 and 11, where transistors and/or memory cells 56 are substantially ring-shaped or ring-shaped in the depicted example. The control gate material 48 has terminal ends 50 corresponding to control gate regions 52 of individual transistors and/or memory cells 56 (fig. 11A). The control gate regions 52 in the depicted embodiment comprise individual portions of individual word lines 29.

A charge blocking region, such as charge blocking material 30, is between the charge storage material 32 and the respective control gate region 52. The charge blocking has the following function in the memory cell: in the program mode, the charge blocking may prevent charge carriers from passing from the charge storage material (e.g., floating gate material, charge trapping material, etc.) towards the control gate, and in the erase mode, the charge blocking may prevent charge carriers from flowing from the control gate into the charge storage material. Thus, the charge blocking may serve to block charge migration between the control gate region and the charge storage material of the individual memory cell. As shown, the example charge blocking region includes an insulator material 30. By way of further example, the charge blocking region may comprise a laterally (e.g., radially) outer portion of a charge storage material (e.g., material 32), wherein such charge storage material is insulating (e.g., in the absence of any material of different composition between the insulating charge storage material 32 and the conductive material 48). Regardless, as an additional example, the interface of the charge storage material and the conductive material of the control gate may be sufficient to serve as a charge blocking region in the absence of any separate composition insulator material 30. Further, the interface of conductive material 48 and material 30 (when present) in combination with insulator material 30 may function together as a charge blocking region, and alternatively or additionally, may be a laterally outer region of insulating charge storage material (e.g., silicon nitride material 32).

Referring to fig. 12, a liner of insulating material 55 has been formed in individual trenches 40 (e.g., silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, combinations of these, etc.) over and vertically along the sidewalls of such trenches. Another material 57 (dielectric and/or silicon-containing, such as polysilicon) has been formed in the individual trenches 40 vertically along the insulating material liner 55 and laterally across between the insulating material liners 55. Any other attributes or aspects as shown and/or described herein with respect to other embodiments may be used.

An alternative example method embodiment in accordance with the present invention is next described with reference to fig. 13-16 and substrate construction 10 a. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix "a" or with different numeral designations. Referring to fig. 13, an example process is shown as may occur immediately following the example process shown by fig. 3. The liner 39 has been formed along the sidewalls of the respective trench openings 25 prior to penetrating the etch stop layer 14, and at least a portion of the liner 39 will remain during penetration through the etch stop layer 14. In one embodiment and as shown, liner layer 39 has been formed across the individual etch stop layer substrates 21.

Fig. 14 shows subsequent processing in which the liner layer 39 has been removed across the central portion of the individual etch stop layer substrates 21 prior to penetrating the etch stop layer 14. This may occur, for example, by an anisotropic etch of liner 39 to remove liner 39 substantially over horizontal surfaces.

Referring to fig. 15, the etch stop layer 14 has been penetrated (e.g., by etching), with at least a portion of the liner layer 39 remaining along sidewalls of the respective trench openings 25 above the etch stop layer 14 during this penetrating action. The purpose of including liner layer 39 may be to protect the sidewalls of the trench opening 25 above the etch stop layer 14 during etching through the etch stop layer 14, for exampleFor example, if the etch chemistry of the etch stop layer 14 can damage or etch one of the materials 24 and 26 of the sidewalls of the trench opening 25. An example material for the underlayer 39 is Al₂O₃. Fig. 15 also shows a subsequent etch into the insulating layer 20 and word line layer below the etch stop layer 14 and a subsequent etch through the insulating layer 20 and the word line layer 22 to extend the individual channel openings 25 deeper into the stack 18 below the etch stop layer 14.

Fig. 16 shows the removal of liner layer 39 (not shown), such as at the end of the fig. 15 etch. Liner 39 may be alternately removed after penetrating etch stop layer 14 and before (not shown) etching into the layers 20, 22 therebelow or during etching into the word line layer 22 below insulating layer 20 and etch stop layer 14. Regardless, subsequent processing can occur as described and/or shown above. Any other attributes or aspects shown and/or described herein with respect to other embodiments may be used.

Another example embodiment is next described with reference to FIGS. 17-21 with respect to substrate construction 10 b. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix "b" or with different numeral symbols. Fig. 17 shows the example processing as occurs through fig. 3, but with a thicker etch stop layer 14 for clarity.

Fig. 18 shows a subsequent process by which penetrating the etch stop layer 14 includes etching the etch stop layer 14 radially outward relative to the individual channel openings 25 to form annular recesses 41 that project radially outward relative to the individual channel openings 25. Example such an etch can be by wet and/or dry anisotropic etching (e.g., using Cl)₂And/or peroxides and Mg_xHf_yO_zA mixture of ammonia) to etch into the etch stop layer 14 and through the etch stop layer 14. Alternatively, an anisotropic etch may be initially conducted to extend the individual channel openings 25 partially or completely through the etch stop layer 14 to create substantially vertical sidewalls within the etch stop layer 14, followed by a substantially anisotropic etch to form the annular recess 41. In any event, this etch may be timed to prevent removal of the etch stop between immediately adjacent trench openings 25All of the materials of layer 14.

Fig. 19 shows subsequent processing, with liner 39b provided and received within annular recess 41.

Fig. 20 shows subsequent processing in which penetration has occurred through a central portion of liner layer 39b (not shown), then liner layer 39b is removed, and then the layers 20, 22 below etch stop layer 14 are subsequently anisotropically etched to extend the channel opening 25 deeper into stack 18 (as shown). Alternatively, and by way of example only, liner layer 39b (not shown) may not be used, or such liner layer (not shown) may be used and not removed prior to etching into layers 20, 22 below etch stop layer 14.

FIG. 21 shows subsequent processing similar to that shown by FIG. 12 in the initially described embodiment, in which strings 49 and word lines 29 have been formed. In one embodiment, this method includes forming transistor charge blocking material 30 within annular recess 41, forming transistor charge storage material 32 in annular recess 41 in one embodiment, and forming both materials 30 and 32 within annular recess 41 in one embodiment shown. Any other attributes or aspects shown and/or described herein with respect to other embodiments may be used.

The embodiments shown above show examples where control gate material 48 is provided after formation of transistor channel material 36. Furthermore, in one such embodiment as described above, the etch stop layer may be one of the word line layers 22 (not shown), wherein such method further comprises replacing the etch stop layer with a control gate material after forming the transistor channel material.

Alternatively, the control gate material may be provided prior to forming the transistor channel material, for example using the substrate construction 10c shown in fig. 22. Like numerals from the above-described embodiments have been used where appropriate. Fig. 22 shows a starting substrate construction 10c in which a starting word line layer 22 includes control gate material 48 (in place of material 26) as compared to fig. 1. By way of example, processing may then occur in other ways, as described above. Any other attributes or aspects shown and/or described herein with respect to other embodiments may be used.

The methods described and shown above are with respect to forming an array of vertically extending strings of transistors and/or memory cells with respect to a single stack 18. Alternatively, processing may occur with respect to a plurality of stacks including at least upper and lower stacks individually comprising vertically alternating layers of insulating layers and word lines, wherein at least one of the upper and lower stacks is processed as described above in accordance with at least one of such stacks having an etch stop layer. This example method is described with respect to the substrate construction 10d shown in fig. 23 and 24. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix "d" or with different numeral designations. Figure 23 shows an upper stack 35 that has been formed over a previously processed lower stack 18. Lower channel opening 25 has been formed in lower stack 18, e.g., as described above. One or more etch stop layers 14 may be used in the lower stack 18, where only one etch stop layer 14 is shown. Alternatively, no etch stop layer may be used in the lower stack and no etch stop layer may be used in the stack above the lower stack.

Figure 24 shows that upper channel openings 37 have been formed into the upper stack 35 to respective ones of the lower channel openings 25 to form interconnected channel openings 47 that individually include one of the respective lower channel openings 25 and one of the respective upper channel openings 37.

At least one of the upper stack 35 and the lower stack 18 (both shown) includes an etch stop layer 14 within the stack between the top layer and the bottom layer of the respective upper or lower stack ("inner" meaning within the stack where there are multiple stacks formed at different times), and which has a composition different from that of the insulating layer and word line layer of the respective upper or lower stack. The formation of at least one of all of the lower channel openings 25 and all of the upper channel openings 37 includes etching into the insulating layer and the wordline layer above the in-stack etch stop layer to form respective lower channel openings or upper channel openings to have individual substrates including the in-stack etch stop layer (e.g., as described in any of the embodiments above). Then, a penetration through the etch stop layer within the stack has been made to extend individual ones of the respective lower or upper channel openings 25, 37 through the etch stop layer. Etching is then performed into and through the insulating layer and the word line layer within the stack below the etch stop layer to extend the respective upper or lower channel opening deeper into the respective upper or lower stack below the etch stop layer. Transistor channel material is eventually formed in the respective upper and lower channel openings vertically along the etch stop layer within the stack and along the insulating and word line layers above and below the etch stop layer. Any other attributes or aspects shown and/or described herein with respect to other embodiments may be used.

Embodiments of the present invention encompass arrays of vertically extending memory cell strings that are independent of the method of fabrication. However, such an array may have any of the physical attributes described above with respect to method embodiments.

In one embodiment, an array (e.g., 12) of such a vertically extending string (e.g., 49) of memory cells (e.g., 56) includes a vertical stack (e.g., 18 and/or 35) of alternating layers of insulation (e.g., 20) and word lines (e.g., 22). Most insulating layers comprise silicon dioxide. At least one of the insulating layers (e.g., 14) between the top and bottom layers of the stack has a different composition than most of the insulating layers. The at least one different composition insulating layer includes an oxide including at least one of Mg and Hf. The word line layer has terminal ends (e.g., 50) corresponding to control gate regions (e.g., 52) of the individual memory cells. The control gate regions individually comprise portions of word lines (e.g., 29) in individual ones of the word line layers.

The charge blocking regions (e.g., 30) of the individual memory cells extend vertically along the individual control gate regions. The charge storage material (e.g., 32) of the individual memory cells extends vertically along individual ones of the charge blocking regions. A string (e.g., 49) of channel material (e.g., 36) extends vertically through the word line layer, most of the insulating layers, and at least one insulating layer comprising an oxide including at least one of Mg and Hf. An insulating charge transport material (e.g., 34) is transverse between the channel material and the charge storage material. Any other attributes or aspects shown and/or described herein with respect to other embodiments may be used.

Embodiments of the invention include an array (e.g., 12) of vertically extending strings (e.g., 49) of memory cells (e.g., 56). Such an array includes a vertical stack (e.g., 18 and/or 35) of alternating insulating layers (e.g., 20) and word line layers (e.g., 22). Most of the insulating layers include a first insulating composition (e.g., 24). At least one of the insulating layers (e.g., 14) between the top and bottom layers of the stack includes a second insulating composition different from the first insulating composition (e.g., in this particular embodiment, the material of the etch stop layer 14 is insulating). The word line layer has terminal ends (e.g., 50) corresponding to control gate regions (e.g., 52) of the individual memory cells. The control gate regions individually comprise portions of word lines (e.g., 29) in individual ones of the word line layers.

The charge blocking regions (e.g., 30) of the individual memory cells extend vertically along individual ones of the control gate regions. The charge storage material (e.g., 32) of the individual memory cells extends vertically along individual ones of the charge blocking regions. A string of channel material (e.g., 36) extends vertically through the word line layer, the insulating layer comprising a first insulating composition, and at least one insulating layer comprising a second insulating composition. An insulating charge transport material (e.g., 34) is transverse between the channel material and the charge storage material. At least one of the insulating layers comprising the second insulating composition has an annular recess (e.g., 41) protruding radially outward relative to an individual one of the strings of channel material. A portion of the charge storage material is within the annular recess. In one embodiment, the charge blocking region comprises a charge blocking material of a different composition than the charge storage material, and wherein a portion of the charge blocking material is within an annular recess radially outward of the charge storage material. Any other attributes or aspects shown and/or described herein with respect to other embodiments may be used.

In this document, "vertical," "upper," "lower," "top," "bottom," "above," "below," "lower," "below," "upper," and "lower" generally refer to a vertical direction unless otherwise indicated. "horizontal" refers to a general direction along the major substrate surface (i.e., within 10 degrees) and may be relative to the direction in which the substrate is processed during fabrication, and vertical is a direction generally orthogonal to the horizontal direction. References to "perfectly horizontal" are directions along (i.e., without degrees from) the major substrate surface, and may be directions relative to the substrate being processed during fabrication. Further, as used herein, "vertical" and "horizontal" are generally vertical directions relative to each other and independent of the orientation of the substrate in three-dimensional space. In addition, "extending vertically-extending/extending (ing) means a direction angularly away from the perfect horizontal by at least 45 °. Furthermore, the "vertical extension" and horizontal extension (extending) with respect to a field effect transistor) are with reference to the orientation of the channel length of the transistor along which current flows between source/drain regions in operation. For a bipolar junction transistor, "vertically extending" and horizontally extending are references to the orientation of the base length along which current flows between the emitter and collector in operation.

Further, "directly above …" and "directly below …" require at least some lateral overlap (i.e., horizontal) of the two such regions/materials/components relative to each other. Moreover, the use of "over" without "directly" above, requires only portions of the zones/materials/components above one another to be vertically outward of the other (i.e., independent of whether there is any lateral overlap of the two zones/materials/components). Similarly, the use of "under" without "directly" in the foregoing requires only that some portion of the zone/material/component under the other be vertically inward of the other (i.e., independent of whether there is any lateral overlap of two of the zones/materials/components).

Any of the materials, regions, and structures described herein may be homogeneous or heterogeneous, and in any event may be continuous or discontinuous over any material that is overlaid herein. Where one or more example compositions of any material are provided, that material may comprise, consist essentially of, or consist of that one or more compositions. Moreover, unless otherwise specified, each material may be formed using any suitable or yet to be developed technique, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation being examples.

Additionally, "thickness" itself (without a preceding directional adjective) is defined to mean the straight-line distance from the nearest surface of an immediately adjacent material or area of a different composition perpendicularly through a given material or area. In addition, the various materials or regions described herein can have a substantially constant thickness or a variable thickness. If there is a variable thickness, the thickness refers to the average thickness unless otherwise indicated, and since the thickness is variable, this material or region will have some minimum thickness and some maximum thickness. As used herein, for example, if such materials or regions are non-homogeneous, then "different compositions" need only be chemically and/or physically different from those portions of two such materials or regions that may be directly against each other. Where such materials or regions are not homogeneous, a "different composition" need only be those portions of two such materials or regions that are closest to each other that are chemically and/or physically different if the two such materials or regions are not directly against each other. In this document, a material, region or structure is "directly against" another material, region or structure when there is at least some physical touching contact of the materials, regions or structures with respect to each other. In contrast, "above," "upper," "adjacent," "along," and "against," without the foregoing being "directly," encompass "directly against," as well as configurations in which intervening materials, regions, or structures cause the materials, regions, or structures not to be in physical touching contact with respect to one another.

Herein, region-material-components are "electrically coupled" with respect to one another if in normal operation current is able to flow continuously from one to the other and this is achieved primarily through the movement of subatomic positive and/or negative charges when current is sufficiently generated. Another electronic component may be between and electrically coupled to the zone-material-component. In contrast, when a region-material-component is referred to as "directly electrically coupled," there are no intervening electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between the directly electrically coupled region-material-components.

Additionally, a "metallic material" is any one or combination of an elemental metal, a mixture or alloy of two or more elemental metals, and any conductive metal compound.

Herein, "selecting" with respect to etching (etching/ablating), removing (removing/removing), and/or forming (reforming/formatting) is an action of one such material at a rate of at least 2:1 by volume relative to another such material.

Unless otherwise indicated, use of "or" herein encompasses either and both.

Conclusion

In some embodiments, a method for forming an array of vertically extending memory cell strings includes forming a stack including vertically alternating layers of insulation and word lines. The stack includes an etch stop layer between a first layer and a second layer of the stack. The etch stop layer has a composition different from a composition of the insulating layer and the word line layer. Etching is performed into the insulating layer and the word line layer above the etch stop layer and up to the etch stop layer to form channel openings with individual substrates including the etch stop layer. The etch stop layer is penetrated such that individual of the channel openings extend through the etch stop layer. After extending the individual channel openings through the etch stop layer, etching into and through the insulating layer and the word line layer below the etch stop layer is performed to extend the individual channel openings deeper into the stack below the etch stop layer. Transistor channel material is formed vertically in the individual channel openings along the etch stop layer and along the insulating layer and the word line layer above and below the etch stop layer.

In some embodiments, a method for forming an array of vertically extending memory cell strings includes forming upper and lower stacks individually comprising vertically alternating layers of insulation and word lines. A lower channel opening is formed in the lower stack. Forming upper channel openings into the upper stack to individual ones of the lower channel openings to form interconnected channel openings individually comprising one of the individual ones of the lower channel openings and one of the individual ones of the upper channel openings. At least one of the upper and lower stacks comprises an in-stack etch stop layer between a top layer and a bottom layer of the respective upper or lower stack. The in-stack etch stop layer has a composition different from a composition of the insulating layer and the word line layer of the respective upper or lower stack. The forming of at least one of all of the lower channel openings and all of the upper channel openings comprises etching into the insulating layer and the word line layer above the in-stack etch stop layer to form the respective lower channel openings or the upper channel openings to have individual substrates comprising the in-stack etch stop layer. Penetrating an etch stop layer within the stack to extend individual ones of the respective lower channel openings or the upper channel openings through the etch stop layer. After extending the individual channel openings through the intra-stack etch stop layer, etching into and through the insulating layer and the word line layer within the stack etch stop layer is performed to extend the respective individual upper or lower channel openings deeper into the respective upper or lower stack below the intra-stack etch stop layer. Transistor channel material is formed vertically in the respective upper and lower channel openings along the in-stack etch stop layer and along the insulating layer and the word line layer of the in-stack etch stop layer.

In some embodiments, an array of vertically extending memory cell strings includes a vertical stack of alternating layers of insulation and word lines. Most of the insulating layer comprises silicon dioxide. At least one of the insulating layers between the top and bottom layers of the stack has a different composition than the majority of insulating layers. The at least one different composition insulating layer includes an oxide including at least one of Mg and Hf. The word line layer has terminal ends corresponding to control gate regions of individual memory cells. The control gate regions individually comprise portions of word lines in individual ones of the word line layers. The charge blocking regions of the individual memory cells extend vertically along the individual control gate regions. The charge storage material of the individual memory cells extends vertically along individual ones of the charge blocking regions. A string of channel material extends vertically through the word line layer, the majority of insulating layers, and the at least one insulating layer comprising the oxide including at least one of Mg and Hf. An insulating charge transport material is transverse to between the channel material and the charge storage material.

In some embodiments, an array of vertically extending memory cell strings includes a vertical stack of alternating layers of insulation and word lines. Most of the insulating layers include a first insulating composition. At least one of the insulating layers between the top and bottom layers of the stack comprises a second insulating composition different from the first insulating composition. The word line layer has terminal ends corresponding to control gate regions of individual memory cells. The control gate regions individually comprise portions of word lines in individual ones of the word line layers. The charge blocking regions of the individual memory cells extend vertically along the individual control gate regions. The charge storage material of the individual memory cells extends vertically along individual ones of the charge blocking regions. A string of channel material extends vertically through the word line layer, the insulating layer comprising the first insulating composition, and the at least one insulating layer comprising the second insulating composition. An insulating charge transport material is transverse to between the channel material and the charge storage material. The at least one insulating layer comprising the second insulating composition has an annular recess projecting radially outward relative to individual ones of the string of the channel material. A portion of the charge storage material is within the annular recess.

In compliance with the statute, the subject matter disclosed herein has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the claims are not limited to the specific features shown and described, since the means herein disclosed comprise example embodiments. Accordingly, the claims should be accorded the full scope literally worded, with appropriate interpretation based on the doctrine of equivalents.