阅读说明：本技术 具有对称路径的存储器字元线驱动器结构及其形成方法 (Memory word line driver structure with symmetrical path and forming method thereof ) 是由 不公告发明人 于 2018-09-13 设计创作，主要内容包括：本发明涉及半导体生产领域,公开了一种具有对称路径的存储器字元线驱动器结构,该驱动器结构通过设置两层或者两层以上的晶体管组合电路,并将一晶体管单独置于第一层,并使该晶体管的与两侧的字元线的连接距离为相等,而实现该晶体管与两侧字元线的连接距离相等,从而使得电流路径驱动器中的电流路径对称,有利于提高存储器的性能。(The invention relates to the field of semiconductor production, and discloses a memory word line driver structure with a symmetrical path.)

1. A memory wordline driver structure having a symmetric path, the driver structure comprising:

the upper surface of the first substrate comprises a peripheral area, a first transistor is arranged in the peripheral area and used for driving and connecting a buried word line positioned in an array area of the first substrate, and a first grid electrode, a first drain electrode and a first source electrode of the first transistor are arranged on the first substrate;

a first electrode isolation layer formed on the first substrate, the first electrode isolation layer covering the first transistor, the first gate, the first drain, and the first source being in the first electrode isolation layer;

the first longitudinal connecting piece is positioned in the first electrode isolation layer, and one end of the first longitudinal connecting piece is electrically connected with the embedded word line;

a first metal layer disposed on the first electrode isolation layer, the first metal layer connecting the first drain and electrically connected to the buried word line via the first vertical connecting member;

a first cover layer formed on the first electrode isolation layer, the first cover layer covering the first metal layer and the surface of the first electrode isolation layer;

a second substrate on the first capping layer, the second substrate including a stacked first active island block, a stacked second active island block, and a stacked isolation structure isolating the first active island block and the second active island block, a second transistor disposed on the first active island block, a third transistor disposed on the second active island block, the second transistor including a second gate, a second drain, and a second source disposed on the first active island block, the third transistor including a third gate, a third drain, and a third source disposed on the second active island block;

a second electrode isolation layer formed on the second substrate, the second gate, the second drain, the second source, the third gate, the third drain, and the third source being located in the second electrode isolation layer;

the second metal layer is arranged on the second electrode isolation layer and is connected with the second drain electrode and the third drain electrode;

the second covering layer is formed on the second electrode isolation layer and covers the surfaces of the second metal layer and the second electrode isolation layer;

wherein the second transistor and the third transistor are symmetrically arranged in a interlayer stacking manner according to a middle line of the first transistor and have a transistor type opposite to that of the first transistor; and the second metal layer connects the second drain electrode and the third drain electrode and is electrically connected to the first vertical connection via a second vertical connection penetrating at least the isolation structure and the second electrode isolation layer.

2. The driver structure as claimed in claim 1, wherein the first drain of the first transistor is connected to the at least two buried word lines on both sides of the first transistor at an equal distance.

3. The driver structure of claim 1, wherein the first metal layer further comprises first electrode contacts respectively connected to the first gate and the first source.

4. The driver structure of claim 1, wherein a region of the isolation structure projected on the first electrode isolation layer comprises the first gate and the first source.

5. The driver structure of claim 1, wherein the second metal layer further comprises second electrode contacts respectively connecting the second gate, the second source, the third gate, and the third source.

6. The driver structure of claim 1, further comprising an isolation layer formed on the second cladding layer.

7. The driver structure of claim 3, further comprising a third vertical connection connecting the first electrode contact of the first metal layer, the third vertical connection being between the first active island block and the second active island block, wherein the third vertical connection connecting the first gate is connected to a word line turn-off voltage.

8. The driver architecture of claim 7, wherein the third vertical connection connecting the first source is connected to a wordline driving voltage.

9. The driver structure of claim 5, further comprising a fourth vertical connection connecting the second electrode contact of the second metal layer, wherein the fourth vertical connection connecting the second gate is connected to a word line turn-on voltage and the fourth vertical connection connecting the third gate is connected to a word line turn-off voltage.

10. The driver structure of claim 8, wherein the second drain electrode and the third drain electrode are further electrically connected to the second vertical connection via the fourth vertical connection on the second metal layer, a longitudinal length of the fourth vertical connection being less than a longitudinal length of the second vertical connection.

11. A method of forming a memory wordline driver structure with symmetric paths, comprising:

providing a first substrate, wherein the upper surface of the first substrate comprises a peripheral area and an array area, a first transistor is arranged in the peripheral area, and a buried word line is arranged in the array area;

forming a first electrode isolation layer on the first substrate, and forming a first grid electrode, a first drain electrode and a first source electrode of the first transistor and a first longitudinal connecting piece with one end electrically connected with the embedded word line in the first electrode isolation layer;

forming a first metal layer on the first electrode isolation layer, wherein the first metal layer is connected with the first drain and is electrically connected to the embedded word line through the first vertical connecting piece, and the first metal layer further comprises a first electrode contact respectively connected with the first grid and the first source;

forming a first covering layer on the first electrode isolation layer, wherein the first covering layer covers the first metal layer and the surface of the first electrode isolation layer, and forming a second substrate on the first covering layer;

separating the second substrate into a first stacked active island block, a second stacked active island block, and a stacked isolation structure isolating the first active island block and the second active island block;

providing a second transistor on the first active island block and a third transistor on the second active island block;

forming a second electrode isolation layer on the second substrate, and forming a second gate, a second drain, and a second source of the second transistor and the third gate, the third drain, and the third source of the third transistor in the second electrode isolation layer;

forming a second metal layer on the second electrode isolation layer, wherein the second metal layer is connected with the second drain electrode and the third drain electrode, and the second metal layer further comprises second electrode contacts respectively connected with the second gate electrode, the second source electrode, the third gate electrode and the third source electrode;

forming a second covering layer on the second electrode isolation layer, wherein the second covering layer covers the second metal layer and the surface of the second electrode isolation layer;

a second longitudinal connection is provided at least through the isolation structure and the second electrode isolation layer, the second metal layer being electrically connected to the first longitudinal connection via the second longitudinal connection.

12. The forming method of claim 11, further comprising:

and forming an isolation layer on the second covering layer.

13. The forming method of claim 11, further comprising:

and arranging a third vertical connecting piece connected with the first electrode contact of the first metal layer, wherein the third vertical connecting piece is positioned between the first active island block and the second active island block, and the third vertical connecting piece connected with the first grid electrode is connected with a word line switching-off voltage.

14. The method of claim 11, wherein the third vertical connection connecting the first source is connected to a wordline driver voltage.

15. The forming method of claim 11, further comprising:

and a fourth longitudinal connecting piece connected with the second electrode contact of the second metal layer is arranged, wherein the fourth longitudinal connecting piece connected with the second grid electrode is connected to a word line switching-on voltage, and the fourth longitudinal connecting piece connected with the third grid electrode is connected to a word line switching-off voltage.

16. The method of forming as claimed in claim 15, wherein the second and third drain electrodes are also electrically connected to the second longitudinal connection via the fourth longitudinal connection having a longitudinal length less than a longitudinal length of the second longitudinal connection.

17. The method of claim 11, wherein the forming of the first gate, the first drain, and the first source of the first transistor in the first electrode isolation layer and the first vertical connection having one end electrically connected to the buried word line comprises:

and forming a first counter bore in the first electrode isolation layer by applying dry etching, and forming a first grid electrode, a first drain electrode, a first source electrode and a first longitudinal connecting piece, wherein one end of the first longitudinal connecting piece is electrically connected with the embedded word line, of the first transistor in the first counter bore.

18. The method of forming as claimed in claim 11, wherein the forming a first metal layer on the first electrode isolation layer comprises:

and forming a first metal original layer on the first electrode isolation layer, and converting the first metal original layer into a first metal layer by applying dry etching.

19. The method of forming as claimed in claim 11, wherein said forming a second substrate on said first cladding layer comprises:

an epitaxial growth technique is applied to form a second substrate, the material of which comprises monocrystalline silicon.

20. The method of forming as claimed in claim 11, wherein forming a second gate, a second drain, and a second source of the second transistor and the third gate, the third drain, and the third source of the third transistor in the second electrode isolation layer comprises:

and forming a second counter bore in the second electrode isolation layer by applying dry etching, and forming a second gate, a second drain and a second source of the second transistor and the third gate, the third drain and the third source of the third transistor in the second counter bore.

21. The method of forming as claimed in claim 11, wherein the forming of the second metal layer on the second electrode isolation layer comprises:

and forming a second metal original layer on the second electrode isolation layer, and converting the second metal original layer into a second metal layer by applying dry etching.

22. The method of forming as claimed in claim 11, wherein said disposing a second longitudinal connection through at least the isolation structure and the second electrode isolation layer comprises:

and forming a third counter bore penetrating at least the isolation structure and the second electrode isolation layer by using dry etching, and forming the second longitudinal connecting piece in the third counter bore.

Technical Field

The invention relates to the field of semiconductor production, in particular to a memory word line driver structure with a symmetrical path and a forming method thereof.

Background

The connection distances between the transistors in the driver of the existing memory and the word lines on two sides are inconsistent, so that the current path in the driver presents asymmetry, and the time difference occurs in the process of opening the word lines on two sides of the driver, thereby causing negative influence on the performance of the memory.

Disclosure of Invention

The invention aims to overcome the problem that the current path in a driver in a memory in the prior art is asymmetric, and provides a memory word line driver structure with a symmetric path.

In order to achieve the above object, an aspect of the embodiments of the present invention provides a memory wordline driver structure with a symmetric path, wherein the driver structure includes:

the upper surface of the first substrate comprises a peripheral area, a first transistor is arranged in the peripheral area and used for driving and connecting a buried word line positioned in an array area of the first substrate, and a first grid electrode, a first drain electrode and a first source electrode of the first transistor are arranged on the first substrate;

a first electrode isolation layer formed on the first substrate, the first electrode isolation layer covering the first transistor, the first gate, the first drain, and the first source being in the first electrode isolation layer;

the first longitudinal connecting piece is positioned in the first electrode isolation layer, and one end of the first longitudinal connecting piece is electrically connected with the embedded word line;

a first metal layer disposed on the first electrode isolation layer, the first metal layer connecting the first drain and electrically connected to the buried word line via the first vertical connecting member;

a first cover layer formed on the first electrode isolation layer, the first cover layer covering the first metal layer and the surface of the first electrode isolation layer;

a second substrate on the first capping layer, the second substrate including a stacked first active island block, a stacked second active island block, and a stacked isolation structure isolating the first active island block and the second active island block, a second transistor disposed on the first active island block, a third transistor disposed on the second active island block, the second transistor including a second gate, a second drain, and a second source disposed on the first active island block, the third transistor including a third gate, a third drain, and a third source disposed on the second active island block;

a second electrode isolation layer formed on the second substrate, the second gate, the second drain, the second source, the third gate, the third drain, and the third source being located in the second electrode isolation layer;

the second metal layer is arranged on the second electrode isolation layer and is connected with the second drain electrode and the third drain electrode;

the second covering layer is formed on the second electrode isolation layer and covers the surfaces of the second metal layer and the second electrode isolation layer;

wherein the second transistor and the third transistor are symmetrically arranged in a interlayer stacking manner according to a middle line of the first transistor and have a transistor type opposite to that of the first transistor; and the second metal layer connects the second drain electrode and the third drain electrode and is electrically connected to the first vertical connection via a second vertical connection penetrating at least the isolation structure and the second electrode isolation layer.

Preferably, the first drain of the first transistor is connected to the at least two buried word lines on both sides of the first transistor at the same distance.

Preferably, the first metal layer further includes first electrode contacts respectively connected to the first gate and the first source.

Preferably, a region of the isolation structure projected on the first electrode isolation layer includes the first gate electrode and the first source electrode.

Preferably, the second metal layer further includes second electrode contacts respectively connected to the second gate, the second source, the third gate and the third source.

Preferably, the driver structure further comprises an isolation layer formed on the second cover layer.

Preferably, the driver structure further comprises a third vertical connection connecting the first electrode contact of the first metal layer, the third vertical connection being located between the first active island block and the second active island block, wherein the third vertical connection connecting the first gate is connected to a word line turn-off voltage.

Preferably, the third vertical connection connecting the first source is connected to a word line driving voltage.

Preferably, the driver structure further includes a fourth vertical connector connected to the second electrode contact of the second metal layer, wherein the fourth vertical connector connected to the second gate is connected to a word line turn-on voltage, and the fourth vertical connector connected to the third gate is connected to a word line turn-off voltage.

Preferably, the second drain electrode and the third drain electrode are also electrically connected to the second vertical connection via the fourth vertical connection located on the second metal layer, and a longitudinal length of the fourth vertical connection is smaller than a longitudinal length of the second vertical connection.

In another aspect, the present invention provides a method for forming a memory wordline driver structure with a symmetric path, including:

providing a first substrate, wherein the upper surface of the first substrate comprises a peripheral area and an array area, a first transistor is arranged in the peripheral area, and a buried word line is arranged in the array area;

forming a first electrode isolation layer on the first substrate, and forming a first grid electrode, a first drain electrode and a first source electrode of the first transistor and a first longitudinal connecting piece with one end electrically connected with the embedded word line in the first electrode isolation layer;

forming a first metal layer on the first electrode isolation layer, wherein the first metal layer is connected with the first drain and is electrically connected to the embedded word line through the first vertical connecting piece, and the first metal layer further comprises a first electrode contact respectively connected with the first grid and the first source;

forming a first covering layer on the first electrode isolation layer, wherein the first covering layer covers the first metal layer and the surface of the first electrode isolation layer, and forming a second substrate on the first covering layer;

separating the second substrate into a first stacked active island block, a second stacked active island block, and a stacked isolation structure isolating the first active island block and the second active island block;

providing a second transistor on the first active island block and a third transistor on the second active island block;

forming a second electrode isolation layer on the second substrate, and forming a second gate, a second drain, and a second source of the second transistor and the third gate, the third drain, and the third source of the third transistor in the second electrode isolation layer;

forming a second metal layer on the second electrode isolation layer, wherein the second metal layer is connected with the second drain electrode and the third drain electrode, and the second metal layer further comprises second electrode contacts respectively connected with the second gate electrode, the second source electrode, the third gate electrode and the third source electrode;

forming a second covering layer on the second electrode isolation layer, wherein the second covering layer covers the second metal layer and the surface of the second electrode isolation layer;

a second longitudinal connection is provided at least through the isolation structure and the second electrode isolation layer, the second metal layer being electrically connected to the first longitudinal connection via the second longitudinal connection.

Preferably, the forming method further includes:

and forming an isolation layer on the second covering layer.

Preferably, the forming method further includes:

and arranging a third vertical connecting piece connected with the first electrode contact of the first metal layer, wherein the third vertical connecting piece is positioned between the first active island block and the second active island block, and the third vertical connecting piece connected with the first grid electrode is connected with a word line switching-off voltage.

Preferably, the third vertical connection connecting the first source electrodes is connected to a word line driving voltage.

Preferably, the forming method further includes:

and a fourth longitudinal connecting piece connected with the second electrode contact of the second metal layer is arranged, wherein the fourth longitudinal connecting piece connected with the second grid electrode is connected to a word line switching-on voltage, and the fourth longitudinal connecting piece connected with the third grid electrode is connected to a word line switching-off voltage.

Preferably, the second drain electrode and the third drain electrode are also electrically connected to the second longitudinal connector via the fourth longitudinal connector, the longitudinal length of the fourth longitudinal connector being smaller than the longitudinal length of the second longitudinal connector.

Preferably, the forming of the first gate, the first drain, and the first source of the first transistor in the first electrode isolation layer and the first vertical connection member having one end electrically connected to the buried word line includes:

and forming a first counter bore in the first electrode isolation layer by applying dry etching, and forming a first grid electrode, a first drain electrode, a first source electrode and a first longitudinal connecting piece, wherein one end of the first longitudinal connecting piece is electrically connected with the embedded word line, of the first transistor in the first counter bore.

Preferably, the forming of the first metal layer on the first electrode isolation layer includes:

and forming a first metal original layer on the first electrode isolation layer, and converting the first metal original layer into a first metal layer by applying dry etching.

Preferably, the forming of the second substrate on the first cover layer includes:

an epitaxial growth technique is applied to form a second substrate, the material of which comprises monocrystalline silicon.

Preferably, forming a second gate, a second drain, and a second source of the second transistor and the third gate, the third drain, and the third source of the third transistor in the second electrode isolation layer includes:

and forming a second counter bore in the second electrode isolation layer by applying dry etching, and forming a second gate, a second drain and a second source of the second transistor and the third gate, the third drain and the third source of the third transistor in the second counter bore.

Preferably, the forming of the second metal layer on the second electrode isolation layer includes:

and forming a second metal original layer on the second electrode isolation layer, and converting the second metal original layer into a second metal layer by applying dry etching.

Preferably, the disposing a second longitudinal connection at least through the isolation structure and the second electrode isolation layer comprises:

and forming a third counter bore penetrating at least the isolation structure and the second electrode isolation layer by using dry etching, and forming the second longitudinal connecting piece in the third counter bore.

Through the technical scheme, the memory word line driver structure with the symmetrical paths is provided with two or more layers of transistor combination circuits, the PMOS transistor is independently arranged on the first layer, the NMOS transistor is arranged on the second layer, so that the connection distances between the PMOS transistor and the word lines on two sides are equal, the current paths in the current path driver are symmetrical, and the performance of the memory is improved.

Drawings

FIG. 1 is a cross-sectional view of a memory wordline driver structure with a symmetric path according to an embodiment of the invention;

FIG. 2 is a circuit diagram of a memory wordline driver architecture with symmetric paths according to an embodiment of the present invention;

FIG. 3 is an equivalent circuit diagram of a memory wordline driver structure with a symmetric path according to an embodiment of the present invention;

FIG. 4 is a second equivalent circuit diagram of a memory wordline driver structure with a symmetric path according to an embodiment of the invention;

fig. 5A to 5J are cross-sectional views of driver structures corresponding to steps of a method for forming a memory wordline driver structure with a symmetric path according to an embodiment of the invention.

Description of the reference numerals

1 first substrate 2 first transistor

3 buried word line 4 first electrode isolation layer

5 first longitudinal connection 6 first metal layer

7 first cover layer 8 second substrate

9 second transistor 10 third transistor

11 second electrode isolation layer 12 second metal layer

13 second cover layer 14 second longitudinal connecting element

15 third longitudinal connecting piece of isolating layer 16A-B

17A-E fourth longitudinal connection 21 first grid

22 first drain electrode 23 first source electrode

61 first electrode contact 81 first active island block

82 second active island 83 isolation structure

91 second gate 92 second drain

93 a second source 101 and a third gate

102 third drain 103 third source

121 second electrode contact

Detailed Description

The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation.

FIG. 1 illustrates a cross-sectional view of a memory wordline driver structure with a symmetric path according to an embodiment of the invention. An aspect of an embodiment of the present invention provides a memory wordline driver structure with a symmetric path, which may include:

the first substrate 1, the upper surface of the first substrate 1 includes a peripheral region and an array region, wherein the peripheral region may be disposed with a first transistor 2 for driving and connecting with a buried word line 3 located in the array region, and a first gate 21, a first drain 22 and a first source 23 of the first transistor 2 are disposed on the first substrate 1 with the first gate 21, the first drain 22 and the first source 23;

a first electrode isolation layer 4 formed on the first substrate 1, the first electrode isolation layer 4 may cover the first transistor 2, and the first gate electrode 21, the first drain electrode 22, and the first source electrode 23 of the first transistor 2 may be located in the first electrode isolation layer 4;

a first vertical connecting member 5 located in the first electrode isolation layer 4, wherein one end of the first vertical connecting member 5 can be electrically connected to the embedded word line 3;

a first metal layer 6 disposed on the first electrode isolation layer 4, wherein the first metal layer 6 can be connected to the first drain 22 and electrically connected to the embedded word line 3 through another end of the first vertical connection member 5;

a first capping layer 7 formed on the first electrode isolation layer 4, the first capping layer 7 may cover the first metal layer 6 and the surface of the first electrode isolation layer 4;

a second substrate 8 on the first capping layer 7, the second substrate 8 may include a stacked first active island block 81, a stacked second active island block 82, and a stacked isolation structure 83 isolating the first active island block 81 and the second active island block 82, a second transistor 9 may be disposed on the first active island block 81, a third transistor 10 may be disposed on the second active island block 82, the second transistor 9 may include a second gate 91, a second drain 92, and a second source 93 disposed on the first active island block 81, and the third transistor 10 may include a third gate 101, a third drain 102, and a third source 103 disposed on the second active island block 82;

a second electrode isolation layer 11 formed on the second substrate 8, and the second gate electrode 91, the second drain electrode 92, the second source electrode 93, the third gate electrode 101, the third drain electrode 102, and the third source electrode 103 may be located in the second electrode isolation layer 11;

a second metal layer 12 disposed on the second electrode isolation layer 11, the second metal layer 12 may connect the second drain electrode 92 and the third drain electrode 102;

a second capping layer 13 formed on the second electrode isolation layer 11, the second capping layer 13 may cover the surfaces of the second metal layer 12 and the second electrode isolation layer 11;

wherein the second transistor 9 and the third transistor 10 of the memory wordline driver structure with symmetrical paths can be arranged symmetrically with respect to the spacers of a middle line of the first transistor 2 and have a transistor type opposite to that of the first transistor 2; the second metal layer 12 may connect the second drain 92 and the third drain 102 and is electrically connected to the first vertical connection 5 through the second vertical connection 14 penetrating at least the isolation structure 83 and the second electrode isolation layer 11, so as to connect the second transistor 9 and the third transistor 10 to the buried word line 3.

Specifically, the first transistor 2 may be a PMOS transistor, and the second transistor 9 and the third transistor 10 may be NMOS transistors. In an embodiment of the present invention, the first drain 22 of the first transistor 2(PMOS transistor) may have an equal connection distance with the embedded word lines 3 on both sides, so that the current paths of the first transistor 2 and the embedded word lines 3 on both sides have high symmetry, thereby avoiding a time difference occurring in the process of opening the word lines on both sides of the memory word line driver structure with the symmetric paths, and facilitating to improve the performance of the memory.

The first metal layer 6 may further include first electrode contacts 61 connected to the first gate electrode 21 and the first source electrode 23, respectively, to form corresponding current connection lines.

As shown in fig. 1, a region of the isolation structure 83 projected on the first electrode isolation layer 4 may include the first gate electrode 21 and the first source electrode 23.

The second metal layer 12 may further include second electrode contacts 121 respectively connected to the second gate 91, the second source 93, the third gate 101 and the third source 103 to form respective current connection lines.

As shown in fig. 1, the memory wordline driver structure with a symmetrical path may further include an isolation layer 15 formed on the second capping layer 13, where the isolation layer 15 is used to provide necessary insulation and protection.

FIG. 2 is a circuit diagram of a memory wordline driver architecture with symmetric paths according to an embodiment of the invention. As shown in fig. 1 and 2, the memory wordline driver structure with a symmetrical path may further include third vertical connectors 16A and 16B connected to the first electrode contact 61 of the first metal layer 6. In particular, the third longitudinal connection 16 is located between the first active island 81 and the second active island 82. Wherein the third vertical connection 16A connecting the first gate 21 is connected to the word line open gate voltage MWLb; the third vertical connection 16B connecting the first source 23 is connected to the word line driving voltage X₀₁₂。

The memory wordline driver structure with a symmetrical path further includes fourth vertical connections 17A-17E connecting the second electrode contacts 121 of the second metal layer 12. Wherein the fourth vertical connection 17B connecting the second gate 91 is connected to the word line switching-off voltage MWLb; the fourth vertical connection 17D connecting the third gate 101 is connected to the word line gate voltage

The second metal layer 12 of the memory wordline driver structure with a symmetrical path connects the second drain 92 and the third drain 102 and is electrically connected to the first vertical connection 5 through the second vertical connection 14. Specifically, as shown in the current path represented by the dashed line in fig. 2, the second drain 92 and the third drain 102 are electrically connected to the second vertical connection 14 through the fourth vertical connection 17C on the second metal layer 12, and further electrically connected to the buried word line 3 through the first metal layer 6 and the second vertical connection 5. Through such a connection manner, the first drain 21 of the first transistor 2, the first drain 91 of the second transistor 9, and the first drain 101 of the third transistor 10 are connected to the embedded word line 3. The longitudinal length of the fourth longitudinal connector 17A-17E is less than the longitudinal length of the second longitudinal connector 14.

The memory word line driver structure with the symmetrical path provided by the embodiment of the invention includes an upper layer and a lower layer, and those skilled in the art will understand that the structure of the upper layer and the lower layer is only a preferred scheme, and can be designed into a structure with three or more layers.

Fig. 3 shows one equivalent circuit diagram of a memory wordline driver structure with symmetric paths according to an embodiment of the invention, and fig. 4 shows the second equivalent circuit diagram of a memory wordline driver structure with symmetric paths according to an embodiment of the invention. As shown in fig. 3, the upper and lower transistor structures (Layer1, Layer2) of the memory wordline driver structure with symmetric paths form wordline driving circuits in the driver. Fig. 5A to 5J are cross-sectional views of driver structures corresponding to steps of a method for forming a memory wordline driver structure with a symmetric path according to an embodiment of the invention. The correspondence relationship between the equivalent circuit diagram shown in fig. 2 and the driver structure shown in fig. 5A to 5J is briefly described below. Referring to fig. 2 and fig. 5B, the first gate 21 in fig. 5B corresponds to the position C of the first transistor 2 in fig. 2, the first drain 22 in fig. 5B corresponds to the position a of the first transistor 2 in fig. 2, and the first source 23 in fig. 5B corresponds to the position B of the first transistor 2 in fig. 2; referring to fig. 2 and fig. 5H, the second gate 91 in fig. 5H corresponds to the position C of the second transistor 9 in fig. 2, the second drain 92 in fig. 5H corresponds to the position a of the second transistor 9 in fig. 2, and the second source 93 in fig. 5H corresponds to the position D of the second transistor 9 in fig. 2; referring to fig. 2 and fig. 5H, the third gate 101 in fig. 5H corresponds to the middle of the third transistor 10 in fig. 2, the third drain 102 in fig. 5H corresponds to the position a of the third transistor 10 in fig. 2, and the third source 103 in fig. 5H corresponds to the position E of the third transistor 10 in fig. 2.

The circuit connections of the memory wordline driver structure with symmetric paths are further described below in conjunction with the equivalent circuit diagram shown in fig. 4. As shown in fig. 4, the memory with symmetrical pathsThe first drain 22 of the first transistor 2 under the memory word line driver structure passes through the point a on the left side in fig. 3 to connect and drive the memory array to which the buried word lines 3 on both sides are connected. The first source 23 of the first transistor 2 is connected to the driving voltage source X of the buried word line 3 through the point B on the left side of fig. 3₀₁₂And the word line open-gate voltage MWLb is connected to the first gate 21 of the first transistor 2) to control the driving voltage source X₀₁₂The conduction of the buried word line 3 is controlled by passing or not passing the word line.

As shown in FIG. 4, the third transistor 10 on the top layer of the memory wordline driver structure with symmetric paths is connected to a wordline off switchSpecifically, the word line gate switchA third source electrode 103 of the third transistor 10 controlled by the third gate 101 of the third transistor 10 and a negative potential V_NWLConnected (by a fourth longitudinal connecting member 17E shown in FIG. 2) to make V_NWLThe potential (negative potential) is outputted to the buried word line 3 through the point E, the third drain 102 of the third transistor 10, the point a on the right side in fig. 4, and the buried word line 3 is turned off.

As shown in fig. 4, the second transistor 9 on the upper layer of the memory word line driver structure with symmetric paths uses the word line open-gate voltage MWLb as the gate control, the second source 93 of the second transistor 9 and the negative potential V_NWLConnected (by a fourth longitudinal connecting member 17A shown in FIG. 2) to make V_NWLThe potential (negative potential) is outputted to the buried word line 3 through the point D, the third drain 92 of the second transistor 9, the point a on the left side in fig. 4, and the buried word line 3 is turned off.

Fig. 5A to 5J are cross-sectional views of driver structures corresponding to steps of a method for forming a memory wordline driver structure with a symmetric path according to an embodiment of the invention. Another aspect of the embodiments of the invention further provides a method for forming a memory wordline driver structure with a symmetric path, as shown in fig. 5A to 5J, the method may include:

as shown in fig. 5A, a first substrate 1 is provided, an upper surface of the first substrate 1 includes a peripheral region and an array region, the peripheral region is provided with a first transistor 2, and the array region is provided with a buried word line 3;

as shown in fig. 5B, a first electrode isolation layer 4 is formed on the first substrate 1, and a first gate 21, a first drain 22 and a first source 23 of the first transistor 2 and a first vertical connection 5 having one end electrically connected to the buried word line 3 are formed in the first electrode isolation layer 4;

as shown in fig. 5C, a first metal layer 6 is formed on the first electrode isolation layer 4, the first metal layer 6 is connected to the first drain 22 and electrically connected to the buried word line 3 through the first vertical connecting member 5, the first metal layer 6 further includes a first electrode contact 61 respectively connected to the first gate 21 and the first source 23;

as shown in fig. 5D, a first capping layer 7 is formed on the first electrode isolation layer 4, the first capping layer 7 covers the first metal layer 6 and the surface of the first electrode isolation layer 4, and a second substrate 8 is formed on the first capping layer 7;

as shown in fig. 5E, the second substrate 8 is divided into a stacked first active island 81, a stacked second active island 82, and a stacked isolation structure 83 isolating the first active island 81 and the second active island 82;

as shown in fig. 5F, the second transistor 9 is provided on the first active island block 81, and the third transistor 10 is provided on the second active island block 82;

as shown in fig. 5G and 5H, a second electrode isolation layer 11 is formed on the second substrate 8, and the second gate 91, the second drain 92, and the second source 93 of the second transistor 9 and the third gate 101, the third drain 102, and the third source 103 of the third transistor 10 are formed in the second electrode isolation layer 11;

as shown in fig. 5I, a second metal layer 12 is formed on the second electrode isolation layer 11, the second metal layer 12 is connected to the second drain 92 and the third drain 102, and the second metal layer 12 further includes a second electrode contact 121 respectively connected to the second gate 91, the second source 93, the third gate 101 and the third source 103;

as shown in fig. 5J, a second capping layer 13 is formed on the second electrode isolation layer 11, the second capping layer 13 covering the second metal layer 12 and the surface of the second electrode isolation layer 11;

as shown in fig. 5J, a second longitudinal connecting member 14 is provided which penetrates at least the isolation structure 83 and the second electrode isolation layer 11, and the second metal layer 12 is electrically connected to the first longitudinal connecting member 5 via the second longitudinal connecting member 14;

in an embodiment of the present invention, the method for forming a memory wordline driver structure with a symmetric path may further include:

on the second cover layer 13, an isolation layer 15 is formed and a third vertical connection 16 for connecting the first metal layer 6 and the second metal layer 12 and a fourth vertical connection 17 electrically connected to the second gate 91, the second source 93, the third gate 101 and the third source 103, respectively, are provided.

In one embodiment of the present invention, the forming of the first gate 21, the first drain 22 and the first source 23 of the first transistor 2 in the first electrode isolation layer 4 and the first vertical connection 5 having one end electrically connected to the buried word line 3 may specifically include:

a first counterbore is formed in the first electrode isolation layer 4 by dry etching, and a first gate 21, a first drain 22 and a first source 23 of the first transistor 2 and a first vertical connection 5 having one end electrically connected to the buried word line 3 are formed in the first counterbore.

In one embodiment of the present invention, forming the first metal layer 6 on the first electrode isolation layer 4 may specifically include:

a first metal original layer is formed on the first electrode isolation layer 4, and the first metal original layer is converted into a first metal layer 6 by dry etching.

In one embodiment of the present invention, and forming the second substrate 8 on the first cover layer 7 may specifically include:

epitaxial growth is applied to form the second substrate 8, the material of the second substrate 8 being monocrystalline silicon.

In one embodiment of the present invention, forming the second gate 91, the second drain 92, and the second source 93 of the second transistor 9 and the third gate 101, the third drain 102, and the third source 103 of the third transistor 10 in the second electrode isolation layer 11 may specifically include:

dry etching is applied to form second counter bores in the second electrode isolation layer 11, in which the second gate 91, the second drain 92 and the second source 93 of the second transistor 9 and the third gate 101, the third drain 102 and the third source 103 of the third transistor 10 are formed.

In one embodiment of the present invention, forming the second metal layer 12 on the second electrode isolation layer 11 may specifically include:

and forming a second metal original layer on the second electrode isolation layer 11, and converting the second metal original layer into a second metal layer 12 by using dry etching.

In one embodiment of the present invention, providing the second longitudinal connecting member 14 penetrating at least the isolation structure 83 and the second electrode isolation layer 11 may specifically include:

a third counterbore is formed through at least the isolation structure 83 and the second electrode isolation layer 11 using dry etching, and a second longitudinal connection 14 is formed in the third counterbore.

The preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited thereto. Within the scope of the technical idea of the invention, numerous simple modifications can be made to the technical solution of the invention, including combinations of the individual specific technical features in any suitable way. The invention is not described in detail in order to avoid unnecessary repetition. Such simple modifications and combinations should be considered within the scope of the present disclosure as well.