阅读说明：本技术 包括栅极间隔物结构的集成电路器件 (Integrated circuit device including gate spacer structure ) 是由 尹灿植 金桐晤 朴济民 李基硕 于 2019-07-17 设计创作，主要内容包括：一种集成电路器件包括在基层上的栅极堆叠结构以及在栅极堆叠结构的相反侧壁上且在基层上的栅极间隔物结构,栅极堆叠结构具有栅极绝缘层和在栅极绝缘层上的栅极结构,栅极绝缘层具有在基层上并具有第一相对电容率的第一电介质层,栅极间隔物结构包括位于基层上的掩埋在位于栅极间隔物结构的下部处的栅极绝缘层的凹陷孔中的掩埋电介质层,掩埋电介质层包括与第一电介质层相同的材料。(An integrated circuit device includes a gate stack structure on a base layer and a gate spacer structure on the base layer on opposite sidewalls of the gate stack structure, the gate stack structure having a gate insulating layer and a gate structure on the gate insulating layer, the gate insulating layer having a first dielectric layer on the base layer and having a first relative permittivity, the gate spacer structure including a buried dielectric layer on the base layer buried in a recess hole of the gate insulating layer at a lower portion of the gate spacer structure, the buried dielectric layer including a same material as the first dielectric layer.)

1. An integrated circuit device, comprising:

a gate stack structure on a base layer, the gate stack structure comprising:

a gate insulating layer including a first dielectric layer on the base layer and having a first relative permittivity, an

A gate structure on the gate insulating layer; and

a gate spacer structure on opposing sidewalls of the gate stack structure and on the base layer, the gate spacer structure comprising a buried dielectric layer on the base layer buried in a recessed hole of the gate insulation layer at a lower portion of the gate spacer structure, the buried dielectric layer comprising the same material as the first dielectric layer.

2. The integrated circuit device of claim 1, wherein:

the base layer includes at least one of a semiconductor substrate and a semiconductor layer, and a memory cell region and a peripheral circuit region on the at least one of the semiconductor substrate and the semiconductor layer, and

the gate insulation layer, the gate structure, and the gate spacer structure are in the peripheral circuit region.

3. The integrated circuit device of claim 1, wherein the gate insulating layer further comprises a second dielectric layer on the first dielectric layer, the second dielectric layer having a second relative permittivity greater than the first relative permittivity.

4. The integrated circuit device of claim 3, wherein the first dielectric layer has a greater thickness than the second dielectric layer.

5. The integrated circuit device of claim 1, wherein each of the first dielectric layer and the buried dielectric layer comprises a silicon oxide layer.

6. The integrated circuit device of claim 1, wherein the gate structure has a metal gate structure comprising a metal layer.

7. The integrated circuit device of claim 1, wherein the gate structure comprises a work function control layer, a first gate layer, and a second gate layer sequentially on the gate insulating layer.

8. The integrated circuit device of claim 1, wherein the gate spacer structure comprises:

a first spacer on opposite sidewalls of the gate structure, the first spacer comprising a third dielectric layer and having a linear stripe shape, the third dielectric layer having a third relative permittivity greater than the first relative permittivity;

second spacers on sidewalls of the first spacers, on sidewalls of the buried dielectric layer, and on the base layer, the second spacers being L-shaped integrally with the buried dielectric layer and comprising the same material as the buried dielectric layer;

a third spacer on a sidewall and an upper portion of the second spacer, the third spacer comprising the same material as the first spacer and having an L-shape; and

a fourth spacer on sidewalls and an upper portion of the third spacer, the fourth spacer comprising a same material as the second spacer.

9. The integrated circuit device of claim 8, wherein each of the first and third spacers comprises a layer of silicon nitride, and each of the buried dielectric layer, the second and fourth spacers comprises a layer of silicon oxide.

10. The integrated circuit device of claim 1, wherein the gate spacer structure comprises:

a first spacer on two opposite walls of the gate structure, including a third dielectric layer having a third relative permittivity greater than the first relative permittivity, and having a linear stripe shape;

a second spacer on sidewalls of the first spacer and on sidewalls of the buried dielectric layer, integrally in a linear stripe shape with the buried dielectric layer, and comprising the same material as the buried dielectric layer;

a third spacer on a sidewall of the second spacer and on the base layer, comprising the same material as the first spacer, and having an L-shape; and

a fourth spacer on a sidewall and an upper portion of the third spacer and comprising the same material as the second spacer.

11. The integrated circuit device of claim 10, wherein each of the first and third spacers comprises a layer of silicon nitride, and each of the buried dielectric layer, the second and fourth spacers comprises a layer of silicon oxide.

12. The integrated circuit device of claim 1, wherein the gate spacer structure comprises:

a first spacer on opposite sidewalls of the gate structure, including a third dielectric layer having a third relative permittivity greater than the first relative permittivity, and having a linear stripe shape;

second spacers on sidewalls of the first spacers, on sidewalls of the buried dielectric layer, and on the base layer, comprising the same material as the first spacers and having an L-shape; and

a third spacer on sidewalls and an upper portion of the second spacer and comprising the same material as the buried dielectric layer.

13. The integrated circuit device of claim 12, wherein each of the first and second spacers comprises a silicon nitride layer, and each of the buried dielectric layer and the third spacer comprises a silicon oxide layer.

14. An integrated circuit device, comprising:

a gate stack structure comprising:

a gate insulating layer having a first dielectric layer on the base layer and having a first relative permittivity and a second dielectric layer having a second relative permittivity greater than the first relative permittivity, an

A gate structure on the gate insulating layer, the gate structure including a metal layer; and

a gate spacer structure on opposing sidewalls of the gate stack structure and on the base layer, the gate spacer structure comprising:

a first spacer on opposite sidewalls of the gate structure, including a third dielectric layer having a third relative permittivity greater than the first relative permittivity, and having a linear stripe shape,

a second spacer comprising a buried dielectric layer buried in a recessed hole in the first dielectric layer, the second spacer comprising the same material as the first dielectric layer at a lower portion of the first spacer, on sidewalls of the first spacer, and on sidewalls of the buried dielectric layer, being integrally disposed with the buried dielectric layer, and comprising the same material as the buried dielectric layer,

a third spacer on sidewalls of the second spacer, comprising the same material as the first spacer, and having an L-shape, an

A fourth spacer on sidewalls and an upper portion of the third spacer and comprising the same material as the second spacer.

15. The integrated circuit device of claim 14, wherein the second spacer is connected to the buried dielectric layer and on the base layer such that the second spacer has an L-shape and the third spacer is on the second spacer on the base layer.

16. The integrated circuit device of claim 14, wherein the second spacers are linear stripes on sidewalls of the first spacers and on sidewalls of the buried dielectric layer, and the third spacers are on sidewalls of the second spacers and on the base layer.

17. The integrated circuit device of claim 14, wherein each of the first spacer and the third spacer comprises a silicon nitride layer, and each of the first dielectric layer, the buried dielectric layer, the second spacer, and the fourth spacer comprises a silicon oxide layer.

18. The integrated circuit device of claim 14, wherein a width of the fourth spacer is greater than a width of the first spacer and a width of the third spacer.

19. An integrated circuit device, comprising:

a gate stack structure including a gate insulation layer and a gate structure on the gate insulation layer, the gate insulation layer including a first dielectric layer on a base layer and having a first relative permittivity and a second dielectric layer having a second relative permittivity greater than the first relative permittivity, the gate structure including a metal layer; and

a gate spacer structure on opposing sidewalls of the gate stack structure and on the base layer, the gate spacer structure comprising:

a first spacer on opposite sidewalls of the gate structure, including a third dielectric layer having a third relative permittivity greater than the first relative permittivity, and having a linear stripe shape,

a buried dielectric layer buried in a recess hole in the first dielectric layer at a lower portion of the first spacer and having the same material as the first dielectric layer,

a second spacer on sidewalls of the first spacer and the buried dielectric layer and the base layer and comprising the same material as the first spacer, an

A third spacer on sidewalls and an upper portion of the second spacer and comprising the same material as the buried dielectric layer.

20. The integrated circuit device of claim 19, wherein:

each of the first and second spacers comprises a silicon nitride layer,

each of the first dielectric layer, the buried dielectric layer, and the third spacer includes a silicon oxide layer, an

The third spacer has a width greater than a width of the first spacer and a width of the second spacer.

Technical Field

Background

In an integrated circuit device, a gate spacer structure may be formed on both sidewalls of the gate stack structure. Due to the high integration of integrated circuit devices, the reliability of the gate insulation layer of an integrated circuit device may be reduced due to the components of the gate spacer structure. In addition, integrated circuit devices may have increased parasitic capacitance due to the components of the gate spacer structure.

Disclosure of Invention

According to an aspect, there is provided an integrated circuit device comprising: a gate stack structure including a gate insulation layer and a gate structure on the gate insulation layer, the gate insulation layer including a first dielectric layer on the base layer and having a first relative permittivity; and a gate spacer structure on both sidewalls of the gate stack structure and on the base layer. The gate spacer structure includes a buried dielectric layer buried in a recess hole in a gate insulating layer located at a lower portion of the gate spacer structure on the base layer, the buried dielectric layer including the same material as the first dielectric layer.

According to another aspect, there is provided an integrated circuit device comprising: a gate stack structure including a gate insulating layer and a gate structure on the gate insulating layer, the gate insulating layer including a first dielectric layer on the base layer and having a first relative permittivity and a second dielectric layer having a second relative permittivity greater than the first relative permittivity, and the gate structure including a metal layer; and a gate spacer structure on both sidewalls of the gate stack structure and on the base layer. The gate spacer structure includes: a first spacer on both sidewalls of the gate structure, including a third dielectric layer having a third relative permittivity greater than the first relative permittivity, and having an I-shape; a second spacer including a buried dielectric layer buried in the recess hole in the first dielectric layer, the second spacer including the same material as the first dielectric layer at a lower portion of the first spacer, on sidewalls of the first spacer and sidewalls of the buried dielectric layer, integrally provided with the buried dielectric layer, and including the same material as the buried dielectric layer; a third spacer on a sidewall of the second spacer, including the same material as the first spacer, and having an L-shape; and a fourth spacer on sidewalls and an upper portion of the third spacer and including the same material as the second spacer.

According to another aspect, there is provided an integrated circuit device comprising: a gate stack structure including a gate insulating layer and a gate structure disposed on the gate insulating layer, the gate insulating layer including a first dielectric layer on the base layer and having a first relative permittivity and a second dielectric layer having a second relative permittivity greater than the first relative permittivity, and the gate structure including a metal layer; and a gate spacer structure on both sidewalls of the gate stack structure and on the base layer. The gate spacer structure includes: a first spacer on both sidewalls of the gate structure, including a third dielectric layer having a third relative permittivity greater than the first relative permittivity, and having an I-shape; a buried dielectric layer buried in the recess hole in the first dielectric layer at a lower portion of the first spacer and having the same material as the first dielectric layer; a second spacer on the sidewalls of the first spacer and the buried dielectric layer and the base layer and comprising the same material as the first spacer; and a third spacer on sidewalls and an upper portion of the second spacer and comprising the same material as the buried dielectric layer.

Drawings

Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the attached drawings, wherein:

FIG. 1 illustrates a top view of an integrated circuit device according to an embodiment;

FIG. 2 shows a cross-sectional view taken along line II-II' of FIG. 1;

FIG. 3 shows an enlarged view of FIG. 2;

FIG. 4 illustrates a cross-sectional view of an integrated circuit device according to an embodiment;

FIG. 5 shows an enlarged view of FIG. 4;

FIG. 6 illustrates a cross-sectional view of an integrated circuit device according to an embodiment;

FIG. 7 shows an enlarged view of FIG. 6;

FIGS. 8A to 8D show cross-sectional views of stages in a method of manufacturing an integrated circuit device according to an embodiment;

FIGS. 9A and 9B show cross-sectional views of stages in a method of fabricating an integrated circuit device, according to an embodiment;

FIGS. 10A and 10B show cross-sectional views of stages in a method of fabricating an integrated circuit device, according to an embodiment;

FIG. 11 illustrates a top view of a schematic structure of a memory device according to an embodiment;

FIG. 12 shows a block diagram of an exemplary structure of a memory device according to an embodiment;

FIG. 13 illustrates a top view of an exemplary structure of a memory device according to an embodiment;

fig. 14 shows a schematic layout of main components of the memory cell array region of fig. 13; and

fig. 15A to 15Q show cross-sectional views of stages in a method of manufacturing a memory device according to an embodiment.

Embodiments relate to integrated circuit devices, and more particularly, to integrated circuit devices including gate spacer structures.