阅读说明：本技术 半导体器件及其制备方法
(Semiconductor device and method for manufacturing the same
) 是由 不公告发明人 于 2018-09-13 设计创作，主要内容包括：本发明提供了一种半导体器件及其制备方法,通过将多晶硅栅极堆叠于金属栅极上方来形成复合栅极,可以改善复合栅极与源极、漏极重叠区域的电场分布,由此,能够兼容金属栅极和多晶硅栅极的优点,在保证栅极具有低电阻值的情况下,还能够降低栅极与源极、漏极重叠区域的漏电流,以提高器件效能及可靠度。进一步地,使得所述导线下方的第一导电接触结构为主要由金属层和多晶硅层堆叠的复合结构,能够降低接触电阻,提高器件性能。(The invention provides a semiconductor device and a preparation method thereof, wherein a composite grid is formed by stacking a polysilicon grid above a metal grid, so that the electric field distribution of the composite grid, a source electrode and a drain electrode overlapping region can be improved, the advantages of the metal grid and the polysilicon grid can be compatible, and the leakage current of the grid, the source electrode and the drain electrode overlapping region can be reduced under the condition of ensuring that the grid has a low resistance value, so that the efficiency and the reliability of the device are improved. Furthermore, the first conductive contact structure below the lead is a composite structure mainly formed by stacking a metal layer and a polycrystalline silicon layer, so that the contact resistance can be reduced, and the performance of the device can be improved.)
1. A method of manufacturing a semiconductor device, comprising:
providing a semiconductor substrate with a gate trench;
filling a metal gate in the gate trench, wherein the height of the metal gate is smaller than the depth of the gate trench; and the number of the first and second groups,
and filling a polysilicon gate in the gate trench, wherein the polysilicon gate is stacked on the metal gate to form a composite gate.
2. The method of fabricating a semiconductor device according to claim 1, wherein a top surface of the polysilicon gate is lower than a top surface of the semiconductor substrate on the sidewalls of the gate trench, the method further comprising: and filling a grid electrode isolation layer in the grid electrode groove, wherein the grid electrode isolation layer fills the grid electrode groove so as to bury the metal grid electrode and the polysilicon grid electrode.
3. The method of claim 1, wherein a gate dielectric layer is formed on sidewalls and bottom walls of the gate trench prior to filling the metal gate in the gate trench.
4. The method of claim 3, wherein a metal barrier layer is formed on the surface of the gate dielectric layer after the gate dielectric layer is formed and before the metal gate is filled, and wherein after the metal gate is filled, the metal barrier layer surrounds the bottom wall and the side wall of the metal gate and exposes the surface of the gate dielectric layer above the metal gate, such that the side wall of the polysilicon gate is in direct contact with the surface of the gate dielectric layer.
5. The method for manufacturing a semiconductor device according to any one of claims 1 to 4, further comprising:
forming a first conductive contact structure on the semiconductor substrate on one side of the grid groove;
forming a conductive line on the first conductive contact structure;
forming an interlayer dielectric layer on the grid groove and the semiconductor substrate, wherein the interlayer dielectric layer buries the lead and the first conductive contact structure; and the number of the first and second groups,
and forming a second conductive contact structure in the interlayer dielectric layer, wherein the bottom surface of the second conductive contact structure is in contact with the surface of the semiconductor substrate on the other side of the grid groove.
6. The method of manufacturing a semiconductor device according to claim 5, wherein at least one active region is formed in the semiconductor substrate, two gate trenches are arranged side by side in the active region, a first source/drain region is formed in the active region between the two gate trenches, second source/drain regions are respectively formed in the active regions on opposite sides of the two gate trenches, the first conductive contact structure is formed over the first source/drain region and has a bottom surface in contact with a top surface of the first source/drain region, and the second conductive contact structure is formed over the second source/drain region and has a bottom surface in contact with a top surface of the second source/drain region.
7. The method of manufacturing a semiconductor device according to claim 6, wherein the step of forming the first conductive contact structure comprises:
forming a hard mask layer to cover the grid grooves and the semiconductor substrate, wherein the hard mask layer is provided with an opening which exposes the surface of the active region between the two grid grooves;
etching the exposed active region by taking the hard mask layer as a mask to form a contact groove, wherein the bottom surface of the contact groove is higher than the top surface of the polysilicon gate; and the number of the first and second groups,
and filling the first conductive contact structure in the contact groove, and removing the hard mask layer.
8. The method for manufacturing a semiconductor device according to claim 7, wherein the contact trenches are respectively communicated with two of the gate trenches at sidewalls thereof, and the step of forming the conductive line includes:
forming a sacrificial layer to cover the grid groove, the semiconductor substrate and the first conductive contact structure, wherein the sacrificial layer is provided with an opening for exposing part of the surface of the first conductive contact structure;
filling the conducting wires in the openings of the sacrificial layer; and the number of the first and second groups,
and removing the sacrificial layer, and etching the first conductive contact structure to the interface between the bottom surface of the first conductive contact structure and the semiconductor substrate by taking the lead as a mask so as to enable the first conductive contact structure to be as wide as the lead.
9. The method of manufacturing a semiconductor device according to claim 5, wherein the first conductive contact structure is a composite structure including a metal layer and a polysilicon layer stacked over the metal layer, and the material of the conductive line includes a metal.
10. A semiconductor device, comprising:
a semiconductor substrate having a gate trench;
the metal grid electrode is filled in the grid electrode groove, and the height of the metal grid electrode is smaller than the depth of the grid electrode groove; and the number of the first and second groups,
and the polysilicon grid electrode is filled in the grid electrode groove and stacked on the metal grid electrode.
11. The semiconductor device of claim 10, wherein a top surface of the polysilicon gate is lower than a top surface of the semiconductor substrate on the gate trench sidewalls, the semiconductor device further comprising: and the grid isolation layer is filled in the grid groove and fills the grid groove so as to bury the metal grid and the polysilicon grid.
12. The semiconductor device of claim 10, further comprising a gate dielectric layer and a metal barrier layer, wherein the gate dielectric layer is formed on the sidewalls and bottom walls of the gate trench, the metal barrier layer is formed between the gate dielectric layer and the metal gate, surrounds the bottom walls and sidewalls of the metal gate and exposes a surface of the gate dielectric layer above the metal gate, and the sidewalls of the polysilicon gate are in direct contact with the surfaces of the sidewalls of the gate dielectric layer exposed by the metal barrier layer.
13. The semiconductor device according to claim 11, further comprising:
the first conductive contact structure is formed on the semiconductor substrate on one side of the grid groove;
a conductive line formed on the first conductive contact structure;
the interlayer dielectric layer covers the grid isolation layer and the semiconductor substrate, and buries the lead and the first conductive contact structure inside; and the number of the first and second groups,
and the bottom surface of the second conductive contact structure is in contact with the surface of the semiconductor substrate on the other side of the grid groove.
14. The semiconductor device according to claim 13, wherein at least one active region is formed in the semiconductor substrate, two gate trenches are arranged side by side in the active region, a first source/drain region is formed in the active region between the two gate trenches, a second source/drain region is formed in the active region on the opposite side of the two gate trenches, respectively, the first conductive contact structure is formed over the first source/drain region and has a bottom surface in contact with a top surface of the first source/drain region, and the second conductive contact structure is formed over the second source/drain region and has a bottom surface in contact with a top surface of the second source/drain region.
15. The semiconductor device of claim 13, wherein a gap is formed between opposing sidewalls of the first conductive contact structure and the gate trench, the gap being filled with the interlevel dielectric layer.
16. The semiconductor device according to any one of claims 13 to 15, wherein the first conductive contact structure is a composite structure including a metal layer and a polysilicon layer stacked over the metal layer, and a material of the wire includes a metal.
Technical Field
The invention relates to the technical field of integrated circuit manufacturing, in particular to a semiconductor device and a preparation method thereof.
Background
Dynamic Random Access Memory (DRAM) is a well-known semiconductor Memory device, and is widely used in various electronic devices. A Dynamic Random Access Memory (DRAM) is composed of a plurality of repetitive memory cells (cells), each of which is mainly composed of a transistor and a capacitor operated by the transistor, and the memory cells are arranged in an array form, and each of the memory cells is electrically connected to a Bit Line (BL) through a Word Line (WL).
In order to increase the integration of Dynamic Random Access Memory (DRAM), increase the operation speed of devices, and meet the demand of consumers for miniaturized electronic devices, the design of the channel region length of the transistor in the DRAM has been continuously shortened recently, but the transistor will generate serious short channel effect (short channel effect) and on-current (on-current) decrease. One known solution is to change a horizontal Transistor structure in a Dynamic Random Access Memory (DRAM) to a vertical Buried Channel Array Transistor (BCAT) structure, and the structure of the Dynamic Random Access Memory (DRAM) having the Buried Channel Array Transistor (BCAT) is shown in fig. 1 and includes: a semiconductor substrate 100, a gate (i.e., a wordline of a DRAM) 104, and a conductive line (i.e., a bitline of a DRAM) 111. The gate 104 of the word BCAT is embedded in a U-shaped longitudinal trench (not shown) of the semiconductor substrate 100 through a gate isolation layer 106 and insulated and isolated from the semiconductor substrate 100 through a gate dielectric layer 102, source/drain regions (not shown) are respectively formed in the semiconductor substrate 100 on both sides of the gate 104, a conducting wire 111 is connected with the source/drain region on one side of the gate 104 through a first conductive contact structure 109, the source/drain region on the other side of the word line 104 is led out through an upper second conductive contact structure (i.e., a conductive plug) 113, and the conducting wire 111 and the second conductive contact structure 113 are both formed in an interlayer dielectric layer 112. Since current needs to flow between a source region (i.e., a source/drain region on one side of the gate 104) and a drain region (i.e., a source/drain region on the other side of the gate 104, not shown) by detour along the U-shaped longitudinal trench portion, the effective channel length is increased, which reduces the area occupied by the BCAT transistor in each memory cell and suppresses the short channel effect.
The word line of the conventional DRAM is mostly formed by using a metal material, that is, the Gate 104 of the BCAT of the memory cell is mostly a metal Gate, and the metal Gate has a low resistance characteristic and a good control capability for the channel switch, but when the channel is in an off state, the metal Gate may cause a leakage current (e.g., GIDL, Gate Induced Drain leakage) in an overlapping region of the Gate, the source and the Drain, which may affect the performance and reliability of the memory cell, and even cause a data access error of the DRAM.
Therefore, it is necessary to design a new semiconductor device and a method for manufacturing the same to solve the above problems.
Disclosure of Invention
The invention aims to provide a semiconductor device and a preparation method thereof, which can be compatible with the advantages of a metal grid and a polysilicon grid, and can reduce the leakage current of the overlapping region of the grid, a source electrode and a drain electrode under the condition of ensuring that the grid has low resistance value so as to improve the efficiency and reliability of the device.
In order to solve the above technical problem, the present invention provides a method for manufacturing a semiconductor device, comprising the steps of:
providing a semiconductor substrate with a gate trench;
filling a metal gate in the gate trench, wherein the height of the metal gate is smaller than the depth of the gate trench; and the number of the first and second groups,
and filling a polysilicon gate in the gate trench, wherein the polysilicon gate is stacked on the metal gate to form a composite gate.
Optionally, the top surface of the polysilicon gate is lower than the top surface of the semiconductor substrate on the sidewall of the gate trench, and the method for manufacturing a semiconductor device further includes: and filling a grid electrode isolation layer in the grid electrode groove, wherein the grid electrode isolation layer fills the grid electrode groove so as to bury the metal grid electrode and the polysilicon grid electrode.
Optionally, before filling the metal gate in the gate trench, a gate dielectric layer is formed on the sidewall and the bottom wall of the gate trench.
Optionally, after the gate dielectric layer is formed and before the metal gate is filled, a metal blocking layer is formed on the surface of the gate dielectric layer, and after the metal gate is filled, the metal blocking layer surrounds the bottom wall and the side wall of the metal gate and exposes the surface of the gate dielectric layer above the metal gate, so that the side wall of the polysilicon gate is directly contacted with the surface of the gate dielectric layer.
Optionally, the method for manufacturing a semiconductor device further includes:
forming a first conductive contact structure on the semiconductor substrate on one side of the grid groove;
forming a conductive line on the first conductive contact structure;
forming an interlayer dielectric layer to cover the grid groove and the semiconductor substrate, wherein the interlayer dielectric layer buries the lead and the first conductive contact structure; and the number of the first and second groups,
and forming a second conductive contact structure in the interlayer dielectric layer, wherein the bottom surface of the second conductive contact structure is in contact with the surface of the semiconductor substrate on the other side of the grid groove.
Optionally, at least one active region is formed in the semiconductor substrate, two gate trenches are arranged in the active region side by side, a first source/drain region is formed in the active region between the two gate trenches, second source/drain regions are respectively formed in the active regions on the opposite sides of the two gate trenches, the first conductive contact structure is formed above the first source/drain region, the bottom surface of the first conductive contact structure is in contact with the top surface of the first source/drain region, and the second conductive contact structure is formed above the second source/drain region, and the bottom surface of the second conductive contact structure is in contact with the top surface of the second source/drain region.
Optionally, the step of forming the first conductive contact structure comprises:
forming a hard mask layer to cover the grid grooves and the semiconductor substrate, wherein the hard mask layer is provided with an opening which exposes the surface of the active region between the two grid grooves;
etching the exposed active region by taking the hard mask layer as a mask to form a contact groove, wherein the bottom surface of the contact groove is higher than the top surface of the polysilicon gate; and the number of the first and second groups,
and filling the first conductive contact structure in the contact groove, and removing the hard mask layer.
Optionally, the contact trenches are respectively communicated with the two gate trenches at the side walls, and the step of forming the conductive line includes:
forming a sacrificial layer to cover the grid groove, the semiconductor substrate and the first conductive contact structure, wherein the sacrificial layer is provided with an opening for exposing part of the surface of the first conductive contact structure;
filling the conducting wires in the openings of the sacrificial layer; and the number of the first and second groups,
and removing the sacrificial layer, and etching the first conductive contact structure to the interface between the bottom surface of the first conductive contact structure and the semiconductor substrate by taking the lead as a mask so as to enable the first conductive contact structure to be as wide as the lead.
Optionally, the first conductive contact structure is a composite structure, and includes a metal layer and a polysilicon layer stacked above the metal layer, and the material of the wire includes metal.
The present invention also provides a semiconductor device comprising:
a semiconductor substrate having a gate trench;
the metal grid electrode is filled in the grid electrode groove, and the height of the metal grid electrode is smaller than the depth of the grid electrode groove; and the number of the first and second groups,
and the polysilicon grid electrode is filled in the grid electrode groove and stacked on the metal grid electrode.
Optionally, the top surface of the polysilicon gate is lower than the top surface of the semiconductor substrate on the sidewall of the gate trench, and the semiconductor device further includes: and the grid isolation layer is filled in the grid groove and fills the grid groove so as to bury the metal grid and the polysilicon grid.
Optionally, the semiconductor device further includes a gate dielectric layer and a metal barrier layer, the gate dielectric layer is formed on the sidewall and the bottom wall of the gate trench, the metal barrier layer is formed between the gate dielectric layer and the metal gate, surrounds the bottom wall and the sidewall of the metal gate and exposes the surface of the gate dielectric layer above the metal gate, and the sidewall of the polysilicon gate is directly contacted with the surface of the sidewall of the gate dielectric layer exposed by the metal barrier layer.
Optionally, the semiconductor device further includes:
the first conductive contact structure is formed on the semiconductor substrate on one side of the grid groove;
a conductive line formed on the first conductive contact structure;
the interlayer dielectric layer covers the grid groove and the semiconductor substrate, and the interlayer dielectric layer buries the lead and the first conductive contact structure; and the number of the first and second groups,
and the bottom surface of the second conductive contact structure is in contact with the surface of the semiconductor substrate on the other side of the grid groove.
Optionally, at least one active region is formed in the semiconductor substrate, two gate trenches are arranged in the active region side by side, a first source/drain region is formed in the active region between the two gate trenches, second source/drain regions are respectively formed in the active regions on the opposite sides of the two gate trenches, the first conductive contact structure is formed above the first source/drain region, the bottom surface of the first conductive contact structure is in contact with the top surface of the first source/drain region, and the second conductive contact structure is formed above the second source/drain region, and the bottom surface of the second conductive contact structure is in contact with the top surface of the second source/drain region.
Optionally, a gap is formed between the first conductive contact structure and the opposite side wall of the gate trench, and the interlayer dielectric layer fills the gap.
Optionally, the first conductive contact structure is a composite structure, and includes a metal layer and a polysilicon layer stacked above the metal layer, and the material of the wire includes metal.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
1. according to the semiconductor device and the preparation method thereof, the polycrystalline silicon grid is stacked above the metal grid to form the composite grid, so that the electric field distribution of the overlapping area of the composite grid, the source electrode and the drain electrode can be improved, the advantages of the metal grid and the polycrystalline silicon grid can be compatible, the leakage current of the overlapping area of the grid, the source electrode and the drain electrode can be reduced under the condition that the grid is ensured to have low resistance value, and the efficiency and the reliability of the device can be improved. Furthermore, the first conductive contact structure below the conducting wire (namely the bit line in the memory) is a composite structure mainly formed by stacking a metal layer and a polycrystalline silicon layer, so that the contact resistance can be reduced, and the device performance can be improved.
2. The semiconductor device and the preparation method thereof are suitable for manufacturing any product with a metal grid electrode, in particular to a Dynamic Random Access Memory (DRAM) with a structure of a Buried Channel Array Transistor (BCAT), and can improve the problems of data access errors of the DRAM and the like caused by leakage paths of overlapped areas of the grid electrode, a source electrode and a drain electrode and improve the performance of the DRAM.
Drawings
Fig. 1 is a schematic cross-sectional view of a conventional DRAM with a BCAT (only the structure at one active region is shown).
Fig. 2 is a flow chart of a method of fabricating a semiconductor device in accordance with an embodiment of the present invention.
Fig. 3A to 3I are schematic cross-sectional views of the device structure in the manufacturing method of the semiconductor device shown in fig. 2.
Fig. 4 is a schematic cross-sectional view of a device structure of a semiconductor device according to an embodiment of the present invention.
Wherein the reference numbers are as follows:
100-a semiconductor substrate;
1002-a first source/drain region;
1003 — second source/drain regions;
101-a gate trench;
102-a gate dielectric layer;
103. 1042, 1094, 1097-metal barrier layer;
104-a metal gate;
1041. 1093, 1098-metal adhesion layers;
1043. 1095, 1096-Metal silicide layer
105-a polysilicon gate;
106-a gate isolation layer;
107-hard mask layer;
108-a contact trench;
108 a-a gap;
109-a first conductive contact structure;
1091-a metal layer in a first conductive contact structure;
1092-a polysilicon layer in the first conductive contact structure;
110-a sacrificial layer;
111-conductive lines (i.e., bit lines when the semiconductor device is a memory);
112-interlayer dielectric layer;
113-second conductive contact structure.
Detailed Description
The integrated circuit memory and the manufacturing method thereof according to the present invention will be described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Referring to fig. 2, an embodiment of the invention provides a method for manufacturing a semiconductor device, including the following steps:
s1, providing a semiconductor substrate with a gate trench;
s2, filling a metal gate in the gate trench, wherein the height of the metal gate is smaller than the depth of the gate trench; and the number of the first and second groups,
s3, filling a polysilicon gate in the gate trench, wherein the polysilicon gate is stacked on the metal gate to form a composite gate;
s4, filling a grid isolation layer in the grid groove, and forming a first conductive contact structure and a lead which are stacked on the semiconductor substrate at one side of the grid groove;
and S5, forming an interlayer dielectric layer on the semiconductor substrate and the grid isolation layer, and forming a second conductive contact structure in the interlayer dielectric layer, wherein the interlayer dielectric layer buries the lead, and the second conductive contact structure is in contact with the semiconductor substrate on the other side of the grid groove.
Referring to fig. 3A, first, step S1 is executed to provide a semiconductor substrate 100 having a gate trench 101, which includes the following steps:
first, a semiconductor substrate 100 is provided, wherein the semiconductor substrate 100 may be any substrate known to those skilled in the art for supporting semiconductor integrated circuit components, such as silicon-on-insulator (SOI), bulk silicon (bulk silicon), germanium, silicon germanium, gallium arsenide, or germanium-on-insulator (ge). The semiconductor substrate 100 in this embodiment includes a base 1001 and a semiconductor epitaxial layer (not shown) epitaxially grown on the surface thereof. At least one active region (not shown, formed in the semiconductor epitaxial layer) for forming a Buried Channel Array Transistor (BCAT) and a shallow trench isolation structure (not shown) for isolating the active region from the surrounding environment may be defined in the semiconductor substrate 100, and the active region may be a fin-type three-dimensional structure or a planar structure. When the semiconductor device to be manufactured is a memory, the shallow trench isolation structure can isolate all active regions into array arrangement so as to manufacture a storage array of the memory. The shallow trench isolation structure may include a shallow trench (not shown) in the semiconductor substrate 100 and a dielectric material filling the shallow trench, and the dielectric material may include a liner oxide layer (line oxide) formed by a thermal oxidation process and covering the shallow trench and silicon dioxide located on a surface of the liner oxide layer and filling the shallow trench, so as to improve an isolation performance of the shallow trench isolation structure, and the specific forming process includes: (1) forming a pad oxide layer (not shown) on the surface of the semiconductor substrate 100 through a thermal oxidation process; (2) forming a silicon nitride hard mask layer (not shown) by a chemical vapor deposition process, and further forming a patterned photoresist layer (not shown) on the silicon nitride hard mask layer by a photoresist coating, exposing, developing, and other photolithography processes, wherein the patterned photoresist layer covers the active region and the layers above the active region and exposes the silicon nitride hard mask layer above the semiconductor substrate 100 between the active regions serving as isolation regionsA mask layer; (3) performing an etching process on the exposed silicon nitride hard mask layer, the pad oxide layer below the exposed silicon nitride hard mask layer and the semiconductor substrate 100 with a partial depth by using the patterned photoresist layer as a mask to form shallow trenches in the semiconductor substrate 100 between the active regions, wherein the etching process can be dry etching; (4) removing the patterned photoresist layer; (5) forming a liner oxide (not shown) on the sidewalls and bottom surface of the shallow trench by a vapor deposition process or a thermal oxidation process; (6) depositing silicon dioxide on the surface of the shallow trench and the surface of the silicon nitride hard mask layer by adopting the processes of chemical vapor deposition and the like until the shallow trench is filled with the silicon dioxide; (7) carrying out top surface planarization on the silicon dioxide by adopting a chemical mechanical planarization process until the top surface of the silicon dioxide is flush with the top surface of the silicon nitride hard mask layer so as to form a shallow trench isolation structure; (8) the silicon nitride hard mask layer can be removed by wet etching and other processes. Further, after depositing silicon dioxide, or planarizing the top surface of the silicon dioxide, or removing the silicon nitride hard mask layer, a densification process (densification) is performed on the silicon dioxide by using the high-temperature thermal annealing, an Ultraviolet (UV) or laser (laser) high-energy light excitation process, or the like, so as to increase the compactness of the dielectric material, ensure the isolation effect of the shallow trench isolation structure, and strengthen the mechanical strength of the shallow trench isolation structure. The process temperature of the high-temperature thermal annealing process is, for example, 800 ℃ to 1200 ℃, and ozone (O) can be further introduced when the high-temperature thermal annealing process is performed3) And/or a strongly reactive gas such as carbon monoxide (CO). In addition, after the shallow trench isolation structure is formed, a well region (not shown) may be formed in each active region by an ion implantation process and further combining with annealing activation and other processes, wherein a doping type of the well region is determined by a conductivity type of a BCAT transistor to be formed, for example, in the present embodiment, if the formed BCAT transistor is an N-type transistor, the well region is a P-type doping region. The doping depth of the well region can be adjusted according to actual conditions. It should be noted that the pad oxide layer can protect the semiconductor during the process of forming the shallow trench isolation structureThe substrate 100 and the active region, the pad oxide layer may remain to serve as a protection layer for the top surface of the semiconductor substrate 100 and the active region in subsequent processes.
Referring to fig. 3A, a patterned hard mask layer (not shown) is sequentially formed on the surface of the shallow trench isolation structure and the pad oxide layer, and the specific forming process includes: (1) a hard mask layer can be formed on the surface with the shallow trench isolation structure and the pad oxide layer through processes of Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD) and the like, the material of the hard mask layer comprises at least one of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, metal nitride, metal oxide and metal carbide, preferably silicon nitride (SiN), the silicon nitride material is easy to obtain, low in cost and mature in manufacturing method, and has a higher etching selection ratio with the pad oxide layer; (2) openings for defining gates (i.e., word lines) can be formed by a series of photolithography processes such as photoresist coating, exposure using a gate mask (which is a word line mask when the semiconductor device to be manufactured is a memory), and development; (3) taking the photoresist layer with the opening as a mask, and etching the hard mask layer to the surface of the pad oxide layer so as to transfer a grid (namely word line) pattern in the photoresist into the hard mask layer; (4) and removing the photoresist, and continuously etching downwards by taking the hard mask layer as a mask, namely sequentially etching the pad oxide layer and the semiconductor substrate 100 (comprising the active region and the shallow trench isolation structure) with partial depth to form a gate trench 101 in the semiconductor substrate 100. In this embodiment, the bottom wall of the gate trench 101 also extends down into the substrate 1001. The shape of the gate trench 101 may be a rounded U shape, a right-angled U shape, or a trapezoid with a wide top and a narrow bottom. Since the electrical characteristics of the Buried Channel Array Transistor (BCAT) may vary according to the depth from the upper surface (i.e., the top surface) of the semiconductor substrate to the bottom surface of the buried gate thereof, the depth of the gate trench 101 is adjusted to achieve desired electrical characteristics of the Buried Channel Array Transistor (BCAT), thereby improving the electrical performance and reliability of the finally formed semiconductor device.
With reference to fig. 3A, the pad oxide layer, the hard mask layer, and the like on the surface of the semiconductor substrate 100 may be removed by an etching process or a chemical mechanical planarization process, and further cleaned to expose the clean active region surface and the sidewalls and the bottom surface of the gate trench 101, so as to prepare for forming the composite gate. In this embodiment, two gate trenches 101 are arranged side by side in one active region of the semiconductor substrate 100, an active region between the two gate trenches 101 is subsequently used to form a first source/drain region, and active regions on opposite sides of the two gate trenches 101 are subsequently used to form second source/drain regions, respectively, so that two BCATs can be manufactured in one active region, which is beneficial to improving the device integration level.
With reference to fig. 3A, in step S2, the metal gate 104 is filled in the gate trench 101, and the specific process includes:
in the first step, a thermal oxidation (dry or wet oxygen) process, a chemical vapor deposition (cvd), an atomic layer deposition (ald), etc. may be adopted, a gate dielectric layer 102 is covered on the sidewalls and the bottom surface of the active region and the gate trench 101, and the gate dielectric layer 102 is preferably made of a high-K dielectric (having a dielectric constant K greater than 7), such as Ta2O5、TiO2、TiN、Al2O3、Pr2O3、La2O3、LaAlO3、HfO2、ZrO2Or metal oxide of other composition, etc. to be compatible with the metal gate 104 to be formed, which is beneficial to increase the mobility of carriers and improve the device performance. And preferably, the gate dielectric layer 102 made of the high-K dielectric material is prepared by using an Atomic Layer Deposition (ALD) process to maintain the film-forming quality and the thickness uniformity of the gate dielectric layer 102.
And step two, depositing the metal barrier layer 103 on the surface of the gate dielectric layer 102 through processes such as physical vapor deposition, chemical vapor deposition, atomic layer deposition and the like, preferably preparing the metal barrier layer 103 by adopting the atomic layer deposition process to protect the gate dielectric layer 102 and prevent the quality of the gate dielectric layer 102 from being poor. The metal barrier layer 103, also referred to as a metal barrier layer or a metal adhesion barrier layer, is intended to protect the gate dielectric layer 102 from introducing metal impurities in subsequent steps, while improving adhesion between the gate dielectric layer 102 and the metal gate 104. For example, in the present embodiment, the metal gate 104 includes one or more work function metal layers. Without the metal barrier layer 103, metal material from those work function metal layers would diffuse into the gate dielectric layer 102, causing manufacturing defects. In various embodiments, the metal barrier layer 103 includes a metal layer such as Ti or Ta, a metal nitride layer such as TiAlN, TaCN, TaSiN, TiN, or TaN, or any combination of metals and metal nitrides. It should be appreciated that in some cases, a single metal barrier layer 103 may not provide sufficient protection for the gate dielectric layer 102, and it is necessary to form the metal barrier layer 103 having a multi-layer stacked composite structure in the gate trench 101 to enhance protection for the gate dielectric layer 102, so as to prevent the material in the metal gate 104 from diffusing into the gate dielectric layer 102 and causing device defects when the surface metal barrier layer 103 is etched and damaged.
Depositing a metal gate material on the surface of the metal barrier layer 103 by processes such as evaporation, electroplating, chemical vapor deposition, atomic layer deposition, and the like, wherein the deposition thickness of the metal gate material on the bottom surface of the first gate trench 101 at least reaches the thickness required by the metal gate 104 to be formed.
And fourthly, removing the metal gate material on the region outside the gate trench 101 by back etching, filling the metal gate material only in the gate trench 101 to be used as the metal gate 104, and reducing the height of the metal gate 104 to be less than the depth of the gate trench 101 and reducing the height of the metal barrier layer 103 to be not higher than the metal gate 104 by the back etching process. The metal gate 104 is typically a stacked structure, and includes a work function metal layer overlying the metal barrier layer 103 and a metal electrode layer surrounded by the work function metal layer. The material of the work function metal layer is determined by the conductivity type of the BCAT transistor to be formed, and when the BCAT transistor to be formed is a P-type transistor, the work function metal layer in the metal gate 104 is a P-type work function metal material, which may include TiN, TaN, Ru, Mo, Al, WN, w, and w,ZrSi2、MoSi2、TaSi2、NiSi2W or other suitable p-type work function material, or a combination thereof, and when the BCAT transistor to be formed is an N-type transistor, the work function metal layer in the metal gate 104 is an N-type work function metal material, which includes Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable N-type work function material, or a combination thereof. The work function metal layer may be a single layer or may be a plurality of layers. In this embodiment, the top surface of the metal gate 104 is lower than the top surfaces of the semiconductor substrate 100 on both sides, and further lower than the top surfaces of the first source/drain region 1002 and the second source/drain region 1003 formed subsequently, so that the distance between the work function metal layer and the first source/drain region 1002 and the second source/drain region 1003 is increased, which is beneficial to preventing gate-induced drain current leakage (GIDL) from occurring between the first source/drain region 1002 and the second source/drain region 1003. The material of the metal electrode layer may include Al, W, Cu, and/or other suitable metal materials.
Referring to fig. 3B, in step S3, the step of filling the polysilicon gate 105 in the gate trench 101 includes:
in the first step, an atomic layer deposition process is used to deposit a metal adhesion layer 1141, a metal barrier layer 1142 and a metal silicide layer 1143. The metal adhesion layer 1141 can enhance the adhesion between the metal gate 104 and the polysilicon gate 105, and prevent the finally formed composite gate from breaking, and the material of the metal adhesion layer 1141 may be metal such as W, Ti or Ta; the metal barrier layer 1142 can prevent the metal in the metal gate 104 from diffusing into the polysilicon gate 105 to affect the performance of the metal gate 104 and the polysilicon gate 105, and the material of the metal barrier layer 1142 can be TiAlN, TaCN, TaSiN, TiN, TaN or other metal nitrides; the metal silicide layer 1143 may reduce the contact resistance between the metal gate 104 and the polysilicon gate 105 to reduce the resistance of the formed composite gate, and the metal silicide layer 1143 may be a metal silicide containing at least one of metal elements of Ti, W, Co, Ni, Zr, Mo, Ta, and the like.
Step two, depositing a polysilicon material on the surfaces of the gate dielectric layer 102, the metal barrier layer 103, the metal gate 104 and the semiconductor substrate 100 by using processes such as physical vapor deposition, chemical vapor deposition, atomic layer deposition and the like, where the polysilicon material may include at least one of doped polysilicon and undoped polysilicon, and the type of doped ions of the doped polysilicon is the same as the type of doped ions of the first source/drain region 1002 and the second source/drain region 1003 to be formed.
And thirdly, performing back etching on the deposited polysilicon material by adopting a dry etching process or a wet etching process to remove the polysilicon material on the region outside the gate trench 101, so that the polysilicon material is only filled in the gate trench 101 and is used as the polysilicon gate 105 stacked on the metal gate 104.
Referring to fig. 3B to fig. 3G, in step S4, a gate isolation layer 106 is filled in the gate trench 101, and a first conductive contact structure 109 and a conductive line 111 are formed to be stacked on the semiconductor substrate 100 at one side of the gate trench 101, which includes:
referring to fig. 3B and 3C, a gate isolation layer 106 is deposited on the semiconductor substrate 100 and the polysilicon gate 105 by using a physical vapor deposition, a chemical vapor deposition, an atomic layer deposition, or the like, wherein the material of the gate isolation layer 106 includes, but is not limited to, silicon oxide, silicon nitride, and silicon oxynitride.
Referring to fig. 3C, the excess gate isolation layer 106 and the gate dielectric layer 102 on the top surface of the semiconductor substrate 100 may be removed by a chemical mechanical planarization process, to form a composite gate embedded in the gate trench 101, the composite gate including a metal gate 104 and a polysilicon gate 105 stacked thereon, and further using the composite gate and a gate isolation layer 106 as a mask, performing LDD (lightly doped drain) ion implantation, Halo (Halo) ion implantation, source-drain heavily doped ion implantation, etc. on the active regions at both sides of the composite gate (i.e. the gate trench 101), to form a first source/drain region 1002 and a second source/drain region 1003 in the active region at both sides of the composite gate (i.e. the gate trench 101) respectively, thereby, the composite gate electrode and the first source/drain region 1002 and the second source/drain region which are both sides of the composite gate electrode are interposed.1003 constitute the main part of the BCAT architecture. In this embodiment, since two gate trenches 101 are formed in one active region, two BCATs may be fabricated in one active region, and a first source/drain region 1002 shared by the two BCATs is formed in the active region between the two gate trenches 101, the shared first source/drain region 1002 may be a drain region electrically connected to a subsequently formed conductive line 111 (i.e., a bit line of a memory), and the second source/drain region 1003 may be a source region electrically connected to a subsequently formed second conductive contact structure. In other embodiments of the present invention, the gate dielectric layer 102 and the gate isolation layer 106 on the surface of the active region between the two composite gates and outside the two composite gates may also be etched by an etching process to form openings exposing the surfaces of the active regions for forming the first source/drain region 1002 and the second source/drain region 1003, and then LDD (lightly doped drain) ion implantation, Halo (Halo) ion implantation, source-drain heavily doped ion implantation, and the like are performed on the exposed active regions with the remaining gate dielectric layer 102 and the gate isolation layer 106 as masks to form the first source/drain region 1002 and the second source/drain region 1003 in the active regions on both sides of the composite gates. When the gate trench 101 is a U-shaped groove, a U-shaped conductive channel may be formed in a conducting direction along a current (i.e., a current flowing direction from the source region to the drain region which are located at both sides of the composite gate), thereby increasing the length of the conductive channel. Therefore, with the reduction of the transistor size, even if the absolute distance between the source region and the drain region at two sides of the composite gate electrode is reduced, the short channel effect of the transistor structure can be effectively improved because the formed conducting channel is a U-shaped channel. Moreover, since the composite gate is mainly formed by the polysilicon gate and the metal gate which are stacked together, the electric field distribution of the overlapping region of the composite gate and the first source/drain region 1002 and the second source/drain region 1003 can be improved, and therefore, the advantages of the metal gate and the polysilicon gate can be compatible, and under the condition that the gate has a low resistance value, the leakage current of the overlapping region of the gate and the first source/drain region 1002 and the second source/drain region 1003 can be reduced, so that the device performance and reliability can be improved. Further, the first source/drain region 1002 and the second source/drain region 1003 are according toThe transistor structure includes transistor structures of different conductivity types, where the first source/drain region 1002 and the second source/drain region 1003 are doped with ions of corresponding conductivity types, for example, when the transistor structure is an N-type transistor, the doped ions in the source/drain regions are N-type doped ions, and the N-type doped ions are, for example, phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions; when the transistor structure is a P-type transistor, the doped ions in the source/drain region are P-type doped ions, such as boron (B) ions and Boron Fluoride (BF)2 +) Ions, gallium (Ga) ions, and indium (In) ions.
Referring to fig. 3D, a hard mask layer 107 is formed on the semiconductor substrate 100 and the gate isolation layer 106, and the hard mask layer 107 above the first source/drain region 1002 is opened by photolithography and etching processes to form an opening exposing the surface of the first source/drain region 1002.
Step four, referring to fig. 3D, the hard mask layer 107 with the opening is used as a mask to etch the first source/drain region 1002 to a certain depth, so as to form a contact trench 108, wherein a bottom surface of the contact trench 108 is higher than a top surface of the polysilicon gate 105. In the present embodiment, the contact trenches 108 are respectively connected to two gate trenches 101 at sidewalls thereof.
Step five, referring to fig. 3D and 3E, depositing a polysilicon material on the surfaces of the contact trench 108 and the hard mask layer 107 by using physical vapor deposition, chemical vapor deposition, atomic layer deposition, and the like until the deposited polysilicon material fills the contact trench 108, wherein the polysilicon material may include at least one of doped polysilicon and undoped polysilicon. The first conductive contact structure 109 is formed by further removing the polysilicon material outside the hard mask layer 107 and the contact trench 108 by a Chemical Mechanical Planarization (CMP) process.
Step six, referring to fig. 3F and 3G, a sacrificial layer 110 may be formed by spin coating, chemical vapor deposition, physical vapor deposition, or the like to cover the gate isolation layer 106, the semiconductor substrate 100, and the first conductive contact structure 109, and an opening 110a may be further formed in the sacrificial layer 110 by photolithography, etching, or the like, where the width of the opening 110a is smaller than the width of the contact trench 108 shown in fig. 3D to expose a portion of the top surface of the first conductive contact structure 109; the thickness of the sacrificial layer 110 may determine the height of the conductive line 110, and may be silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric material, and/or other suitable insulating material.
Step seven, referring to fig. 3F and 3G, filling the opening 110a with Al, W, Cu and/or other suitable metal materials by processes such as evaporation, electroplating, chemical vapor deposition, atomic layer deposition, and the like, and further removing the metal material on the top of the sacrificial layer 110 by a chemical mechanical planarization process to form the conductive line 111.
Step eight, referring to fig. 3G and fig. 3H, removing the sacrificial layer 110 by using an appropriate process such as etching, and further etching the first conductive contact structure 109 by using the conductive line 111 as a mask, where the etching is stopped at the interface between the first source drain region 1002 and the first conductive contact structure 109 to form a gap 108a, where at this time, the width of the first conductive contact structure 109 is equal to that of the conductive line 111.
Referring to fig. 4, in another embodiment of the invention, the first conductive contact structure 109 may also be a composite structure, and mainly comprises a metal layer 1091 and a polysilicon layer 1092 stacked on the metal layer 1091, so as to reduce the contact resistance and avoid the problem that the cross-sectional area of the sidewall of the remaining first conductive contact structure 109 is reduced due to lateral etching when the first conductive contact structure 109 is etched by using the conductive line 111 as a mask. In an embodiment of the present invention, a metal silicide layer (not shown), a metal blocking layer (not shown), and a metal adhesion layer (not shown) are sequentially disposed between the metal layer 1091 and the first source/drain region 1002 from bottom to top, where the metal adhesion layer may enhance adhesion between the metal layer 1091 and the first source/drain region 1002, so as to prevent the first conductive contact structure 109 from making poor contact with the first source/drain region 1002, and the metal adhesion layer may be W, Ti or Ta; the metal barrier layer can prevent metal in the metal layer from diffusing into the first source drain region 1002 to affect the performance of the first source drain region 1002, and the material of the metal barrier layer can be TiAlN, TaCN, TaSiN, TiN, TaN or other metal nitrides; the metal silicide layer may reduce contact resistance between the metal layer and the first source drain region 1002, and may be a metal silicide containing at least one of metal elements of Ti, W, Co, Ni, Zr, Mo, Ta, or the like. In another embodiment of the present invention, a metal adhesion layer 1093, a metal barrier layer 1094, a metal silicide layer 1095, a metal silicide layer 1096, a metal barrier layer 1097, and a metal adhesion layer 1098 are sequentially formed from bottom to top between the metal layer 1091 and the polysilicon layer 1092, and between the polysilicon layer 1092 and the bit line 111, wherein the metal adhesion layer 1093 can enhance the adhesion between the metal layer 1091 and the polysilicon layer 1092, and prevent the metal layer 1091 and the polysilicon layer 1092 from being in poor contact or even cracked, the metal adhesion layer 1098 can enhance the adhesion between the conductive line 111 and the polysilicon layer 1092, and prevent the bit line 111 and the polysilicon layer 1092 from being in poor contact or even cracked, and the metal adhesion layers 1093 and 1098 can be made of metal such as W, Ti or Ta; the metal barrier layer 1094 may prevent the metal in the metal layer 1091 from diffusing into the polysilicon layer 1092, the metal barrier layer 1097 may prevent the metal in the conductive line 111 from diffusing into the polysilicon layer 1092, and the metal barrier layers 1094 and 1097 may be made of TiAlN, TaCN, TaSiN, TiN, TaN, or other metal nitrides; the metal silicide layer 1095 may reduce contact resistance between the metal layer 1091 and the polysilicon layer 1092, and further block diffusion of metal in the metal layer 1091 into the polysilicon layer 1092, the metal silicide layer 1096 may reduce contact resistance between the wire 111 and the polysilicon layer 1092, and further block diffusion of metal in the wire 111 into the polysilicon layer 1092, and the metal silicide layers 1095 and 1096 may be a metal silicide containing at least one of metal elements such as Ti, W, Co, Ni, Zr, Mo, and Ta.
Referring to fig. 3H, 3I and fig. 4, in step S5, a top planar interlayer dielectric layer 112 may be formed by spin coating, chemical vapor deposition, physical vapor deposition, and the like, and further by combining with a chemical mechanical planarization process, so as to cover the gate isolation layer 106, the first source/drain region 1002, the second source/drain region 1003, the first conductive contact structure 109, and the conductive line 111, the interlayer dielectric layer 112 fills the gap 108a and buries the conductive line 111 and the first conductive contact structure 109, and the interlayer dielectric layer 112 may be made of silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric material, and/or other suitable insulating materials. Then, a contact hole (not shown) aligned with the second source/drain region 1003 is formed in the interlayer dielectric layer 112 by photolithography, etching, or the like, and the contact hole exposes a top surface of the second source/drain region 1003 to expose a portion of the top surface of the first conductive contact structure 109. Then, a metal material is filled into the contact hole through a plating, sputtering, or other process, so as to form a second conductive contact structure 113 (i.e., a conductive contact plug) filled in the contact hole of the interlayer dielectric layer 112, wherein a bottom surface of the second conductive contact structure 113 contacts a top surface of the second source/drain region 1003.
The preparation method of the semiconductor device of the invention substantially replaces the existing single metal grid with the composite grid formed by stacking the polysilicon grid above the metal grid, thereby improving the electric field distribution of the overlapping area of the composite grid and the source electrode and the drain electrode, being compatible with the advantages of the metal grid and the polysilicon grid, and reducing the leakage current of the overlapping area of the grid and the source electrode and the drain electrode under the condition of ensuring that the grid has low resistance value, so as to improve the efficiency and the reliability of the device. Furthermore, the first conductive contact structure under the conducting wire (namely the bit line in the memory) is a composite structure mainly formed by stacking a metal layer and a polycrystalline silicon layer, so that the contact resistance can be reduced, the performance of the device can be improved, and the method is particularly suitable for manufacturing the memory. When the manufacturing method of the semiconductor device of the present invention is applied to the manufacture of a memory, the composite gates of the plurality of active regions are aligned and connected together to form a word line of the memory, and the conductive lines 111 of the plurality of active regions are aligned and connected together to form a bit line of the memory. For example, referring to fig. 3A to 3I, in an embodiment of the present invention, the semiconductor substrate 100 has a plurality of active regions arranged in a cell row (i.e., corresponding to a word line direction) and a cell column (i.e., corresponding to a bit line direction), and a shallow trench isolation structure is further disposed between adjacent active regions, that is, all the shallow trench isolation structures may include a plurality of parallel and a plurality of intersecting active regions, so as to isolate all the active regions into an array structure arranged in a cell row and a cell column for manufacturing a memory array of a memory. Each of the active regions arranged in the word line direction intersects with two adjacent gate trenches 101. The composite gate filled in each gate trench serves as a word line corresponding to a corresponding cell row, and the conductive line 110 on the active region between two gate trenches 101 serves as a bit line on a corresponding cell column.
Referring to fig. 3A to 3I, an embodiment of the present invention provides a semiconductor device, which is preferably manufactured by the above-mentioned manufacturing method of the semiconductor device of the present invention. The semiconductor device includes: the semiconductor device includes a semiconductor substrate 100 having a gate trench 101, a metal gate 104, a polysilicon gate 105, a first conductive contact structure 109, a conductive line 111, an interlayer dielectric layer 112, and a second conductive contact structure 113.
A first source/drain region 1002 and a second source/drain region 1103 are respectively formed in the semiconductor substrate 100 on two sides of the gate trench 101, the metal gate 104 is filled in the gate trench 101, and the height of the metal gate 104 is smaller than the depth of the gate trench 101; the polysilicon gate 105 is filled in the gate trench 101 and stacked on the metal gate 104.
In this embodiment, the top surface of the polysilicon gate 105 is lower than the top surface of the semiconductor substrate 100 on the sidewall of the gate trench 101, the semiconductor device further includes a gate isolation layer 106, the gate isolation layer 106 is filled in the gate trench 101 and fills the gate trench 101, and the metal gate 104 and the polysilicon gate 105 are buried therein.
In this embodiment, the semiconductor device further includes a gate dielectric layer 102 and a metal blocking layer 103, the gate dielectric layer 102 is formed on the sidewall and the bottom wall of the gate trench 101, the metal blocking layer 103 is formed between the gate dielectric layer 102 and the metal gate 104 and surrounds the bottom wall and the sidewall of the metal gate 104, and the metal blocking layer 103 exposes the sidewall of the gate dielectric layer 102 above the metal gate 104The sidewall of the polysilicon gate 105 is in direct contact with the sidewall surface of the gate dielectric layer 102 exposed by the metal barrier layer 103. The gate dielectric layer 102 is preferably made of a high-K dielectric (dielectric constant K is greater than 7), such as Ta2O5、TiO2、TiN、Al2O3、Pr2O3、La2O3、LaAlO3、HfO2、ZrO2Or metal oxide of other composition, etc. to be compatible with the metal gate 104 to be formed, which is beneficial to increase the mobility of carriers and improve the device performance. The metal barrier layer 103 is intended to protect the gate dielectric layer 102, to prevent metal impurities from being introduced into the gate dielectric layer 102, and to improve adhesion between the gate dielectric layer 102 and the metal gate 104. The metal barrier layer 103 may have a single-layer structure or a stacked-layer structure, and include a metal layer such as Ti or Ta, a metal nitride layer such as TiAlN, TaCN, TaSiN, TiN, or TaN, or at least one of a metal and a metal nitride. In this embodiment, the metal gate 104 may include one or more work function metal layers and a metal electrode layer surrounded by the work function metal layers, wherein the material of the work function metal layers is determined by the conductivity type of the BCAT transistor to be formed, and when the BCAT transistor to be formed is a P-type transistor, the work function metal layer in the metal gate 104 is a P-type work function metal material, and the P-type work function metal material may include TiN, TaN, Ru, Mo, Al, WN, ZrSi2、MoSi2、TaSi2、NiSi2W or other suitable p-type work function material, or a combination thereof, and when the BCAT transistor to be formed is an N-type transistor, the work function metal layer in the metal gate 104 is an N-type work function metal material, and the N-type work function metal material includes Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable N-type work function material, or a combination thereof; the material of the metal electrode layer may include Al, W, Cu, and/or other suitable metal materials.
Preferably, a metal adhesion layer 1141, a metal barrier layer 1142 and a metal silicide layer 1143 are sequentially formed between the metal gate 104 and the polysilicon gate 105 from bottom to top. The metal adhesion layer 1141 can enhance the adhesion between the metal gate 104 and the polysilicon gate 105, and prevent the finally formed composite gate from breaking, and the material of the metal adhesion layer 1141 may be metal such as W, Ti or Ta; the metal barrier layer 1142 can prevent the metal in the metal gate 104 from diffusing into the polysilicon gate 105 to affect the performance of the metal gate 104 and the polysilicon gate 105, and the material of the metal barrier layer 1142 can be TiAlN, TaCN, TaSiN, TiN, TaN or other metal nitrides; the metal silicide layer 1143 may reduce the contact resistance between the metal gate 104 and the polysilicon gate 105 to reduce the resistance of the formed composite gate, and the metal silicide layer 1143 may be a metal silicide containing at least one of metal elements of Ti, W, Co, Ni, Zr, Mo, Ta, and the like.
In this embodiment, the first conductive contact structure 109 is formed on the first source/drain region 1002, and the top surface of the first conductive contact structure 109 is flush with the top surface of the gate isolation layer 106, and a gap is formed between the facing sidewalls of the first conductive contact structure 109 and the gate trench 101; a conductive line 111 is formed on the first conductive contact structure 109, and the conductive line 111 and the first conductive contact structure 109 are arranged with the same width; the interlayer dielectric layer 112 covers the gate isolation layer 106, the first source/drain region 1002, the second source/drain region 1003, the conductive line 111 and the first conductive contact structure 109, the interlayer dielectric layer 112 fills the gap on the side wall of the first conductive contact structure 109, and the conductive line 111 and the first conductive contact structure 109 are buried therein. A second conductive contact structure 113 is formed in the interlayer dielectric layer 112, and a bottom surface of the second conductive contact structure 113 contacts a top surface of the second source/drain region 1003.
In an embodiment of the present invention, a plurality of active regions (not shown) are formed in the semiconductor substrate 100, two gate trenches 101 are disposed in each of the active regions side by side, a first source/drain region 1002 is formed in the active region between the two gate trenches 101, second source/drain regions 1003 are respectively formed in the active regions on the opposite sides of the two gate trenches 101, the first conductive contact structure 109 is formed above the first source/drain region 1002 and has a bottom surface contacting a top surface of the first source/drain region 1002, and the second conductive contact structure 113 is formed above the second source/drain region 1003 and has a bottom surface contacting a top surface of the second source/drain region 1003, so that two BCATs are formed in one active region 1003, and device integration is improved. When the semiconductor device is a memory, the active regions are arranged in an array according to unit rows and unit columns, the composite gates on each unit row are connected into a whole to be used as a word line of the memory, and the conducting wires 111 on each unit column are connected into a whole to be used as a bit line of the memory.
Referring to fig. 4, in another embodiment of the present invention, the first conductive contact structure 109 is a composite structure including a metal layer 1091 and a polysilicon layer 1092 stacked on the metal layer 1091, and the conductive line 111 is made of metal.
In an embodiment of the present invention, a metal silicide layer (not shown), a metal blocking layer (not shown), and a metal adhesion layer (not shown) are sequentially disposed between the metal layer 1091 and the first source/drain region 1002 from bottom to top, where the metal adhesion layer may enhance adhesion between the metal layer 1091 and the first source/drain region 1002, so as to prevent the first conductive contact structure 109 from making poor contact with the first source/drain region 1002, and the metal adhesion layer may be W, Ti or Ta; the metal barrier layer can prevent metal in the metal layer from diffusing into the first source drain region 1002 to affect the performance of the first source drain region 1002, and the material of the metal barrier layer can be TiAlN, TaCN, TaSiN, TiN, TaN or other metal nitrides; the metal silicide layer may reduce contact resistance between the metal layer and the first source drain region 1002, and may be a metal silicide containing at least one of metal elements of Ti, W, Co, Ni, Zr, Mo, Ta, or the like.
In another embodiment of the present invention, a metal adhesion layer 1093, a metal barrier layer 1094, a metal silicide layer 1095, a metal silicide layer 1096, a metal barrier layer 1097, and a metal adhesion layer 1098 are sequentially formed from bottom to top between the metal layer 1091 and the polysilicon layer 1092, and between the polysilicon layer 1092 and the bit line 111, wherein the metal adhesion layer 1093 can enhance the adhesion between the metal layer 1091 and the polysilicon layer 1092, and prevent the metal layer 1091 and the polysilicon layer 1092 from being in poor contact or even cracked, the metal adhesion layer 1098 can enhance the adhesion between the conductive line 111 and the polysilicon layer 1092, and prevent the bit line 111 and the polysilicon layer 1092 from being in poor contact or even cracked, and the metal adhesion layers 1093 and 1098 can be made of metal such as W, Ti or Ta; the metal barrier layer 1094 may prevent the metal in the metal layer 1091 from diffusing into the polysilicon layer 1092, the metal barrier layer 1097 may prevent the metal in the conductive line 111 from diffusing into the polysilicon layer 1092, and the metal barrier layers 1094 and 1097 may be made of TiAlN, TaCN, TaSiN, TiN, TaN, or other metal nitrides; the metal silicide layer 1095 may reduce contact resistance between the metal layer 1091 and the polysilicon layer 1092, and further block diffusion of metal in the metal layer 1091 into the polysilicon layer 1092, the metal silicide layer 1096 may reduce contact resistance between the wire 111 and the polysilicon layer 1092, and further block diffusion of metal in the wire 111 into the polysilicon layer 1092, and the metal silicide layers 1095 and 1096 may be a metal silicide containing at least one of metal elements such as Ti, W, Co, Ni, Zr, Mo, and Ta.
In addition, the invention also provides electronic equipment comprising the semiconductor device. The electronic equipment can be various mobile terminals such as mobile phones, wearable equipment, notebook computers and tablet computers, and the wearable equipment comprises intelligent glasses, head-wearing equipment and wrist-wearing equipment such as watches and bracelets.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
