阅读说明：本技术 用于操作具有多个电容器的铁电存储单元的方法 (Method for operating a ferroelectric memory cell with a plurality of capacitors ) 是由 潘锋 吕震宇 于 2019-07-17 设计创作，主要内容包括：公开了用于操作铁电存储单元的方法的实施例。在一个示例中，提供了用于写入铁电存储单元的方法。铁电存储单元包括晶体管和N个电容器。晶体管分别电连接到位线和字线，并且N个电容器中的每个都电连接到N根并行板线(plate line)中的相应板线。在0V与Vdd之间脉冲波动的板线信号根据板线时序被施加到N根板线中的每根。在0V与Vdd之间脉冲波动的位线信号根据位线时序被施加到位线，以将数据的有效状态写入到N个电容器中。该数据包括可被写入到N个电容器中的N+1个有效状态。数据的有效状态是基于板线时序来确定的。位线时序是基于写入到N个电容器中的数据的有效状态来确定的。(Embodiments of a method for operating a ferroelectric memory cell are disclosed. In one example, a method for writing a ferroelectric memory cell is provided. The ferroelectric memory cell includes a transistor and N capacitors. The transistors are electrically connected to a bit line and a word line, respectively, and each of the N capacitors is electrically connected to a corresponding plate line of the N parallel plate lines (plate lines). A plate line signal that is pulsed between 0V and Vdd is applied to each of the N plate lines according to the plate line timing. A bit line signal pulsed between 0V and Vdd is applied to the bit lines according to the bit line timing to write the valid state of the data into the N capacitors. The data includes N +1 valid states that can be written into the N capacitors. The valid state of the data is determined based on the plate line timing. The bit line timing is determined based on the valid state of the data written into the N capacitors.)

1. A method for writing to a ferroelectric memory cell comprising a transistor and N capacitors, where N is a positive integer greater than 1, wherein the transistor is electrically connected to a bit line and a word line, respectively, and each of the N capacitors is electrically connected to a respective plate line of N parallel plate lines, the method comprising:

applying a plate line signal, which is pulsed between 0V and a supply voltage (Vdd) of the ferroelectric memory cell, to each of the N plate lines according to a plate line timing; and

applying a bit line signal pulsed between 0V and Vdd to the bit lines according to bit line timing to write an active state of data into the N capacitors, wherein

The data comprises N +1 valid states that can be written into the N capacitors;

the valid state of the data is determined based on plate line timing; and

the bit line timing is determined based on the valid state of the data written into the N capacitors.

2. The method of claim 1, wherein bit line timing is different from plate line timing.

3. The method of claim 1, wherein the data comprises 2 that cannot be written to the N capacitors^N- (N +1) invalid states.

4. The method of claim 3, wherein each of the invalid states corresponds to a case where bit line timing is the same as plate line timing.

5. The method of claim 1, further comprising: a word line signal greater than Vdd is applied to the word line to select the ferroelectric memory cell.

6. The method of claim 5, wherein the bitline signal, the wordline signal, and the plateline signal are applied in the same write cycle.

7. The method of claim 1, wherein the bit line timing is determined by selecting from a plurality of candidate bit line timings corresponding to data valid states written to the N capacitors.

8. The method of claim 1, wherein

N capacitors are vertically stacked, wherein each capacitor comprises a first electrode, a second electrode and a ferroelectric layer arranged laterally between the first electrode and the second electrode; and

the transistor is electrically connected to the N capacitors and includes a channel structure, a gate conductor, and a gate dielectric layer disposed laterally between the channel structure and the gate conductor.

9. The method of claim 1 wherein the bit line signal and the plate line signal are applied through the bit line and the plate line by a peripheral device electrically connected to the ferroelectric memory cell.

10. The method of claim 9 wherein the peripheral device is disposed below the ferroelectric memory cell.

11. A method for writing to a ferroelectric memory cell comprising a transistor and N capacitors, where N is a positive integer greater than 1, wherein the transistor is electrically connected to a bit line and a word line, respectively, and each of the N capacitors is electrically connected to a respective plate line of N parallel plate lines, the method comprising:

applying a plate line signal, which pulsates between 0V and a bias voltage greater than a supply voltage (Vdd) of the ferroelectric memory cell, to each of the N plate lines according to a plate line timing; and

applying a bit line signal pulsed between 0V and Vdd to the bit lines according to bit line timing to write an active state of data into the N capacitors, wherein

The data includes 2 that can be written into N capacitors^NAn active state; and

the bit line timing is determined based on the valid state of the data written into the N capacitors.

12. The method of claim 11, wherein the bias voltage is about 4/3 at Vdd.

13. The method of claim 11, wherein the bit line signal is different from each of the plate line signals when the valid state of the data is written to the N capacitors.

14. The method of claim 11 further comprising applying a word line signal greater than Vdd to the word line to select the ferroelectric memory cell.

15. The method of claim 14, wherein the bitline signal, the wordline signal, and the plateline signal are applied in the same write cycle.

16. The method of claim 11, wherein the bit line timing is determined by selecting from a plurality of candidate bit line timings corresponding to data valid states written to the N capacitors.

17. The method of claim 11, wherein

N capacitors are vertically stacked, wherein each capacitor comprises a first electrode, a second electrode and a ferroelectric layer arranged laterally between the first electrode and the second electrode; and

the transistor is electrically connected to the N capacitors and includes a channel structure, a gate conductor, and a gate dielectric layer disposed laterally between the channel structure and the gate conductor.

18. The method of claim 11 wherein the bit line signal and the plate line signal are applied through the bit line and the plate line by a peripheral device electrically connected to the ferroelectric memory cell.

19. The method of claim 18 wherein the peripheral device is disposed below the ferroelectric memory cell.

20. A method for reading a ferroelectric memory cell comprising a transistor and N capacitors, where N is a positive integer greater than 1, wherein the transistor is electrically connected to a bit line and a word line, respectively, and each of the N capacitors is electrically connected to a respective plate line of N parallel plate lines, the method comprising:

sequentially applying a plate line signal, which is pulsed between 0V and a bias voltage, to each of the N plate lines; and

after a plate line signal at a bias voltage is applied to each of the N plate lines, bit line signals on the bit lines read from the N capacitors are simultaneously compared with N reference voltages to determine a valid state of data stored in the N capacitors from among a plurality of valid states of data.

21. The method of claim 20, further comprising: after the valid state of the data is determined, the valid state of the data is written back to the N capacitors.

22. The method of claim 21, wherein writing the valid state of the data back to the N capacitors comprises:

applying another plate line signal, which is pulsed between 0V and a bias voltage, to each of the N plate lines according to a plate line timing; and

another bit line signal pulsed between 0V and the supply voltage (Vdd) of the ferroelectric memory cell is applied to the bit lines according to the bit line timing to write the valid state of the data into the N capacitors.

23. The method of claim 22, wherein

The bias voltage is Vdd;

the data comprises N +1 valid states that can be written into the N capacitors;

the N +1 valid states of the data are determined based on plate line timing; and

the bit line timing is determined based on the valid state of the data written into the N capacitors.

24. The method of claim 22, wherein

The bias voltage is greater than Vdd;

the data includes 2 that can be written into N capacitors^NAn active state; and

the bit line timing is determined based on the valid state of the data written into the N capacitors.

25. The method of claim 21, further comprising: a word line signal greater than Vdd is applied to the word line to select the ferroelectric memory cell,

wherein the word line signal and the plate line signal are applied in the same read cycle in which the bit line signal is read.

26. A method for reading a ferroelectric memory cell comprising a transistor and N capacitors, where N is a positive integer greater than 1, wherein the transistor is electrically connected to a bit line and a word line, respectively, and each of the N capacitors is electrically connected to a respective plate line of N parallel plate lines, the method comprising:

sequentially applying a plate line signal, which is pulsed between 0V and a bias voltage, to each of the N plate lines; and

after each of the plate line signals at the bias voltage is applied to a respective plate line of the N plate lines, a respective bit line signal on the bit line read from a respective capacitor of the N capacitors is compared to a reference voltage to determine a valid state of data stored in the N capacitors from among a plurality of valid states of data.

27. The method of claim 26, further comprising: after the valid state of the data is determined, the valid state of the data is written back to the N capacitors.

28. The method of claim 27, wherein writing the valid state of the data back to the N capacitors comprises:

applying another plate line signal, which is pulsed between 0V and a bias voltage, to each of the N plate lines according to a plate line timing; and

another bit line signal pulsed between 0V and the supply voltage (Vdd) of the ferroelectric memory cell is applied to the bit lines according to the bit line timing to write the valid state of the data into the N capacitors.

29. The method of claim 28, wherein

The bias voltage is Vdd;

the data comprises N +1 valid states that can be written into the N capacitors;

the N +1 valid states of the data are determined based on plate line timing; and

the bit line timing is determined based on the valid state of the data written into the N capacitors.

30. The method of claim 28, wherein

The bias voltage is greater than Vdd;

the data includes 2 that can be written into N capacitors^NAn active state; and

the bit line timing is determined based on the valid state of the data written into the N capacitors.

Background

Embodiments of the present disclosure relate to a ferroelectric memory device and a method of operating the same.

Ferroelectric memories such as ferroelectric RAM (FeRAM or FRAM) use a layer of ferroelectric material to achieve non-volatility. The ferroelectric material layer has a non-linear relationship between the applied electric field and the stored apparent charge, and thus can switch polarity under an electric field. Advantages of ferroelectric memories include low power consumption, fast write performance, and excellent maximum read/write endurance.

Disclosure of Invention

Embodiments of a method for operating a ferroelectric memory cell are disclosed herein.

In one example, a method for writing a ferroelectric memory cell is provided. A ferroelectric memory cell includes a transistor and N capacitors, where N is a positive integer greater than 1. The transistors are electrically connected to a bit line and a word line, respectively, and each of the N capacitors is electrically connected to a corresponding plate line of the N parallel plate lines (plate lines). A plate line signal that fluctuates in pulse between 0V and a supply voltage (Vdd) of the ferroelectric memory cell is applied to each of the N plate lines according to a plate line timing. A bit line signal pulsed between 0V and Vdd is applied to the bit lines according to the bit line timing to write the valid state of the data into the N capacitors. The data includes N +1 valid states that can be written into the N capacitors. The valid state of the data is determined based on the plate line timing. The bit line timing is determined based on the valid state of the data written into the N capacitors.

In some embodiments, the bit line timing is different from the plate line timing.

In some embodiments, the data includes 2 that cannot be written to the N capacitors^N- (N +1) invalid states.

In some embodiments, each of the invalid states corresponds to a case where the bit line timing is the same as the plate line timing.

In some embodiments, a word line signal greater than Vdd is applied to the word line to select the ferroelectric memory cell.

In some embodiments, the bit line signal, the word line signal, and the plate line signal are applied in the same write cycle.

In some embodiments, the bit line timing is determined by selecting from a plurality of candidate bit line timings corresponding to valid states of data written to the N capacitors.

In some embodiments, N capacitors are vertically stacked, wherein each capacitor comprises a first electrode, a second electrode, and a ferroelectric layer arranged laterally between the first and second electrodes. The transistor is electrically connected to the N capacitors and includes a channel structure, a gate conductor, and a gate dielectric layer disposed laterally between the channel structure and the gate conductor.

In some embodiments, the bit line signal and the plate line signal are applied through the bit line and the plate line by a peripheral device electrically connected to the ferroelectric memory cell.

In some embodiments, the peripheral device is disposed below the ferroelectric memory cell.

In another example, a method for writing a ferroelectric memory cell is provided. A ferroelectric memory cell includes a transistor and N capacitors, where N is a positive integer greater than 1. The transistors are electrically connected to a bit line and a word line, respectively, and each of the N capacitors is electrically connected to a corresponding plate line of the N parallel plate lines (plate lines). A plate line signal that fluctuates in pulse between 0V and a bias voltage greater than a supply voltage (Vdd) of the ferroelectric memory cell is applied to each of the N plate lines in accordance with a plate line timing. A bit line signal pulsed between 0V and Vdd is applied to the bit lines according to the bit line timing to write the valid state of the data into the N capacitors. The data includes 2 that can be written into N capacitors^NAn active state. The bit line timing is determined based on the valid state of the data written into the N capacitors.

In some examples, the bias voltage is about 4/3 at Vdd.

In some embodiments, the bit line signal is different from each of the plate line signals when a valid state of data is written to the N capacitors.

In some embodiments, a word line signal greater than Vdd is applied to the word line to select the ferroelectric memory cell.

In some embodiments, the bit line signal, the word line signal, and the plate line signal are applied in the same write cycle.

In some embodiments, the bit line timing is determined by selecting from a plurality of candidate bit line timings corresponding to valid states of data written to the N capacitors.

In some embodiments, N capacitors are vertically stacked, wherein each capacitor comprises a first electrode, a second electrode, and a ferroelectric layer arranged laterally between the first and second electrodes. The transistor is electrically connected to the N capacitors and includes a channel structure, a gate conductor, and a gate dielectric layer disposed laterally between the channel structure and the gate conductor.

In some embodiments, the bit line signal and the plate line signal are applied through the bit line and the plate line by a peripheral device electrically connected to the ferroelectric memory cell.

In some embodiments, the peripheral device is disposed below the ferroelectric memory cell.

In yet another example, a method for reading a ferroelectric memory cell is provided. A ferroelectric memory cell includes a transistor and N capacitors, where N is a positive integer greater than 1. The transistors are electrically connected to a bit line and a word line, respectively, and each of the N capacitors is electrically connected to a corresponding plate line of the N parallel plate lines (plate lines). A plate line signal that pulses between 0V and a bias voltage is sequentially applied to each of the N plate lines. After a plate line signal at a bias voltage is applied to each of the N plate lines, bit line signals on the bit lines read from the N capacitors are simultaneously compared with N reference voltages to determine a valid state of data stored in the N capacitors from among a plurality of valid states of data.

In some embodiments, after the valid state of the data is determined, the valid state of the data is written back to the N capacitors. In some embodiments, to write the valid state of the data back to the N capacitors, another plate line signal pulsed between 0V and a bias voltage may be applied to each of the N plate lines according to a plate line timing, and another bit line signal pulsed between 0V and a supply voltage (Vdd) of the ferroelectric memory cell is applied to the bit line according to a bit line timing to write the valid state of the data into the N capacitors.

In some embodiments, the bias voltage is Vdd, the data includes N +1 valid states that can be written into the N capacitors, the N +1 valid states of the data are determined based on plate line timing, and the bit line timing is determined based on the valid states of the data written into the N capacitors.

In some embodiments, the bias voltage is greater than Vdd, and the data includes 2 that can be written to N capacitors^NAn active state, and the bit line timing is determined based on the active state of the data written into the N capacitors.

In some embodiments, a word line signal greater than Vdd is applied to the word line to select the ferroelectric memory cell. The word line signal and the plate line signal are applied in the same read cycle in which the bit line signal is read.

In another example, a method for reading a ferroelectric memory cell is provided. A ferroelectric memory cell includes a transistor and N capacitors, where N is a positive integer greater than 1. The transistors are electrically connected to a bit line and a word line, respectively, and each of the N capacitors is electrically connected to a corresponding plate line of the N parallel plate lines (plate lines). A plate line signal that pulses between 0V and a bias voltage is sequentially applied to each of the N plate lines. After each of the plate line signals at the bias voltage is applied to a respective plate line of the N plate lines, a respective bit line signal on the bit line read from a respective capacitor of the N capacitors is compared to a reference voltage to determine a valid state of data stored in the N capacitors from among a plurality of valid states of data.

In some embodiments, after the valid state of the data is determined, the valid state of the data is written back to the N capacitors. In some embodiments, to write the valid state of the data back to the N capacitors, another plate line signal pulsed between 0V and a bias voltage may be applied to each of the N plate lines according to a plate line timing, and another bit line signal pulsed between 0V and a supply voltage (Vdd) of the ferroelectric memory cell is applied to the bit line according to a bit line timing to write the valid state of the data into the N capacitors.

In some embodiments, the bias voltage is Vdd, the data includes N +1 valid states that can be written into the N capacitors, the N +1 valid states of the data are determined based on plate line timing, and the bit line timing is determined based on the valid states of the data written into the N capacitors.

In some embodiments, the bias voltage is greater than Vdd, and the data includes 2 that can be written to N capacitors^NAn active state, and the bit line timing is determined based on the active state of the data written into the N capacitors.

In some embodiments, a word line signal greater than Vdd is applied to the word line to select the ferroelectric memory cell. The word line signal and the plate line signal are applied in the same read cycle in which the bit line signal is read.

In another example, a method for reading a ferroelectric memory cell is provided. A ferroelectric memory cell includes a transistor and N capacitors, where N is a positive integer greater than 1. The transistors are electrically connected to a bit line and a word line, respectively, and each of the N capacitors is electrically connected to a corresponding plate line of the N parallel plate lines (plate lines). A plate line signal that pulses between 0V and a bias voltage is sequentially applied to each of the N plate lines. After each of the plate line signals at the bias voltage is applied to a respective plate line of the N plate lines, a respective bit line signal on the bit line read from a respective capacitor of the N capacitors is compared to a reference voltage to determine a valid state of data stored in the N capacitors from among a plurality of valid states of data.

In some embodiments, after the valid state of the data is determined, the valid state of the data is written back to the N capacitors. In some embodiments, to write the valid state of the data back to the N capacitors, another plate line signal pulsed between 0V and a bias voltage is applied to each of the N plate lines according to a plate line timing, and another bit line signal pulsed between 0V and a supply voltage (Vdd) of the ferroelectric memory cell is applied to the bit lines according to a bit line timing to write the valid state of the data into the N capacitors.

In some embodiments, the bias voltage is Vdd, the data includes N +1 valid states that can be written into the N capacitors, the N +1 valid states of the data are determined based on plate line timing, and the bit line timing is determined based on the valid states of the data written into the N capacitors.

In some embodiments, the bias voltage is greater than Vdd, and the data includes 2 that can be written to N capacitors^NAn active state, and the bit line timing is determined based on the active state of the data written into the N capacitors.

Drawings

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present invention and, together with the description, further serve to explain the principles of the invention and to enable a person skilled in the pertinent art to make and use the invention.

Fig. 1A illustrates a plan view of an exemplary three-dimensional ferroelectric memory device according to some embodiments of the present invention.

Fig. 1B illustrates a cross-sectional view of the exemplary three-dimensional ferroelectric memory device of fig. 1A, in accordance with some embodiments of the present invention.

Fig. 1C illustrates another cross-sectional view of the exemplary three-dimensional ferroelectric memory device of fig. 1A in accordance with some embodiments of the present invention.

Fig. 1D illustrates a cross-sectional view of another exemplary three-dimensional ferroelectric memory device of fig. 1A, in accordance with some embodiments of the present invention.

Fig. 1E illustrates a cross-sectional view of yet another exemplary three-dimensional ferroelectric memory device of fig. 1A, in accordance with some embodiments of the present invention.

Fig. 2 illustrates a cross-sectional view of another exemplary three-dimensional ferroelectric memory device, in accordance with some embodiments of the present invention.

Fig. 3 illustrates a cross-sectional view of yet another exemplary three-dimensional ferroelectric memory device, in accordance with some embodiments of the present invention.

Fig. 4A-4F illustrate exemplary fabrication methods for forming a three-dimensional ferroelectric memory device according to some embodiments of this invention.

Fig. 5A-5C illustrate another exemplary fabrication method for forming a three-dimensional ferroelectric memory device according to some embodiments of this invention.

Fig. 6A-6H illustrate yet another exemplary fabrication method for forming a three-dimensional ferroelectric memory device according to some embodiments of this invention.

Fig. 7 is a flow chart of an exemplary method for forming a three-dimensional ferroelectric memory device according to some embodiments of this invention.

Fig. 8 is a flow chart of another exemplary fabrication method for forming a three-dimensional ferroelectric memory device according to some embodiments of this invention.

Fig. 9 illustrates a circuit diagram of an exemplary ferroelectric memory device having a plurality of ferroelectric memory cells each having a plurality of capacitors in accordance with some embodiments of the present disclosure.

Fig. 10 illustrates an exemplary timing diagram for writing to a ferroelectric memory cell having multiple capacitors in accordance with some embodiments of the present disclosure.

FIG. 11A is a graph depicting an example data state and corresponding plate line timing and bit line timing, according to some embodiments of the present disclosure.

FIG. 11B is another graph depicting example data states and corresponding plate line timing and bit line timing, according to some embodiments of the present disclosure.

Fig. 12A is a flow chart of an exemplary method of writing to a ferroelectric memory cell having N capacitors in accordance with some embodiments of the present disclosure.

Fig. 12B is a flow chart of another exemplary method of writing to a ferroelectric memory cell having N capacitors in accordance with some embodiments of the present disclosure.

Fig. 13 illustrates an exemplary timing diagram for reading a ferroelectric memory cell having multiple capacitors in accordance with some embodiments of the present disclosure.

Fig. 14 is a flow chart of an exemplary method of reading a ferroelectric memory cell having N capacitors in accordance with some embodiments of the present disclosure.

Fig. 15 illustrates another exemplary timing diagram for reading a ferroelectric memory cell having multiple capacitors in accordance with some embodiments of the present disclosure.

Fig. 16 is a flow chart of another exemplary method of reading a ferroelectric memory cell having N capacitors in accordance with some embodiments of the present disclosure.

Detailed Description

While configurations and arrangements of the present invention are discussed, it is understood that this discussion is intended to be illustrative only. Those skilled in the art will appreciate that other configurations and arrangements can be used without departing from the spirit and scope of the invention. It will be apparent to those skilled in the art that the present invention may be used in a variety of other applications.

It should be noted that references to "one embodiment," "an embodiment," "example embodiment," "some embodiments" in this specification mean that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described herein.

In general, terms may be understood at least in part from the context in which they are used. For example, the terms "one or more" as used herein may be used, at least in part, in the context of context to describe any feature, structure, or characteristic in the singular or in the plural. Similarly, terms such as "a," "an," or "the" may in turn be understood to convey singular usage or plural usage, depending at least in part on the context.

It will be readily understood that the meaning of "on … …", "above … …", and "above … …" in the present invention should be interpreted in the broadest manner such that "on … …" not only means directly on something, but may also include on something with an intermediate feature or layer therebetween, and "on … …", or "above … …" not only means on or above something, but may also include on or above something without an intermediate feature or layer therebetween (i.e., directly on something).

Furthermore, spatially relative terms, such as "under … …," "under … …," "under," "at … …," "over," and the like, may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation of the device depicted in the figures. The device may be otherwise oriented (rotated 90 deg. or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as such.

The term "substrate" as used herein refers to a material to which a subsequent layer of material is added. The substrate itself may be patterned. The material added over the substrate may be patterned or may remain unpatterned. In addition, the substrate may comprise a wide variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may also be made of an electrically non-conductive material, such as glass, plastic, or sapphire wafers.

The term "layer" as used herein refers to a region of material having a thickness. A layer may extend over all of the underlying or overlying structures or may have a lesser extent than the underlying or overlying structures. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes, or at the top or bottom surface of the continuous structure. The layers may extend horizontally, vertically, and/or along a tapered surface. The substrate may be a layer, may include one or more layers therein, and/or may have one or more layers thereon, and/or one or more layers thereunder. One layer may comprise multiple layers. For example, the interconnect layer may include one or more conductors and contact layers (where contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

The term "nominal" as used herein refers to a desired or target value of a characteristic or parameter of a part, process, set at the design stage of a product or process, and includes ranges of values above and/or below the desired value. This range of values may be due to slight differences or tolerances in the manufacturing process. As used herein, "about" refers to a value given as a quantity: the number may vary based on the particular technology node associated with the semiconductor device involved. Based on the particular technology node, the term "about" may refer to a number of values given as: the amount varies, for example, within a range of 10% to 30% of the value (e.g., the value is 10%, ± 20%, or ± 30%).

The term "3D memory device" used herein refers to the following semiconductor devices: the semiconductor device has vertically oriented memory cells (referred to herein as "memory strings") on a laterally oriented substrate such that the memory strings extend in a vertical direction relative to the substrate. As used herein, "vertical" means nominally perpendicular to a lateral surface of a substrate.

The relatively small memory cell density compared to other memory devices is a major limiting factor of existing ferroelectric memories. Planar ferroelectric memory cells can be scaled to smaller dimensions by improving processes, techniques, circuit designs, programming algorithms and manufacturing processes. However, as the feature size of ferroelectric memory cells approaches the lower limit, planar processes and fabrication techniques become challenging and costly. As a result, the storage density of the planar ferroelectric memory device approaches the upper limit.

Various embodiments according to the present invention provide a three-dimensional ferroelectric memory architecture that can cope with density limitations of planar ferroelectric memory devices, thereby achieving an increase in performance to area ratio and a reduction in memory cost per byte.

Fig. 1A is a plan view of an exemplary three-dimensional ferroelectric memory device 100 according to some embodiments of the invention. As shown in fig. 1A, a three-dimensional ferroelectric memory device 100 may include an array of ferroelectric memory cells 102 and a plurality of slot structures 104. Each ferroelectric memory cell 102 may be substantially circular in plan view. It should be understood that the shape of the ferroelectric memory cell 102 in plan view is not limited to a circle, but may be any other shape such as a rectangle, a square, an ellipse, and the like. The slot structure 104 may divide the three-dimensional ferroelectric memory device 100 into a plurality of regions, such as memory blocks and/or a plurality of memory fingers, each block and/or finger including a plurality of ferroelectric memory cells 102. It should be noted that to further illustrate the spatial relationship of the components in the three-dimensional ferroelectric memory device 100, the x and y axes are included in fig. 1A. The x and y axes define a lateral plane of the three-dimensional ferroelectric memory device 100 in which the slot structure 104 extends along the x-square. In some embodiments, the word lines of the three-dimensional ferroelectric memory device 100 also extend in the x-direction, and the bit lines of the three-dimensional ferroelectric memory device 100 extend in the y-direction perpendicular to the x-direction. The same notation is used to describe the spatial relationship throughout the scope of the present invention. In some embodiments, the bit line extension direction and the word line extension direction are not perpendicular to each other.

Fig. 1B illustrates a cross-sectional view of the three-dimensional ferroelectric memory device 100 of fig. 1A along the x-direction, in accordance with some embodiments of the present invention. As shown in fig. 1B, the three-dimensional ferroelectric memory device 100 may include a substrate 106, and the substrate 106 may include silicon (e.g., single crystal silicon), silicon germanium, gallium arsenide, germanium, Silicon On Insulator (SOI), Germanium On Insulator (GOI), or any other suitable material.

In some embodiments, one or more peripheral devices (not shown) are formed on substrate 106 or within substrate 106. The peripheral devices may include any suitable digital, analog, and/or mixed-signal peripheral circuitry for facilitating operation of the three-dimensional ferroelectric memory 100. For example, the peripheral devices may include one or more data buffers, decoders (e.g., row and column decoders), sense amplifiers (sense amplifiers), drivers, charge pumps, current or voltage references, or any active or passive component of a circuit (e.g., a transistor, diode, resistor, or capacitor).

As shown in fig. 1B, the three-dimensional ferroelectric memory device 100 may include an interconnect layer 107 (referred to herein as a "peripheral interconnect layer") located over the peripheral device for transmitting electrical signals to or from the peripheral device. It should be noted that the x and z axes are included in fig. 1B to further illustrate the spatial relationship of the components of the three-dimensional ferroelectric memory device 100. The substrate 106 includes two lateral surfaces (e.g., a top surface and a bottom surface) that extend laterally along an x-direction (e.g., one of the two lateral directions). As used herein, whether a component (e.g., a layer or device) is "on," "above," or "below" another component (e.g., a layer or device) of a semiconductor device (e.g., the three-dimensional ferroelectric memory device 100) is determined in a z-direction (e.g., a vertical direction) relative to a substrate (e.g., the substrate 106) of the semiconductor device when the substrate is positioned within a lowest plane of the semiconductor device in the z-direction. The same notation used to describe the spatial relationship is used throughout the scope of the present invention.

The peripheral interconnect layer 107 may include a plurality of interconnects (also referred to herein as "contacts") including lateral interconnect lines and vertical interconnect (via) contacts. The term "interconnect" as used herein may broadly include any suitable type of interconnect, such as a mid-end-of-line (MEOL) interconnect and a back-end-of-line (BEOL) interconnect. The peripheral interconnect layer 107 may also include one or more interlayer dielectric (ILD) layers (also known as IMD) in which interconnect lines and via contacts may be formed. That is, the peripheral interconnect layer 107 may include interconnect lines and via contacts in one or more ILD layers. The interconnect lines and via contacts in the peripheral interconnect layer 107 may comprise a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, doped silicon, TCO, or any combination thereof. The ILD layer in the peripheral interconnect layer 107 may comprise a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low-k) dielectric, or any combination thereof.

As shown in fig. 1B, the three-dimensional ferroelectric memory device 100 may include a stop layer 108 over the peripheral interconnect layer 107 and a capacitor gate stack 110 over the stop layer 108. In some embodiments, a stop layer 108 is disposed at the array to help stop the etching process during the formation of the ferroelectric memory cells 102 in the array (as shown in the plan view of fig. 1A). In some embodiments, the stop layer 108 is removed at the perimeter or edge of the array of ferroelectric memory cells 102 (as shown in plan view in fig. 1A) to allow the bit lines and contacts to reach the peripheral devices beneath the ferroelectric memory cells 102. As shown in fig. 1B, the stop layer 108 may define a bottom position of the ferroelectric memory cell 102 that extends vertically at least partially through the capacitor gate stack 110.

In some embodiments, capacitor gate stack 110 includes a first dielectric layer 112, a conductor layer 114, and a second dielectric layer 116, arranged in this order from bottom to top. That is, the conductor layer 114 may be vertically formed between the first dielectric layer 112 and the second dielectric layer 116, while the first dielectric layer 112 and the second dielectric layer 116 are disposed below and above the conductor layer 114, respectively. The conductor layer 114 may include a conductive material including, but not limited to, W, Co, Cu, Al, silicide, doped silicon, TCO, or any combination of the above materials. The first and second dielectric layers 112 and 116 may be formed of a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. The stop layer 108 may comprise a dielectric material different from that used in the first dielectric layer 112, including but not limited to a high dielectric constant (high-k) dielectric, such as aluminum oxide (Al)₂O₃) Hafnium oxide (HfO)₂) Tantalum oxide (Ta)₂O₅) Zirconium oxide (ZrO)₂) Titanium oxide (TiO)₂) Or any combination thereof.

As shown in fig. 1B, the three-dimensional ferroelectric memory device 100 may include an array of ferroelectric memory cells 102, wherein each ferroelectric memory cell 102 extends vertically above a peripheral device on a substrate 106. In some embodiments, ferroelectric memory cell 102 is a "1T-1C" cell that includes a capacitor 118 and a transistor 120 located on capacitor 118 and electrically connected to capacitor 118. That is, the three-dimensional ferroelectric memory device 100 may include a "peripheral-capacitor-transistor" architecture in which a peripheral device, a capacitor 118, and a transistor 120 are arranged in this order from bottom to top. In some embodiments, the three-dimensional ferroelectric memory device 100 may include a "peripheral-transistor-capacitor" architecture in which peripheral devices, transistors, and capacitors are arranged in this order from bottom to top. The capacitor 118 of the ferroelectric memory cell 102 may extend vertically through the capacitor gate stack 110 and contact the stop layer 108 at its lower portion.

In some embodiments, the capacitor 118 includes a first electrode 122, a second electrode 126, and a ferroelectric layer 124 laterally disposed between the first electrode 122 and the second electrode 126. The second electrode 126 may be in contact with a conductor layer 114 (located in the capacitor gate stack 110), which conductor layer 114 may extend laterally and act as a gate line for the capacitor 118 of the ferroelectric memory cell 102. In some embodiments, each ferroelectric memory cell 102 (and its capacitor 118) may have a substantially cylindrical shape (e.g., a pillar shape). The first electrode 122, the ferroelectric layer 124, and the second electrode 126 may be arranged in this order in a radial direction from the center of the ferroelectric memory cell 102. It will be appreciated that the shape of the ferroelectric memory cell 102 (and its capacitor 118) is not limited to a cylindrical shape and may be any other suitable shape, such as a trench shape. In some embodiments, ferroelectric layer 124 is a continuous film that extends across multiple capacitors 118 and is shared by multiple capacitors 118.

The first electrode 122 and the second electrode 126 may include a conductive material including, but not limited to, W, Co, Cu, Al, silicon, TCOs, or any combination thereof. In some embodiments, the first electrode 122 comprises silicon, such as polysilicon. In some embodiments, the second electrode 126 and the conductor layer 114 of the capacitor 118 comprise the same conductive material, such as W. The materials of the first electrode 122 and the second electrode 126 may also include, but are not limited to, at least one of: titanium nitride (TiN) and titanium silicon nitride (TiSiN)_x) Titanium aluminum nitride (TiAlN)_x) Titanium carbonitride (TiCN)_x) Tantalum nitride (TaN)_x) Tantalum silicon nitride (TaSiN)_x) Tantalum aluminum nitride (TaAlN)_x) Tungsten nitride (WN)_x) Tungsten silicide (WSi)_x) Tungsten carbonitride (WCN)_x) Ruthenium (Ru), and ruthenium oxide (RuO)_x). In some embodiments, the first electrode 122 and the second electrode 126 comprise the same material. In some embodiments, the first electrode 122 and the second electrode 126 comprise different materials.

In some embodiments, the first or second electrode comprises a Transparent Conductive Oxide (TCO). Transparent conductive oxides include, but are not limited to, TCOs based on doped zinc oxide (ZnO), TCOs based on doped titanium oxide (TiO)₂) TCO based on doped tin oxide (SnO)₂) And a perovskite TCO.

Ferroelectric layer 124 may comprise a ferroelectric binary composite oxide. In some embodiments, ferroelectric layer 124 comprises oxygen and at least one ferroelectric metal. Ferroelectric metals may include, but are not limited to, zirconium (Zr), hafnium (Hf), titanium (Ti), aluminum (Al), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), radium (Ra), vanadium (V), niobium (Nb), tantalum (Ta),

(Db), lanthanum (La), cerium (Ce), gadolinium (Gd), dysprosium (Dy), erbium (Er), and ytterbium (Yb). In some embodiments, ferroelectric layer 124 comprises oxygen and two or more ferroelectric metals. The molar ratio of the two ferroelectric metal elements may be 0.1 to 10 (e.g., 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, with the lower limit being any range bounded by any of the above values, or any range defined by any two of the above values). In one embodiment, ferroelectric layer 124 comprises zrfox and the molar ratio of Zr to Hf is 1. In other embodiments, ferroelectric layer 124 comprises TiHfOx and the molar ratio of Ti to Hf is 1. In some embodiments, ferroelectric layer 124 is a composite layer comprising a plurality of sublayers, at least some of which comprise a ferroelectric metal.

In some embodiments, transistor 120 includes a channel structure 128, a gate conductor 132, and a gate dielectric layer 130 disposed laterally between channel structure 128 and gate conductor 132. The channel structure 128 may include source/drain regions at lower and upper portions thereof, and a channel between the source/drain regions in a vertical direction. As shown in fig. 1B, the channel structure 128 may be disposed over the first electrode 122 and electrically connected to the first electrode 122 through a lower source/drain region thereof. Gate conductor 132 may extend laterally and function as a gate line for transistor 120 and a word line for ferroelectric memory cell 102. A gate conductor 132 and a gate dielectric layer 130 (e.g., gate oxide) may form a gate stack for controlling the electrical properties of the channel in channel structure 128. In some embodiments, each ferroelectric memory cell 102 (and its transistor 120) may have a substantially cylindrical shape (e.g., a pillar shape). The channel structure 128, the gate dielectric layer 130, and the gate conductor 132 may be arranged in this order in a radial direction from the center of the ferroelectric memory cell. It will be appreciated that the shape of the ferroelectric memory cell 102 (and its transistor 118) is not limited to a cylindrical shape, but may be any other suitable shape, such as a trench shape.

In some embodiments, the channel structure 128 includes a semiconductor material, such as single crystal silicon, polycrystalline silicon, amorphous silicon, Ge, any other semiconductor material, or any combination thereof. The source/drain regions of the channel structure 128 may be doped with n-type or p-type dopants to a desired doping level. In some embodiments, gate dielectric layer 130 comprises a dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to aluminum oxide (Al)₂O₃) Hafnium oxide (HfO)₂) Tantalum oxide (Ta)₂O₅) Zirconium oxide (ZrO)₂) Titanium oxide (TiO)₂) Or any combination of the above. In some embodiments, the gate conductor 132 comprises a conductive material including, but not limited to, W, Co, Cu, Al, polysilicon, silicide, doped silicon, TCO, or any combination thereof. In some embodiments, a barrier/adhesion layer (not shown) may include one or more layers for increasing adhesion and/or preventing metal diffusion between gate conductor 132 and gate dielectric layer 130. The material of the barrier/adhesion layer may include, but is not limited to, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or any combination thereof.

As shown in fig. 1B, the three-dimensional ferroelectric memory 100 may include an interconnect layer 134 (referred to herein as a "BEOL interconnect layer") located over the ferroelectric memory device 102 for transferring electrical signals from or to the ferroelectric memory cell 102. The BEOL interconnect layer 134 may include local interconnects formed in one or more ILD layers and contacting components in the three-dimensional ferroelectric memory device 100, such as word lines (e.g., gate conductors 132) and ferroelectric memory cells 102. These interconnects may be referred to herein as "local interconnects" because they are directly connected with components of the three-dimensional ferroelectric memory component 100 for fan-out. Each local interconnect may include an opening (e.g., a via or trench) filled with a conductive material including, but not limited to, W, Co, Cu, Al, doped silicon, silicide, TCO, or any combination thereof. The local interconnect may include a bit line contact 136. In some embodiments, the bit line contact 136 contacts a source/drain region of the transistor 120 located above the channel structure 128.

The BEOL interconnect layer 134 may also include other interconnect lines and via contacts located over local interconnects, such as bit lines 138 formed in one or more ILD layers. In some embodiments, bit line contact 136 contacts bit line 138 and electrically connects bit line 138 with transistor 120 of ferroelectric memory cell 102. Bit line 138 may comprise a conductive material including, but not limited to, W, Co, Cu, Al, doped silicon, silicide, TCO, or any combination thereof. The ILD layer may be formed of a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

Fig. 1C illustrates a cross-sectional view of the three-dimensional ferroelectric memory 100 of some embodiments of the present invention along the y-direction of fig. 1A. Unlike fig. 1B, fig. 1C also shows a cross section of the slot structure 104. As shown in fig. 1C, the slot structure 104 may be formed through the gate conductor 132, the ferroelectric layer 124, the capacitor gate stack 110 and the stop layer 108. The slot structure 104 may be patterned and etched by wet etching and/or dry etching to form a trench. The trench may be filled with a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. As a result, the capacitor 118 and the gate line of the transistor 120 (e.g., the conductor layer 114 and the gate conductor 132) extending in the y-direction (e.g., the direction perpendicular to the slot structure 104 in the plan view of fig. 1A) are electrically insulated from each other to form individual memory blocks and/or fingers. It is understood that the details (e.g., materials, dimensions, functions, etc.) of other similar structures of the three-dimensional ferroelectric memory 100 in both fig. 1B and 1C may not be repeated below.

Fig. 1D illustrates a cross-sectional view of another three-dimensional ferroelectric memory 101 in accordance with some embodiments of the present invention. Unlike the three-dimensional ferroelectric memory device 100 shown in fig. 1B, the three-dimensional ferroelectric memory device 101 in fig. 1D may include a capacitor 119 including a first composite electrode 122 composed of 122-1 and 122-2 of a plurality of electrodes. In addition to the electrode 122-1 comprising a semiconductor material (e.g., silicon), the first composite electrode 122 may also comprise another electrode 122-2 comprising a conductive material including, but not limited to, W, Co, Cu, Al, doped silicon, silicide, TCO, or any combination thereof. Electrode 122-2 may be arranged laterally (e.g., in a radial direction) between electrode 122-1 and ferroelectric layer 124. It is to be understood that the details (e.g., materials, dimensions, functions, etc.) of other similar structures (e.g., ferroelectric memory cell 102) of the three-dimensional ferroelectric memory 100 in both fig. 1B and 1C may not be repeated below.

Fig. 1E illustrates a cross-sectional view of yet another three-dimensional ferroelectric memory device 103, in accordance with some embodiments of the present invention. Unlike the three-dimensional ferroelectric memory device 100 shown in fig. 1B, the three-dimensional ferroelectric memory device 103 in fig. 1D may include a hollow channel structure 128 having a hollow channel 128-1 and a hollow core 128-2. The hollow channel 128-1 may be formed to surround the hollow core 128-2 in the cross-sectional view of fig. E, i.e., to cover the top and bottom surfaces and the side walls of the hollow core 128-2. In some embodiments, the hollow channel 128-1 comprises a semiconductor material, such as monocrystalline silicon, polycrystalline silicon, amorphous silicon, germanium, any other semiconductor material, or any combination thereof. In some embodiments, hollow core 128-2 comprises a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. The hollow core 128-2 may also be partially or fully filled with air. It is understood that the details (e.g., materials, dimensions, functions, etc.) of other similar structures (e.g., ferroelectric memory cell 102) of the three-dimensional ferroelectric memory device 100 in both fig. 1B and 1C may not be repeated below.

Fig. 2 illustrates a cross-sectional view of another exemplary three-dimensional ferroelectric memory device 200 according to some embodiments of this invention. Unlike the three-dimensional ferroelectric memory device 100 or 101 shown in fig. 1A-1D, the three-dimensional ferroelectric memory device 200 in fig. 2 includes an array of ferroelectric memory cells 202, each including a plurality of capacitors 204-1 and 204-2 stacked vertically. Although each ferroelectric memory cell 102 may be a single-level cell (SLC) capable of storing a single bit of information, ferroelectric memory cell 202 may be a multi-level cell (MLC) capable of storing multiple bits of information in capacitors 204-1 and 204-2. However, the number of transistors used in each memory cell may be the same for ferroelectric memory cells 102 and 202. As shown in FIG. 2, ferroelectric memory cell 202 may be a "1T-2C" cell. It is understood that the number of capacitors 204 vertically stacked in the ferroelectric memory cell 202 is not limited to 2, but may be 3, 4 or more. For example, ferroelectric memory Cell 202 may be a "1T-3C" Cell, i.e., a Triple-Level Cell (TLC). In some embodiments, ferroelectric memory cell 202 may include a plurality of transistors therein to form an "nT-mC" cell, where n and m are integers. In such an "nT-mC" cell, n transistors and m capacitors are included in the cell. It is to be understood that the details (e.g., materials, dimensions, functions, etc.) of other similar structures of the three-dimensional ferroelectric memory devices 100 and 200 of both fig. 1B and fig. 2 may not be repeated below.

As shown in fig. 2, the three-dimensional ferroelectric memory device 200 may include a substrate 206, one or more peripheral devices (not shown) formed on and/or within the substrate 206, and an interconnect layer 207 (referred to herein as a "peripheral interconnect layer") over the peripheral devices.

As shown in fig. 2, the three-dimensional ferroelectric memory device 200 may further include a stop layer 208 located above the peripheral interconnect layer 207, a lower capacitor gate stack 210 located above the stop layer 208, and an upper capacitor gate stack 211 located above the lower capacitor gate stack 210. Unlike the three-dimensional ferroelectric memory device 100, which includes only a single capacitor gate stack 110, the ferroelectric memory device 200 may include two capacitor gate stacks 210 and 211, which correspond to the two capacitors 204-1 and 204-2, respectively.

In some embodiments, the lower capacitor gate stack 210 includes: a first lower dielectric layer 212, a lower conductor layer 214, and a second lower dielectric layer 216, which are arranged in this order from bottom to top; upper capacitor gate stack 211 includes a first upper dielectric layer 213, an upper conductor layer 215, and a second upper dielectric layer 217, which are arranged in this order from bottom to top. The upper conductor layer 214 and the lower conductor layer 215 can include a conductive material including, but not limited to, W, Co, Cu, Al, doped silicon, silicide, TCO, or any combination thereof. The upper and lower dielectric layers 212, 213, 216 and 217 may be comprised of a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

As shown in fig. 2, the three-dimensional ferroelectric memory device 200 may include an array of ferroelectric memory cells 202, each ferroelectric memory cell 202 extending vertically over peripheral devices on a substrate 206. In some embodiments, ferroelectric memory cell 202 is a "1T-2C" cell that includes a lower capacitor 204-1, an upper capacitor 204-2, and a transistor 220 located above upper capacitor 204-2 and lower electrode 204-1 and electrically connected to upper capacitor 204-2 and lower electrode 204-1. That is, the three-dimensional ferroelectric memory device 200 may include a "peripheral device-capacitor-transistor" architecture in which a peripheral device, a lower capacitor 204-1, an upper capacitor 204-2, and a transistor 220 are arranged in this order from bottom to top. The lower capacitor 204-1 may extend vertically through the lower capacitor gate stack 210 and contact the stop layer 208 at its lower portion; the upper capacitor 204-2 may extend vertically through the upper capacitor gate stack 211 and contact the upper portion of the lower capacitor 204-1 at its lower portion. In some embodiments, the three-dimensional ferroelectric memory device 200 may include more than two capacitors. In some embodiments, the 3D ferroelectric memory 200 may include more than one transistor. This device 200 may include "n" capacitors and "m" transistors, where n and m are integers.

In some embodiments, the lower capacitor 204-1 includes a first lower electrode 222-1, a second lower electrode 226-1, and a lower ferroelectric layer 224-1 laterally disposed between the first lower electrode 221-2 and the second lower electrode 226-1. The second lower electrode 226-1 may be in contact with the lower conductor layer 214 (which is in the lower capacitor gate stack 210), and the lower conductor layer 214 may extend laterally and serve as a gate line for the lower capacitor 204-1. In some embodiments, the upper capacitor 204-2 includes a first upper electrode 222-2, a second upper electrode 226-2, and an upper ferroelectric layer 224-2 disposed laterally between the first upper electrode 222-2 and the second upper electrode 226-2. The second upper electrode 226-2 may be in contact with the upper conductor layer 215 (which is in the upper capacitor gate stack 211), and the upper conductor layer 215 may extend laterally and serve as a gate line for the upper capacitor 204-2.

In some embodiments, each ferroelectric memory cell 202 (and its capacitors 204-1 and 204-2) may have a substantially cylindrical shape (e.g., a pillar shape). The first lower electrode 222-1, the lower ferroelectric layer 224-1, and the second lower electrode 226-1 may be arranged in this order in a radial direction from the center of the ferroelectric memory cell 202; the first upper electrode 222-2, the upper ferroelectric layer 224-2 and the second upper electrode 226-2 may also be arranged in this order in a radial direction from the center of the ferroelectric memory cell 202. It will be appreciated that the shape of the ferroelectric memory cell 202 (and its capacitors 204-1 and 204-2) is not limited to a cylinder, and may be any other suitable shape, such as a trench shape.

In some embodiments, the first lower electrode 222-1 and the first upper electrode 222-2 in each ferroelectric memory cell 202 are part of a continuous electrode that spans the upper capacitor 204-1 and the lower capacitor 204-2 and is shared by the upper capacitor 204-1 and the lower capacitor 204-2. Similarly, in some embodiments, lower ferroelectric layer 224-1 and upper ferroelectric layer 224-2 in each ferroelectric memory cell 202 are part of a continuous ferroelectric layer that spans lower capacitor 204-1 and upper capacitor 204-2 and is shared by lower capacitor 204-1 and upper capacitor 204-2. According to some embodiments, the continuous ferroelectric layer is a continuous film that spans across the plurality of ferroelectric memory cells 202 and is shared by the plurality of ferroelectric memory cells 202.

As shown in fig. 2, second lower electrode 226-1 and second upper electrode 226-2 in each ferroelectric memory cell 202 may be electrically insulated from each other, e.g., by a dielectric layer. Each of the second lower electrode 226-1 and the second upper electrode 226-2Each of which may be individually and separately electrically connected to the lower conductor layer 214 (gate line of the lower capacitor 204-1) and the upper conductor layer 215 (gate line of the upper capacitor 204-2) such that each of the lower capacitor 204-1 and the upper capacitor 204-2 may be independently controlled to store bit information. In some embodiments, to produce an MLC charge distribution, the vertical dimensions (e.g., in the z-direction) of second lower electrode 226-1 and second upper electrode 226-2 are different. For example, the vertical direction of the second lower electrode 226-1 may be greater than the vertical direction of the second upper electrode 226-2, or vice versa. Thus, the second lower electrode 226-1 and the second upper electrode 226-2 are also different in area, which can introduce different states of the MLC cell. In one embodiment, if the second lower electrode 226-1 is twice the area of the second upper electrode 226-2, or vice versa, an MLC cell may have four states, Q_L0+Q_U0、Q_L1+Q_U0、Q_L0+Q_U1、Q_L1+Q_U1Wherein Q is_L0And Q_L1The charge stored in the lower capacitor is represented by states 0 and 1, respectively, and Q_U0And Q_U1The charge stored in the upper capacitor is represented in states 0 and 1, respectively.

The first electrodes 222-1 and 222-2, and the second electrodes 226-1 and 226-2 may comprise a conductive material including, but not limited to, W, Co, Cu, Al, silicon, silicide, TCO, or any combination thereof. In some embodiments, the first electrodes 221-1 and 222-2 comprise silicon, such as polysilicon. In some embodiments, second electrodes 226-1 and 226-2, and conductor layers 214 and 215 comprise the same conductive material, such as W. The materials of the first electrodes 222-1 and 222-2 and the second electrodes 226-1 and 226-2 may further include, but are not limited to, at least one of the following: doped silicon, TCO, titanium nitride (TiN), titanium silicon nitride (tisnx), titanium aluminum nitride (TiAlNx), titanium carbonitride (TiCNx), tantalum nitride (TaNx), tantalum silicon nitride (TaSiNx), tantalum aluminum nitride (TaAlNx), tungsten nitride (WNx), tungsten silicide (WSix), tungsten carbonitride (WCNx), ruthenium (Ru), and ruthenium oxide (RuOx). In some embodiments, the first electrodes 222-1 and 222-2 and the second electrodes 226-1 and 226-2 comprise the same material. In some embodiments, the first electrodes 221-1 and 221-2 and the second electrodes 226-1 and 226-2 comprise different materials.

In some embodiments, the first or second electrode comprises a Transparent Conductive Oxide (TCO) including, but not limited to: TCO based on doped ZnO, based on doped TiO₂TCO based on doped SnO₂And a perovskite TCO.

Ferroelectric layers 224-1 and 224-2 may comprise ferroelectric binary composite oxides. In some embodiments, ferroelectric layers 224-1 and 224-2 include oxygen and at least one ferroelectric metal, such as zirconium (Zr), hafnium (Hf), titanium (Ti), aluminum (Al), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), radium (Ra), vanadium (V), niobium (Nb), tantalum (Ta), and mixtures thereof,

(Db), lanthanum (La), cerium (Ce), gadolinium (Gd), dysprosium (Dy), erbium (Er) and ytterbium (Yb). In some embodiments, ferroelectric layers 224-1 and 224-2 comprise oxygen and two or more ferroelectric metals. The molar ratio of the two ferroelectric metal elements may be in the range of 0.1 to 10.

In some embodiments, transistor 220 includes a channel structure 228, a gate conductor 232, and a gate dielectric layer 230 disposed laterally between channel structure 228 and gate conductor 232. The channel structure 228 may include source/drain regions at lower and upper portions thereof, and a channel between the source/drain regions in a vertical direction. As shown in fig. 2, channel structure 228 may be disposed over and electrically connected to a continuous electrode including first electrodes 222-2 and 222-1 through underlying source/drain regions. In some embodiments, channel structure 228 may also be disposed under and electrically connected to a continuous electrode including first electrodes 222-2 and 222-1 through its source/drain regions. Gate conductor 232 may extend laterally and function as a gate line for transistor 220 and a word line for ferroelectric memory cell 202. Gate conductor 232 and gate dielectric layer 230 (e.g., gate oxide) may form a gate stack for controlling the electrical properties of the channel in channel structure 228. In some embodiments, each ferroelectric memory cell 202 (and its transistor 220) may have a substantially cylindrical shape (e.g., a pillar shape). The channel structure 228, the gate dielectric layer 230, and the gate conductor 232 may be arranged in this order in a radial direction from the center of the ferroelectric memory cell 202. It will be appreciated that the shape of the ferroelectric memory cell 202 (and its transistor 220) is not limited to a cylinder, but may be any other suitable shape, such as a trench shape.

Fig. 3 illustrates a cross-sectional view of another exemplary three-dimensional ferroelectric memory device 300 according to some embodiments of this invention. Unlike the three-dimensional ferroelectric memory device 200 shown in fig. 2, the three-dimensional ferroelectric memory device 300 shown in fig. 3 includes a plurality of arrays of ferroelectric memory cells 304 and 306 arranged in different planes and sharing bit lines therebetween in the vertical direction. In other words, each bit line may be arranged between the lower ferroelectric memory cell 304 and the upper ferroelectric memory cell 306 in the vertical direction and electrically connected to the lower ferroelectric memory cell 304 and the upper ferroelectric memory cell 306. Such a structure may be repeated in the lateral direction (x-direction and/or y-direction) and in the vertical direction (z-direction). It is to be understood that the details (e.g., materials, dimensions, functions, etc.) of other similar structures in the three-dimensional ferroelectric memory devices 200 and 300 in both fig. 2 and 3 may not be repeated below.

As shown in fig. 3, a three-dimensional ferroelectric memory device 300 may include an array of lower ferroelectric memory cells 304, each memory cell 304 extending vertically above a substrate 302. The three-dimensional ferroelectric memory device 300 may further include a bit line 308 and a lower bit line contact 310 disposed above the lower ferroelectric memory cell 304, the lower bit line contact 310 being in contact with the bit line 308 and a source/drain region of a transistor in the lower ferroelectric memory cell 304. In some embodiments, the three-dimensional ferroelectric memory device 300 further includes an upper bit line contact 312 located above the bit line 308. The upper line contacts 312 may include interconnect lines and via contacts that include conductive materials including, but not limited to, W, Co, Cu, Al, silicon, silicide, or any combination thereof. In some embodiments, the upper level contacts 312 comprise silicon, such as polysilicon. It can be appreciated that although the lower ferroelectric memory cell 304 is shown in fig. 3 as an MLC cell, the lower ferroelectric memory cell 304 may be an SLC cell (as shown with reference to fig. 1B-1D) in accordance with some embodiments.

As shown in fig. 3, the ferroelectric memory device 300 may further include an array of upper ferroelectric memory cells 306, wherein each memory cell 306 extends vertically above the array of lower ferroelectric memory cells 304 and a bit line 308. The upper ferroelectric memory cell 306 can include a transistor 314 and one or more capacitors 316, the capacitors 316 being located above and electrically connected to the transistor 314. It can be appreciated that although the upper ferroelectric memory cell 304 is shown in fig. 3 as an MLC cell, the upper ferroelectric memory cell 304 may be an SLC cell (as shown with reference to fig. 1B-1D) according to some embodiments.

In some embodiments, transistor 314 includes a channel structure 318, a gate conductor 322, and a gate dielectric layer 320 disposed laterally between channel structure 318 and gate conductor 322. The channel structure 318 may include source/drain regions at lower and upper portions thereof, and a channel between the source/drain regions in a vertical direction. As shown in fig. 3, a channel structure 318 may be disposed over the upper bit line contact 312 and electrically connected to the upper bit line contact through its lower source/drain region. Gate conductor 322 can extend laterally and serve as the gate of transistor 314 and the word line for ferroelectric memory cell 306. Gate conductor 322 and gate dielectric layer 320 (e.g., gate oxide) can form a gate stack for controlling the electrical properties of the channel in channel structure 318. In some embodiments, each ferroelectric memory cell 306 (and its transistor 314) may have a substantially cylindrical shape (e.g., a pillar shape). The channel structure 318, the gate dielectric layer 320, and the gate conductor 322 may be arranged in this order in a radial direction from the center of the upper ferroelectric memory cell 306. It will be appreciated that the shape of the upper ferroelectric memory cell 306 (and its transistor 314) is not limited to a cylinder, but may be any other suitable shape, such as a trench shape.

As shown in fig. 3, the three-dimensional ferroelectric memory device 300 can further include a lower capacitor gate stack 324 positioned above the transistor 314 and an upper capacitor gate stack 325 positioned above the lower capacitor gate stack 324. In some embodiments, the lower capacitor gate stack 324 includes a first lower dielectric layer 326, a lower conductor layer 328, and a second lower dielectric layer 330, arranged in this order from bottom to top; the upper capacitor gate stack 325 includes a first upper dielectric layer 327, an upper conductor layer 329, and a second upper dielectric layer 311, which are arranged in this order from bottom to top.

As shown in fig. 3, each upper ferroelectric memory cell 306 may further include a lower capacitor 316-2 extending vertically through the lower capacitor gate stack 324 and an upper capacitor 316-1 extending vertically through the upper capacitor gate stack 325. The transistor 314, the lower capacitor 316-2, and the upper capacitor 316-1 may be stacked in this order in a vertical direction. In some embodiments, the lower capacitor 316-2 includes a first electrode 332, a second lower electrode 336-2, and a ferroelectric layer 334 laterally disposed between the first electrode 332 and the second lower electrode 336-2. The second lower electrode 336-2 may be in contact with a lower conductor layer 328 (which is located in the lower capacitor gate stack 324), which lower conductor layer 328 may extend laterally and serve as a gate line for the lower capacitor 316-2. In some embodiments, the upper capacitor 316-1 includes a first electrode 332, a second upper electrode 336-1, and a ferroelectric layer 334 laterally disposed between the first electrode 332 and the second upper electrode 336-1. The second upper electrode 336-1 may be in contact with an upper conductor layer 329 (which is located in the upper capacitor gate stack 325), which upper conductor layer 329 may extend laterally and serve as a gate line for the upper capacitor 316-1.

In some embodiments, first electrode 332 is a continuous electrode that spans and is shared by upper capacitor 316-1 and lower capacitor 316-2. Similarly, in some embodiments, ferroelectric layer 334 is a continuous ferroelectric layer that spans and is shared by upper capacitor 316-1 and lower capacitor 316-2. As shown in fig. 3, at the bottom of the lower capacitor 316, a lower portion of the first electrode 332 may protrude through the ferroelectric layer 334 and contact an upper source/drain region of the channel structure 318 of the transistor 314. Thus, the channel structure 318 may be located below the first electrode 332 and electrically connected thereto.

As shown in FIG. 3, the second lower electrode 336-2 and the second upper electrode 336-1 in each upper ferroelectric memory cell 306 can be electrically insulated from each other, such as by a dielectric layer. Each of the second lower electrode 336-2 and the second upper electrode 336-1 may be individually and respectively electrically connected with the lower conductor layer 328 (gate line of the lower capacitor 316-2) and the upper conductor layer 329 (gate line of the upper capacitor 316-1) so that each of the lower capacitor 316-2 and the upper capacitor 316-1 may be independently controlled to store bit information.

As shown in fig. 3, the three-dimensional ferroelectric memory device 300 may further include local interconnects, such as gate line contacts 338, word line contacts 340 for gate lines and word lines (e.g., gate conductor 322 of transistor 314) for fan-out capacitors (e.g., conductor layers 328 and 329 for capacitors 316-2 and 316-1). In some embodiments, the three-dimensional ferroelectric memory device 300 includes a core region in which an array of ferroelectric memory cells 304, 306 and a step region surrounding the core region are formed. At least some of the local interconnects, such as gate line contact 338 and word line contact 340, may land on the gate lines and word lines in the stepped region. Each of the gate line contact 338 and the word line contact 340 may include an opening (e.g., a via or a trench) filled with a conductive material including, but not limited to, W, Co, Cu, Al, doped silicon, silicide, or any combination thereof.

Fig. 4A-4F illustrate an exemplary fabrication process for forming a three-dimensional ferroelectric memory device according to some embodiments of the present invention. Fig. 5A-5C illustrate another exemplary fabrication process for forming a three-dimensional ferroelectric memory device according to some embodiments of this invention. Fig. 7 is a flow chart of an example method for forming a three-dimensional ferroelectric memory device according to some embodiments of this invention. Examples of the three-dimensional ferroelectric memory devices illustrated in fig. 4A to 4F, fig. 5A to 5C, and fig. 7 include the three-dimensional ferroelectric memory devices 100 and 200 illustrated in fig. 1 to 2. Fig. 4A-4F, fig. 5A-5C, and fig. 7 will be described together. It is to be understood that the operations shown in method 700 are not exhaustive, and that other operations may be performed before, after, or between the illustrated operational steps. Further, some of the operational steps may be performed concurrently or in a different order than that shown in FIG. 7.

Referring to fig. 7, the method 700 begins with operation 702, in which operation 702 a capacitor gate stack is formed on a substrate. In some embodiments, prior to forming the capacitor gate stack, peripheral devices are formed on and/or in the substrate, and an interconnect layer (e.g., a peripheral interconnect layer) is formed over the peripheral devices. The substrate may be a silicon substrate.

As shown in fig. 4A, a peripheral interconnect layer 404 may be formed on a silicon substrate 402. The peripheral interconnect layer 404 may include interconnects in multiple ILD layers, such as MEOL and/or BEOL interconnect lines and via contacts. In some embodiments, the peripheral interconnect layer 404 includes multiple ILD layers and interconnects therein formed by multiple processes. For example, the interconnects may include conductive materials deposited by one or more thin film deposition processes including, but not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), electroplating, electroless plating, or any combination thereof. The fabrication process to form the interconnects may also include photolithography, Chemical Mechanical Polishing (CMP), wet/dry etching, or any other suitable process. The ILD layer may comprise a dielectric material deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof.

In some embodiments, peripheral devices (not shown) are formed on silicon substrate 402 or in silicon substrate 402 prior to forming peripheral interconnect layer 404. The peripheral devices may include a plurality of transistors formed by a number of processes including, but not limited to, photolithography, dry/wet etching, thin film deposition, thermal growth, implantation (implantation), CMP, and any other suitable process. In some embodiments, doped regions (not shown) are formed in the silicon substrate 402 by ion implantation and/or thermal diffusion, for example, to serve as source and/or drain regions for transistors. In some embodiments, insulating regions (not shown) may also be formed in the silicon substrate 402 by wet/dry etching and thin film deposition.

As shown in fig. 4A, a stop layer 406 is formed over the peripheral interconnect layer 404. The stop layer 406 may comprise a dielectric material including, but not limited to, a high-k dielectric, such as Al₂O₃、HfO₂、Ta₂O₅、ZrO₂、TiO₂Or any combination of the above. The stop layer 406 may be formed by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. In some embodimentsThe stop layer 406 is patterned by photolithography and wet/dry etching to form it at the perimeter or edge of the ferroelectric memory cell array for landing bit lines and contacts on peripheral devices.

As shown in fig. 4A, a capacitor gate stack 408 may be formed over the stop layer 406. In some embodiments, a first dielectric layer 410 is formed on the stop layer 406. The first dielectric layer 410 may comprise a dielectric material different from the dielectric material used in the stop layer 406, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. In some embodiments, a conductor layer 412 comprising a conductive material, such as W, Co, Cu, Al, doped silicon, silicide, TCO, or any combination thereof, is then formed on the first dielectric layer 410. In some embodiments, a second dielectric layer 414 is then formed on the conductor layer 412. The second dielectric layer 414 may comprise the same dielectric material as the first dielectric layer 410, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The first and second dielectric layers 410 and 414 and the conductor layer 412 may be formed by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electrochemical deposition, or any combination thereof.

As shown in fig. 7, method 700 proceeds to operation 704 where one or more capacitors are formed that extend vertically through the capacitor gate stack. In some embodiments, the capacitor gate stack may include a plurality of capacitor gate stacks, and the plurality of capacitors are formed such that each of the capacitors extends vertically through a respective capacitor gate stack. Forming the capacitor may include: etching an opening through the capacitor gate stack to the stop layer; forming a second electrode in the opening; forming a ferroelectric layer in contact with the second electrode; and forming a first electrode in contact with the ferroelectric layer.

As shown in fig. 4B, an opening 416 may be etched through capacitor gate stack 408 (including first and second dielectric layers 410 and 414, and conductor layer 412) to stop layer 406. Opening 416 may be formed by wet etching and/or dry etching dielectric materials (e.g., silicon oxide and silicon nitride) anda conductive material (e.g., W) and the etch stops at stop layer 406. The etching of capacitor gate stack 408 to form opening 416 may be controlled by etch stop on the different material. For example, aluminum oxide (Al)₂O₃) The stop layer 406 may prevent further etching into the peripheral interconnect layer 404.

The second electrode 418 can be formed by depositing a conductive film (e.g., a metal film) on the sidewalls and bottom surface of the opening 416 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electrochemical deposition, or any combination thereof. The resulting conductive film of the second electrode 418 can be electrically connected to the conductor layer 412 in the capacitor gate stack 408. In some embodiments, the second electrode 418 is not formed on the top surface of the capacitor gate stack 408. Any portion of the conductive film formed on the top surface of capacitor gate stack 408 can be removed by patterning the sacrificial/protective layer and etching the sacrificial/protective layer and the conductive film.

As shown in fig. 4C, a ferroelectric layer 420 in contact with the second electrode 418 may be formed along the second electrode 418 and on the top surface of the capacitor gate stack 408. The ferroelectric layer 420 may cover the second electrode 418 formed in the opening 416, for example, at the sidewall and bottom of the opening 416. According to some embodiments, ferroelectric layer 420 may be formed as a continuous film across plurality of openings 416. Ferroelectric layer 420 may comprise a ferroelectric binary composite oxide film deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electrochemical deposition, or any combination thereof. In some embodiments, ferroelectric layer 420 is formed by sequentially depositing a plurality of dielectric films by a thin film deposition process.

As shown in fig. 4D, a first electrode 422 may be formed to fill the remaining space in the opening 416 and to contact the ferroelectric layer 420. In some embodiments, a semiconductor film (e.g., a silicon film) is first deposited using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electrochemical deposition, or any combination thereof, to fill the remaining space in opening 416 and to cover ferroelectric layer 420 within opening 416 and outside opening 416 (e.g., at field regions). The semiconductor film is then patterned and etched (e.g., by wet/dry etching and/or CMP) to remove at least a portion outside of the opening 416 (which is, for example, at the field region) to form a first electrode 422 as shown in fig. 4D. In some embodiments, first electrode 422 is a composite electrode comprising a conductor layer (e.g., a metal film) that is formed within opening 416 and in contact with ferroelectric layer 420 prior to forming a semiconductor film that fills the remaining space in opening 416.

Method 700 proceeds to operation 706 where transistors electrically connected to one or more capacitors are formed over the capacitors, as shown in fig. 7. Forming the transistor may include: forming a channel structure on the first electrode and electrically connected with the first electrode; forming a gate dielectric layer in contact with the channel structure; and forming a gate conductor in contact with the gate dielectric layer.

As shown in fig. 4D, a channel structure 424 may be formed over and aligned with the first electrode 422. In some embodiments, a silicon film is first formed over the semiconductor film forming the first electrode 422. The silicon film may comprise polysilicon or amorphous silicon, which is deposited using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electrochemical deposition, or any combination thereof. Alternatively, the silicon film may include single crystal silicon bonded (e.g., forming a silicon-silicon covalent bond) to the semiconductor film forming the first electrode 422. In some embodiments, after bonding of the single crystal silicon to the first electrode 422, the bonded single crystal silicon is thinned. In some embodiments, the silicon film is then patterned and etched (e.g., by wet/dry etching and/or CMP) to remove at least a portion outside of opening 416 (e.g., at the field region) to form channel structure 424 as shown in fig. 4D. In some embodiments, the upper and/or lower portions of the channel structure 424 are doped with n-type or p-type dopants to form source/drain regions.

As shown in fig. 4E, a gate dielectric layer 426 is formed to cover the sidewalls of the channel structure 424. In some embodiments, gate dielectric layer 426 also covers the top surface of channel structure 424. In some embodiments, the channel structure 424 is first trimmed (e.g., at its sidewalls and top surface) by a wet etch and/or a dry etch. In some embodiments, a gate dielectric layer 426 is then formed by oxidizing the sidewalls and top surface of the trimmed channel structure 424 (e.g., by thermal oxidation). Gate conductor 428 may be formed to fill the spaces between channel structures 424 covered by gate dielectric 426 and be flush with the top surface of gate dielectric 426. In some embodiments, a barrier/adhesion layer (e.g., Ti/TiN) is first formed along the sidewalls of gate dielectric layer 426 using one or more thin film deposition processes, including, but not limited to, CVD, PVD, ALD, electrochemical deposition, or any combination thereof. In some embodiments, one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electrochemical deposition, or any combination thereof, then planarize the deposited conductive film with CMP to make it flush with the top surface of gate dielectric layer 426.

The method 700 proceeds to operation 708 where, as shown in fig. 7, in operation, an interconnect layer (e.g., BEOL interconnect layer) is formed over the transistors. Forming the BEOL interconnect layer may include: forming a bit line contact portion over and in contact with the transistor; and forming a bit line in contact with the bit line contact portion over the bit line contact portion.

As shown in fig. 4F, a BEOL interconnect layer 430 may be formed over the channel structure 424 covered by the gate dielectric layer 426. The BEOL interconnect layers 430 may include interconnects, such as bit line contacts 432 and bit lines 434 formed in multiple ILD layers. In some embodiments, the BEOL interconnect layer 430 includes a plurality of ILD layers formed by a plurality of processes and bit line contacts 432 and bit lines 434 in the ILD layers. For example, bit line contacts 432 and bit lines 434 may comprise conductive material deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication process to form the bit line contacts 432 and the bit lines 434 may also include photolithography, CMP, wet/dry etching, or any other suitable process. The ILD layer may comprise a dielectric material formed by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof.

Fig. 5A-5C illustrate another embodiment of operation 704 in fig. 7, in which a plurality of capacitors are formed in an MLC cell. It is to be understood that the details of other similar operations (e.g., processes, materials, etc.) in fig. 4 and 5 may not be repeated below. As shown in fig. 5A, an MLC ferroelectric memory cell 501 may be formed to extend vertically above a silicon substrate 502. The peripheral interconnect layer 504, the stop layer 506, the lower capacitor gate stack 508, the sacrificial layer 510 (e.g., a silicon nitride layer or any dielectric material different from the dielectric layers of the capacitor gate stacks 508 and 512), and the upper capacitor gate stack 512 may be sequentially deposited in this order from bottom to top by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. As described in detail with reference to fig. 4A-4F, the MLC ferroelectric memory cell 501 may be formed to extend vertically at least partially through the lower capacitor gate stack 508, the sacrificial layer 510, and the upper capacitor gate stack 512 and stop at the stop layer 506.

As shown in fig. 5B, a slot 516 may be etched vertically through stop layer 506, lower capacitor gate stack 508, sacrificial layer 510, and upper capacitor gate stack 512. The gap 516 may be formed by wet etching and/or dry etching a dielectric material (e.g., silicon oxide, silicon nitride, and aluminum oxide) and a conductive material (e.g., W). The slit 516 is used as a channel for removing the sacrificial layer 510, the removal of the sacrificial layer 510 being performed using a wet etch of the sacrificial layer 510 (e.g., silicon nitride) that is selective to the dielectric layer (e.g., silicon oxide) in the capacitor gate stacks 508 and 512. As a result, a lateral recess 518 is formed, which lateral recess 518 divides the second electrode into two electrically insulated lower and upper electrodes for the two capacitors, respectively. As shown in fig. 5C, a dielectric material (e.g., silicon oxide) may fill the gaps 516 and the lateral recesses 518 using CVD, PVD, ALD, or any combination thereof. For example, sacrificial layer 510 (e.g., silicon nitride) may be replaced with silicon oxide. As a result, not only the lower electrode and the upper electrode of the second electrode of each MLC ferroelectric memory cell 501 may be electrically insulated from each other, but also the gate line of the capacitor and the word line of the transistor may be cut by the slits 516 filled with the dielectric material, thereby forming a plurality of memory blocks and/or memory fingers.

Fig. 6A-6H illustrate another exemplary fabrication process for forming a three-dimensional ferroelectric memory device according to some embodiments of this invention. Fig. 8 is a flow chart of another exemplary method for forming a three-dimensional ferroelectric memory device according to some embodiments of this invention. Examples of the three-dimensional ferroelectric memory device shown in fig. 6A-6H and fig. 8 include the three-dimensional ferroelectric memory device 300 shown in fig. 3. Fig. 6A-6H and fig. 8 will be described together. It is to be understood that the operations shown in method 800 are not exhaustive, and that other operations may be performed before, after, or in between the operations shown. Further, some operations may be performed concurrently or in a different order than shown in FIG. 8.

Referring to fig. 8, a method 800 begins at operation 802 where a first ferroelectric memory cell extending in a vertical direction is formed above a substrate. The first ferroelectric memory cell may be formed as described with reference to fig. 4 and 5.

As shown in fig. 8, method 800 proceeds to operation 804 where a bit line electrically connected to a first ferroelectric memory cell is formed above the first ferroelectric memory cell. In some embodiments, a lower bit line electrically connected to the first ferroelectric memory cell is formed over the first ferroelectric memory cell before the bit line is formed, and an upper line contact electrically connected to the bit line is formed over the bit line after the bit line is formed. As shown in fig. 6A, bit lines 602 are formed in one or more ILD layers, as described above with reference to fig. 4F.

As shown in fig. 6A, an upper bit line contact 604 may be formed over the bit line 602 and in contact with the bit line 602. The upper line contacts 604 may include via contacts through the ILD layer and interconnect lines on the top surface of the ILD layer. In some embodiments, a via opening through the ILD layer is first etched by wet and/or dry etching to reach the bitline 602. In some embodiments, a conductive film (e.g., a metal film) or a semiconductor film (e.g., a polysilicon film) may be formed within and outside the via opening (on top of the ILD layer) by deposition using one or more thin film deposition processes, including, but not limited to, CVD, PVD, ALD, electrochemical deposition, or any combination thereof. In some embodiments, the conductive or semiconductor film is then patterned and etched (e.g., by wet/dry etching and/or CMP, etc.) to remove at least a portion of the outside of the via, so as to form the upper line contact 604 as shown in fig. 6A.

Method 800 proceeds to operation 806, shown in fig. 8, where a second ferroelectric memory cell extending vertically above and electrically connected to the bit line is formed. As shown in fig. 6A, a channel structure 606 may be formed over the upper bit line contact 604 and aligned with the upper bit line contact 604. In some embodiments, a silicon film is first formed over the conductive film or semiconductor film forming the upper line contact 604. This silicon film may comprise polycrystalline silicon or amorphous silicon deposited using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. Alternatively, the silicon film may comprise a single crystal silicon layer that is first bonded to the semiconductor film forming the upper line contact 604 (e.g., forming a silicon-silicon covalent bond), and then the bonded single crystal silicon is thinned. In some embodiments, the silicon film is then patterned and etched (e.g., by wet/dry etching and/or CMP) to remove at least a portion of the silicon film outside of the via opening 416 to form the channel structure 606 shown in fig. 6A. In some embodiments, the upper and/or lower portions of the channel structure 606 may be doped with n-type or p-type dopants to form source/drain regions.

As shown in fig. 6B, a gate dielectric layer 608 may be formed to cover the sidewalls and top surface of the channel structure 606. In some embodiments, the channel structure 606 is first trimmed (e.g., at its sidewalls and top surface) by wet etching and/or dry etching. In some embodiments, gate dielectric layer 608 is then formed by oxidizing a portion of the sidewalls and top surface of the trimmed channel structure 606, such as by thermal oxidation. Gate conductor 610 may be formed to fill the space between channel structures 606 covered by gate dielectric 608 and flush with the top surface of gate dielectric 608. In some embodiments, a barrier/adhesion layer (e.g., Ti/TiN) may first be formed along the sidewalls of gate dielectric layer 608 by using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. In some embodiments, a conductive film is then deposited on the barrier/adhesion layer using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electrochemical deposition, or any combination thereof, and then planarized by CMP to be flush with the top surface of the gate dielectric layer 608.

As shown in fig. 6C, the separation layer 612 (e.g., a silicon nitride layer), the lower capacitor gate stack 614, the sacrificial layer 616 (e.g., a silicon nitride layer or any dielectric material different from the dielectric layers in the capacitor gate stacks 614 and 618), and the upper capacitor gate stack 618 may be sequentially deposited in this order from bottom to top by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof.

As shown in fig. 6D, an opening 620 may be etched through upper capacitor gate stack 618, sacrificial layer 616, lower capacitor gate stack 614, separation layer 612, and gate dielectric layer 608 to the upper portion (i.e., source/drain region) of channel structure 606. The opening 620 may be achieved by wet etching and/or dry etching dielectric materials (such as silicon oxide, silicon nitride, and high-k dielectrics) and conductive materials (such as W). The second electrode 622 may be formed by depositing a conductive film (e.g., a metal film) on the sidewalls and bottom surface of the opening 620 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electrochemical deposition, or any combination thereof. The resulting conductive film of the second electrode 622 may be electrically connected to the conductor layers in the capacitor gate stacks 614 and 618. The ferroelectric layer 624 may be formed along the second electrode 622 and in contact with the second electrode 622. The ferroelectric layer 624 may cover the second electrode 622 formed in the opening 620 (e.g., on the sidewalls and bottom surface of the opening 620). The ferroelectric layer 624 may comprise a ferroelectric binary composite oxide film formed by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electrochemical deposition, or any combination thereof.

As shown in fig. 6E, the second electrode 622 and the ferroelectric layer 624 are not formed on the top surface of the upper capacitor gate stack 618. Any portion of the conductive film and the ferroelectric binary composite oxide film formed on the top surface of upper capacitor gate stack 618 can be removed by patterning the sacrificial/protective layer and etching the sacrificial/protective layer, the conductive film, and the ferroelectric binary composite oxide film. As shown in fig. 6E, the second electrode 622 and the ferroelectric layer 624 are not formed on the bottom surface of the opening 620. The conductive film and the portion of the ferroelectric binary composite oxide film formed on the bottom surface of the opening 620 may be removed by a bottom-piercing process including wet etching and/or dry etching.

As shown in fig. 6E, the first electrode 626 may be formed to fill the remaining space in the opening 620. As a result, the sidewalls of the first electrode 626 may contact the ferroelectric layer 624, and the bottom portion of the first electrode 626 may contact the source/drain region at the top portion of the channel structure 606. In some embodiments, a semiconductor thin film (e.g., a silicon film) may be first deposited to fill the remaining space in opening 620 and cover ferroelectric layer 624 within opening 620 and outside opening 620 (e.g., at the field region) using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electrochemical deposition, or any combination thereof. The semiconductor film is then patterned and etched (e.g., by wet/dry etching and/or CMP) to remove portions outside the opening 620 (i.e., at the field regions) to form the first electrode 626 shown in fig. 6E.

As shown in fig. 6F, the separation layer 612 and sacrificial layer 616 (e.g., silicon nitride) may be removed through an aperture (not shown) to form a lateral recess 628 using a wet etch of the separation layer 612 and sacrificial layer 616 (e.g., silicon nitride) that is selective to the dielectric layers (e.g., silicon oxide) in the capacitor gate stacks 614 and 618. The lateral recess 628 may separate the second electrode 622 into two mutually electrically insulated lower and upper electrodes 622-2 and 622-1 for the two capacitors, respectively. In some embodiments, the lateral recess 628 as shown in fig. 6H is filled with a dielectric material (e.g., silicon oxide) by using one or more thin film deposition processes, such as CVD, PVD, ALD, electrochemical deposition, or any combination thereof. In some embodiments, the lateral recess 628 may further separate the ferroelectric layer 624, such that the ferroelectric layer 624 may be separated into a lower portion and an upper portion. That is, the ferroelectric layer 624 may become discontinuous.

As shown in fig. 6G, in some embodiments, the first electrode 626 is a composite electrode that includes a conductor layer 626-2 (e.g., a metal film) that is formed in the opening 620 in contact with the ferroelectric layer 624 prior to forming the semiconductor film 626-1 that fills the remaining space in the opening 620.

As shown in fig. 6H, local interconnects (e.g., gate line contacts 630 and word line contacts 632) may be formed through one or more ILD layers and in contact with corresponding gate lines and word lines in the stepped region. In some embodiments, the via opening is first patterned and etched by wet etching and/or dry etching. In some embodiments, the via openings may be filled with a conductive material to form the gate line contacts 630 and the word line contacts 632 using one or more thin film deposition processes including, but not limited to, PVD, CVD, ALD, electrochemical deposition, or any combination thereof.

As described above with reference to fig. 2 and 3, a three-dimensional ferroelectric memory device may include an array of MLCs (e.g., "nT-mC" cells), where each MLC is capable of storing multiple data bits in multiple capacitors. Unlike planar ferroelectric memory devices whose planar dimensions are controlled by capacitors, in the three-dimensional ferroelectric memory device disclosed herein, the vertically stacked capacitors do not increase the size of the ferroelectric memory cell because the total capacitor area in plan view does not depend on the number of capacitors. As described in detail below, various methods of operating a ferroelectric memory cell (e.g., MLC) having multiple capacitors, such as write and read operations, that allow the three-dimensional ferroelectric memory devices disclosed herein to be used in high capacity applications are also provided according to various embodiments of the present disclosure. It is to be understood that the method of operation disclosed herein may be implemented by any ferroelectric memory device including an MLC array, such as the three-dimensional ferroelectric memory devices disclosed herein with reference to fig. 2 and 3. In other words, the three-dimensional ferroelectric memory devices 200 and 300 may perform any of the write operations or read operations disclosed herein.

Fig. 9 illustrates a circuit diagram of an exemplary ferroelectric memory device 900 having a plurality of ferroelectric memory cells 902, wherein each ferroelectric memory cell 902 has a plurality of capacitors 904, in accordance with some embodiments of the present disclosure. As shown in fig. 9, a ferroelectric memory device 900, such as the three-dimensional ferroelectric memory devices 200 and 300, includes an array of ferroelectric memory cells 902 arranged in rows and columns. Each ferroelectric memory cell 902 may be an MLC including a plurality of capacitors, such as a first capacitor C00 and a second capacitor C01, as shown in fig. 9. "C00" means: the first capacitor of ferroelectric memory cell 902 is electrically connected to first bit line BL [0] and first plate line PL0, and "C01" denotes: the second capacitor of ferroelectric memory cell 902 is electrically connected to first bit line BL [0] and second plate line PL 1. Likewise, "C01" indicates: the capacitor is electrically connected to the second bit line BL [1] and the first plate line PL0, and "C11" indicates: the capacitor is electrically connected to the second bit line BL [1] and the second plate line PL 1. Each ferroelectric memory cell 902 may further comprise a transistor 906, respectively, the transistor 906 being electrically connected to each of the first and second capacitors 904. For simplicity of description, the ferroelectric memory cell 902 that can perform the various operations disclosed herein is generalized as a "1T-nC" MLC that includes one transistor and N capacitors. According to some embodiments, N capacitors (e.g., first and second capacitors 904) are vertically stacked in the three-dimensional ferroelectric memory devices 200 and 300. In one example, the ferroelectric memory cell 902 may be the ferroelectric memory cell 202, the transistor 906 may be the transistor 220, and the first and second capacitors 904 may be the capacitors 204-1 and 204-2, as shown in FIG. 2. In another example, the ferroelectric memory cell 902 may be the ferroelectric memory cell 304 or 306, the transistor 906 may be the transistor 314, and the first and second capacitors 904 may be the capacitors 316-1 and 316-2, as shown in FIG. 3.

As shown in FIG. 9, each word line WL [0] or WL [1] is electrically connected to the gate of transistor 906 in each ferroelectric memory cell 902 in the same row of the array, and each bit line BL [0] or BL [1] is electrically connected to the source/drain of transistor 906 in each ferroelectric memory cell 902 in the same column of the array. The N plate lines may be arranged in parallel and are respectively electrically connected to first nodes of N capacitors 904 in each ferroelectric memory cell 902 in the same row of the array. For example, as shown in fig. 9, the first plate line PL0 is electrically connected to the first node of the first capacitor C00, and the second plate line PL1 is electrically connected to the first node of the second capacitor C01. In each ferroelectric memory cell 902, the drain/source of the transistor 906 is electrically connected to a second node of each of the N capacitors 904, e.g., the second nodes of the first and second capacitors C00 and C01.

In some embodiments, the ferroelectric memory device 900 further comprises a peripheral device 908, the peripheral device 908 being electrically connected to the ferroelectric memory cell 902 through the bit line, the word line and the plate line. The peripheral device 908 may be a peripheral device in the three-dimensional ferroelectric memory device 200 that is electrically connected to the ferroelectric memory cell 202 through the peripheral interconnect layer 207 in which the bit line, the word line, and the plate line are formed. In some embodiments, the peripheral device 908 is disposed below the ferroelectric memory cell 902. The peripheral devices 908 may include any suitable digital, analog, and/or mixed-signal circuitry for facilitating operation of the ferroelectric memory cell 902. For example, peripheral devices 908 may include one or more of the following: a data buffer (e.g., a bit line page buffer), a decoder (e.g., a row decoder or a column decoder), a sense amplifier (sense amplifier), a driver (e.g., a word line driver), a charge pump, a current or voltage reference, or any active or passive component of a circuit (e.g., a transistor, diode, resistor, or capacitor).

In some embodiments, peripheral devices 908 include word line driver circuitry, plate line driver circuitry, and bit line driver circuitry. The word line driver circuit may be configured to generate and apply a plurality of word line signals to each word line, respectively, in order to select a ferroelectric memory cell 902 electrically connected to the same word line (e.g., WL [0] and WL [1]) to which the word line signal is applied. In some embodiments, the word line signal is a voltage signal that pulses between 0V and a bias voltage that is greater than the supply voltage Vdd for the ferroelectric memory cell 902. For example, the word line signal may be Vdd plus a threshold voltage Vth of the transistor 906 to turn on the transistor 906.

The plate line driver circuit may be configured to generate N plate line signals and apply each plate line signal to a respective plate line of the N plate lines (e.g., PL0 and PL1 in fig. 9) according to a plate line timing (i.e., plate line code). In some embodiments, each plate line signal is a voltage signal that pulses between 0V and a bias voltage. According to some embodiments, the plate line signal is a binary signal that is either 0V or a bias voltage. In one example, the bias voltage is Vdd. In another example, the bias voltage is greater than Vdd, such as about 4/3 at Vdd. Each plate line signal may be applied through a respective plate line within the range of a respective capacitor 904 to polarize a respective ferroelectric memory cell 902. Plate line timing may be determined by various factors including: the type of operation (e.g., read or write), the arrangement of the ferroelectric memory cell 902 (e.g., whether all bit lines are accessed at once due to the selected word line), the valid state of data that can be written into the capacitor 904, and so on, which will be described in detail below.

As shown in fig. 9, according to some embodiments, the word lines and the plate lines are in a parallel architecture, where the page operation is the only working configuration that prevents cell disturb in operation. All ferroelectric memory cells 902 of a page on the same word line can be accessed simultaneously in a read or write operation. According to some embodiments, the plate lines are associated with separate word lines, and one plate line is not shared by multiple word lines.

The bit line driver circuit may be configured to generate bit line signals and apply the bit line signals to the respective bit lines (e.g., BL [0] in FIG. 9) according to bit line timing (i.e., bit line encoding) in order to write the valid state of data into the capacitors 904 in the respective ferroelectric memory cells 902 during a write operation. In some embodiments, each bit line signal is a voltage signal that is pulsed between 0V and Vdd. According to some embodiments, the bit line signal is a binary signal that is either 0V or Vdd. During a read operation, the bit line signal may be read by the bit line driver circuit via the corresponding bit line (e.g., BL [0] in FIG. 9) and compared to one or more reference voltages to determine the data valid state stored in the capacitor 904. Bit line timing may be determined by various factors, including: the type of operation (e.g., read or write), the arrangement of the ferroelectric memory cell 902 (e.g., whether all bit lines are accessed at once due to the selected word line), the valid state of data to be read from the capacitor 904 or written to the capacitor 904, etc., which will be described in detail below.

Fig. 10 illustrates an exemplary timing diagram for writing to a ferroelectric memory cell having multiple capacitors in accordance with some embodiments of the present disclosure. FIG. 11A is a graph depicting an example data state and corresponding plate line timing and bit line timing, according to some embodiments of the present disclosure. Fig. 12A is a flow chart of an exemplary method 1200 of writing to a ferroelectric memory cell having N capacitors in accordance with some embodiments of the present disclosure. The ferroelectric memory cell depicted in fig. 10, 11A, and 12A may include a transistor and N capacitors, where N is a positive integer greater than 1 (e.g., 2, 3, 4, 5, 6, etc.). According to some embodiments, the transistors are electrically connected to the bit line and the word line, respectively, and each of the N capacitors is electrically connected to a respective plate line of the N parallel plate lines. Examples of the ferroelectric memory cell depicted in fig. 10, 11A, and 12A (where N is 2) include the ferroelectric memory cell 902 depicted in fig. 9, the ferroelectric memory cell 202 depicted in fig. 2, and the ferroelectric memory cells 304 and 306 depicted in fig. 3. Fig. 10, 11A and 12A will be described together. It can be appreciated that the operations illustrated in the method 1200 are not exhaustive, and that other operations may be performed before, after, or in between the illustrated operations. Additionally, some of the operations may be performed concurrently or in a different order than shown in fig. 12A.

Referring to fig. 12, method 1200 begins with operation 1202 in which a word line signal greater than a supply voltage (Vdd) of a ferroelectric memory cell is applied to a word line to select the ferroelectric memory cell. In some embodiments, the word line signal is Vdd plus the threshold voltage of the transistor. For example, a word line signal may be applied by a word line driver circuit of the peripheral device 908 to the gate of the transistor 906 via the first word line WL [0] to select the ferroelectric memory cell 902 for a write operation. As shown in the timing chart in fig. 10, with a complete write cycle (T0, T1, T2, and T3), the word line signal WL at a high level (e.g., "1") may be applied and held to select the ferroelectric memory cell electrically connected to the corresponding word line. According to some embodiments, the high level of the word line signal WL is greater than Vdd.

The method 1200 proceeds to operation 1204, which is shown in fig. 12A, where in operation 1204, a plate line signal pulsed between 0V and Vdd is applied to each of the N plate lines according to a plate line timing. For example, a first plate line signal may be applied to one node of the first capacitor C00 by the plate line driving circuit of the peripheral device 908 through the first plate line PL0, and a second plate line signal may be applied to one node of the second capacitor C01 by the plate line driving circuit of the peripheral device 908 through the second plate line PL 1. Each of the first and second plateline signals can be applied according to a plateline timing. In some embodiments, the first and second plate line signals are coordinated (e.g., synchronized) in the same write cycle. Each plate line signal may be pulsed between 0V and Vdd to indicate the charge on the ferroelectric memory cell.

As shown in the timing chart in fig. 10, in the write period (T0, T1, T2, and T3) in which the word line signal WL is held at the high level, the first plate line signal PL0 that pulses between the low level (e.g., "0") and the high level (e.g., "1") may be applied according to the plate line timing (e.g., 1, 0, and 1 in T0, T1, T2, and T3, respectively, of PL 0). In the same write cycle, the second plate line signal PL1, which is pulsed between a low level (e.g., "0") and a high level (e.g., "1"), may be applied according to the plate line timing (e.g., PL1 is 0, 1, and 1 in T0, T1, T2, and T3, respectively). In other words, the plate line code PL [1:0] in each write cycle is 01, 00, 10, 11. According to some embodiments, the high level of the plate line signal PL is Vdd.

The method 1200 proceeds to operation 1206, which is shown in fig. 12A, in which operation 1206 a bit line signal pulsed between 0V and Vdd is applied to the bit line according to the bit line timing to write the valid state of the data into the N capacitors. The data includes N +1 valid states that can be written into the N capacitors. For example, a bit line signal may be applied by the bit line driver circuit of the peripheral device 908 to the source/drain of the transistor 906 via the first bit line BL [0] to write the valid state (e.g., two bits) of data into the first and second capacitors C00 and C01 of the selected ferroelectric memory cell 902. The bit line signals may be applied according to bit line timing. In some embodiments, the bit line signal and the first and second plate line signals are coordinated (e.g., synchronized) in the same write cycle.

As shown in the timing chart in fig. 10, in the write period (T0, T1, T2, and T3) in which the word line signal WL is held at the high level, the bit line signal BL whose pulse fluctuates between the low level (e.g., "0") and the high level (e.g., "1") may be applied according to the bit line timing. According to some embodiments, the high level of the bit line signal BL is Vdd. Bit line timing in combination with plate line coding PL [1:0]]The state of data to be written into the first and second capacitors C00 and C01 of the ferroelectric memory cell can be determined. It can be appreciated that for multi-level bits stored in N capacitors, the number of all states of data is 2^N. For example, 2-bit data stored in two capacitors may have four states (00, 01, 10, and 11), and 3-bit data stored in three capacitors may have eight states (000, 001, 010, 011, 100, 101, 110, and 111). However, due to the nature of the write operation of the ferroelectric memory cell, not all states of data may be written into the N capacitors. Specifically, in the case where each of the bit line signal and the plate line signal pulsates between the same levels (e.g., between 0V and Vdd), if the bit line timing is the same as the plate line timing (e.g., the timing waveform of any of the plate line signals), the resulting state becomes invalid, and thus cannot be written into the N capacitors.

In some embodiments, the N bits of data include N +1 valid states that can be written into the N capacitors. For example, 2-bit data may include 3 valid states writable into 2 capacitors, and 3-bit data may include 4 valid states writable into 3 capacitors, and 4-bit data may include 5 valid states writable into 4 capacitors. According to some embodiments, each of the N +1 valid states of data occurs when the bit line timing is different from the plate line timing. On the other hand, the remaining states are invalid states. In some embodiments, the N bits of data include data that cannot be written to the N capacitors2^N- (N +1) invalid states. For example, 2-bit data may include 1 invalid state, 3-bit data may include 4 invalid states, and 4-bit data may include 11 invalid states. According to some embodiments, 2 of the data^NEach of the (N +1) invalid states occurs at the same bit line timing as the plate line timing.

As shown in FIG. 11A, for a given plate line timing (e.g., plate line code PL [1:0] in FIG. 10), by permuting the bit line timing in the write cycles (T0, T1, T2, and T3), the 2-bit data for the 2 capacitors C01 and C00 has (contains) only 3 states (00, 01, and 11) that can be written into capacitors C01 and C00. The 3 valid states occur when the bit line timing is different from the plate line timing, assuming that the standard bias voltage 0V/Vdd is used by each of the plate line signal and the bit line signal. In contrast, the resulting data state becomes invalid (e.g., X1 and 0X) in both cases where the bit line timing is the same as the plate line timing (e.g., 0011 for PL1 and 1001 for PL 0). It can be appreciated that although the number of valid states (and invalid states) of data is determined by the number of data bits N (which is also the number of capacitors), the particular valid states may vary based on the particular plate line timing. That is, the valid state of the data may be determined based on the plate line timing. For example, although the 3 valid states of the data in fig. 11A are 00, 01, and 11, they may be changed in the case where the plate line timing is changed. In some embodiments, since the plate line timing is a given value (e.g., a preset plate line code) for a write operation of the ferroelectric memory device, the valid states of the data and the number of particular valid states are also known.

It can also be appreciated that there may be more than one candidate bit line timing that may result in the same data valid state. For example, as shown in FIG. 11, active state 00 may be implemented by two candidate bit line timings (0000 and 0001), and active state 11 may be implemented by three candidate bit line timings (0111, 1011, and 1111). As a result, in some embodiments, for each valid data state, a given bit line timing may be determined (e.g., selected from a plurality of candidate bit line timings) for writing the valid state of data into the N capacitors. In other words, the bit line timing is determined based on the valid state of the data written into the N capacitors. For example, the bit line timing may be determined by selecting from a plurality of candidate bit line timings corresponding to data valid states written into the N capacitors. Referring back to fig. 10, the specific bit line timing of the bit line signal BL in a write cycle is determined based on the valid state of data to be written into the capacitors C01 and C00 in the write cycle, and is changed when the valid state of the data is changed, for example, in the next write cycle. If the same data valid state is written in different write cycles, the bit line timing of the bit line signal BL in each of these write cycles remains unchanged.

By varying the bias voltage of the plate line signal (e.g., greater than Vdd), the number of valid states of multi-level bit data that can be written into the N capacitors of the ferroelectric memory cell can be increased. In the case where the bit line timing is the same as the plate line timing, since the bias voltage of the plate line signal becomes greater than the bit line signal that is still Vdd, the resulting data state can be written into the N capacitors (i.e., becomes an active state) because of the nature of the write operation of the ferroelectric memory cell. Fig. 12B is a flow chart of another exemplary method 1201 of writing to a ferroelectric memory cell having N capacitors in accordance with some embodiments of the present disclosure. FIG. 11B is another graph depicting example data states and corresponding plate line timing and bit line timing, according to some embodiments of the present disclosure. Fig. 11B and 12B will be described together. Method 1201 is similar to method 1200 except that at 1205, instead of applying a plate line signal that pulses between 0V and Vdd as at 1204 of FIG. 12A, a plate line signal that pulses between 0V and a bias voltage greater than Vdd for the ferroelectric memory cell is applied to each of the N plate lines according to a plate line timing. In some examples, the bias voltage is about 4/3 at Vdd.

The method 1201 proceeds to operation 1207, which is shown in fig. 12B, in which operation 1207 a bit line signal pulsed between 0V and Vdd is applied to the bit lines according to bit line timing to write an active state of data into the N capacitors. The data packetIncluding 2 that can be written into N capacitors^NAn active state. For example, a bit line signal may be passed through first bit line BL [0] by a bit line driver circuit of peripheral device 908]Is applied to the source/drain of the transistor 906 to write the active state (e.g., two bits) of data into the first and second capacitors C00 and C01 of the selected ferroelectric memory cell 902. The bit line signals may be applied according to bit line timing. In some embodiments, the bit line signal and the first and second plate line signals are coordinated (e.g., synchronized) in the same write cycle. In some embodiments, the additional bias voltage due to the plate line signal compared to Vdd on the bit line signal, comprises 2^NN-bit data of one active state can be written into N capacitors. In other words, all states of data become active states even if the bit line timing is the same as the plate line timing. For example, 2-bit data may include 4 valid states writable into 2 capacitors, and 3-bit data may include 8 valid states writable into 3 capacitors, and 4-bit data may include 16 valid states writable into 4 capacitors.

As shown in FIG. 11B, a given plate line timing (e.g., plate line code PL [1:0] is provided in the write cycles (T1, T2, and T3)]It is 00, 10, 0.66/1.33). Unlike the example shown in fig. 11A, the bias voltage in T3 is 2/3Vdd and 4/3Vdd for PL1 and PL0, respectively, instead of 0 and Vdd. By permuting the bit line timing in the write cycles (T1, T2, and T3), 2-bit data for two capacitors (e.g., C01 and C00 or C11 and C10) in each ferroelectric memory cell can have all 2-bits writable into both capacitors²(4) Active states (00, 01, 10 and 11). Bit line signal BL [0]]And BL [1]]The pulse fluctuates between 0V and Vdd (e.g., 0, 1/3Vdd or Vdd), which will be different from the plate line signals PL0 and PL1 in T3, since the plate line signal can be biased at 4/3Vdd in T3. Fig. 11B corresponds to two adjacent ferroelectric memory cells in the same row, which for example comprises four capacitors C00, C01, C10 and C11, which are electrically connected to the same two plate lines PL0 and PL1, as shown in fig. 9. The write operation of two adjacent ferroelectric memory cells may not be disturbed. In total 2⁴(16) An effective stateCan be written into four capacitors C00, C01, C10 and C11 in two adjacent ferroelectric memory cells.

Fig. 13 illustrates an exemplary timing diagram for reading a ferroelectric memory cell having multiple capacitors in accordance with some embodiments of the present disclosure. Fig. 14 is a flow chart of an exemplary method 1400 of reading a ferroelectric memory cell having N capacitors in accordance with some embodiments of the present disclosure. The ferroelectric memory cell depicted in fig. 13 and 14 may include a transistor and N capacitors, where N is a positive integer greater than 1. According to some embodiments, the transistors are electrically connected to the bit line and the word line, respectively, and each of the N capacitors is electrically connected to a respective plate line of the N parallel plate lines. Examples of the ferroelectric memory cell depicted in fig. 13 and 14 (where N ═ 2) include ferroelectric memory cell 902 depicted in fig. 9, ferroelectric memory cell 202 depicted in fig. 2, and ferroelectric memory cells 304 and 3063 depicted in fig. 3. Fig. 13 and 14 will be described together. It can be appreciated that the operations illustrated in the method 1400 are not exhaustive, and that other operations can be performed before, after, or in between the illustrated operations. Additionally, some of the operations may be performed concurrently or in a different order than shown in fig. 14.

The read operation disclosed with reference to fig. 13 and 14 implements a step-sensing scheme having a fast read speed by simultaneously using a plurality of reference voltages for sensing and less long-term disturbance due to enhancement of all data states by a write-back operation after the read operation. Referring to fig. 14, a method 1400 begins with operation 1402 in which a word line signal greater than Vdd is applied to a word line to select a ferroelectric memory cell. In some embodiments, the word line signal is Vdd plus the threshold voltage of the transistor. For example, a word line signal may be applied by a word line driver circuit of the peripheral device 908 to the gate of the transistor 906 via the first word line WL [0] to select the ferroelectric memory cell 902 for a read operation. As shown in the timing diagram of fig. 13, through a complete read cycle (t0 to t3), the word line signal WL at a high level (e.g., "1") may be applied and held to select the ferroelectric memory cell electrically connected to the corresponding word line. According to some embodiments, the high level of the word line signal WL is greater than Vdd.

The method 1400 proceeds to operation 1404, which is shown in fig. 14, where in operation 1404 plate line signals pulsed between 0V and a bias voltage are applied to each of the N plate lines in turn. In one example, the bias voltage is Vdd. In another example, the bias voltage is greater than Vdd, such as 4/3 at Vdd. As shown in the timing chart in fig. 13, in the first part (t0 to t1) of the reading period, the first plate line signal PL0 pulsed from a low level (e.g., "0") to a high level (e.g., "1") may be applied to the first plate line, and then in the second part (t1 to t2) of the reading period, the second plate line signal PL1 pulsed from a low level (e.g., "0") to a high level (e.g., "1") may be applied to the second plate line. According to some embodiments, the high level of the plate line signal PL is greater than or equal to Vdd. In some embodiments, each plate line signal fluctuates from 0V to Vdd or 4/3 pulses of Vdd in turn during a read cycle to a corresponding plate line of the N plate lines. The first plate line signal PL0 may be maintained at a high level (e.g., "1") during the second portion (t1 to t2) of the read cycle. In some embodiments, the first and second plate line signals may be applied by plate line driver circuitry of peripheral device 908 through first and second plate lines PL0 and PL1, respectively.

After a plate line signal at a bias voltage (e.g., Vdd or 4/3Vdd) is applied to each of the N plate lines, the bit line signal may be pulled up to one of N +1 levels by the plate line signal based on the valid state of the data stored in the N capacitors. In some embodiments, each of the N +1 levels reachable by the bit line signal corresponds to a respective active state of the N +1 active states of data. For example, as shown in FIG. 13, at t3 when the second plate line signal PL1 pulses high, the bit line signal BL [0] may be pulled up to any one of three levels: this level corresponds to a respective active state of the 3 active states 00, 01 and 11 and can be written and stored in the first and second capacitors C00 and C01.

Method 1400 proceeds to operation 1406, which is shown in FIG. 14, where in operation 1406, a plate line signal at a bias voltage is applied to each of the N plate linesThereafter, bit line signals on the bit lines read from the N capacitors are simultaneously compared to the N reference voltages to determine a valid state of data stored in the N capacitors from among a plurality of valid states of data. In one example where the bias voltage is Vdd, the data includes N +1 valid states. In another example where the bias voltage is greater than Vdd, such as 4/3 for Vdd, the data includes 2^NAn active state. As shown in the timing diagram of FIG. 13, in the third part of the read cycle (t 2-t 3, i.e., the sensing period), the bit line signal BL [0]]Are simultaneously read from the first and second capacitors C00 and C01, and the levels thereof are simultaneously compared with two reference voltages to determine the valid state of data stored in the first and second capacitors C00 and C01 from among 3 valid states of data (e.g., 00, 10, and 11). According to some embodiments, a first of the two reference voltages is between a low level and a middle level of the bit line signal and a second of the two reference voltages is between a level and a high level in the bit line signal in order to distinguish the valid state from the 3 possible valid states by comparison. The first and second plate line signals PL0 and PL1 may return to a low level (e.g., "0") during the sensing period. In some embodiments, the bit line signal is read by the peripheral device 908 through the bit line BL (0), two reference voltages are generated by the peripheral device 908, and the bit line signal is simultaneously compared to the two reference voltages using two sense amplifiers in the peripheral device 908.

As described above, the step sensing method may be used to simultaneously compare bit line signals read from the N capacitors with the N reference voltages to distinguish N +1 valid states of data in order to determine one of the valid states of data stored in the N capacitors. The N reference voltages may be preset based on N +1 levels to which the bit line signals may be sequentially pulled up by N plate line signals pulsed to a bias signal (e.g., Vdd) at the beginning of the sensing period.

In some embodiments, the word line signal and the plate line signal are applied in the same read cycle in which the bit line signal is read. In some embodiments, after the valid state of the data is determined, the valid state of the data is written back to the N capacitors. To write the valid state of the data back to the N capacitors, another plate line signal pulsed between 0V and the bias voltage may be applied to each of the N plate lines according to plate line timing, and another bit line signal pulsed between 0V and Vdd may be applied to the bit lines according to bit line timing to write the valid state of the data into the N capacitors. For example, as shown in fig. 13, after a read cycle (e.g., after t3), the valid state of the data is written back to the first and second capacitors C00 and C01 simultaneously in a write back period to enhance the storage of the valid state of the data in the first and second capacitors C00 and C01. The write back operation may be the same as the write operation described above, and thus the details thereof will not be described again.

Fig. 15 illustrates another exemplary timing diagram for reading a ferroelectric memory cell having multiple capacitors in accordance with some embodiments of the present disclosure. Fig. 16 is a flow chart of an exemplary method 1600 of reading a ferroelectric memory cell having N capacitors in accordance with some embodiments of the present disclosure. The ferroelectric memory cell depicted in fig. 15 and 16 may include a transistor and N capacitors, where N is a positive integer greater than 1. According to some embodiments, the transistors are electrically connected to the bit line and the word line, respectively, and each of the N capacitors is electrically connected to a respective plate line of the N parallel plate lines. Examples of the ferroelectric memory cell depicted in fig. 15 and 16 (where N ═ 2) include ferroelectric memory cell 902 depicted in fig. 9, ferroelectric memory cell 202 depicted in fig. 2, and ferroelectric memory cells 304 and 306 depicted in fig. 3. Fig. 15 and 16 will be described together. It can be appreciated that the operations shown in the method 1600 are not exhaustive, and that other operations may be performed before, after, or in between the operations shown. Additionally, some of the operations may be performed concurrently or in a different order than shown in 16.

The read operations described in fig. 15 and 16 implement a pulsed sensing scheme that avoids deleterious coupling effects by using a pulsed plate line signal. Referring to fig. 16, method 1600 begins with operation 1602 in which a word line signal greater than Vdd is applied to a word line to select a ferroelectric memory cell. In some embodiments, the word line signal is Vdd plus the threshold voltage of the transistor. For example, a word line signal may be applied by a word line driver circuit of the peripheral device 908 to the gate of the transistor 906 via the first word line WL [0] to select the ferroelectric memory cell 902 for a read operation. As shown in the timing diagram of fig. 15, through a complete read cycle (t0 to t6), the word line signal WL at a high level (e.g., "1") may be applied and held to select the ferroelectric memory cell electrically connected to the corresponding word line. According to some embodiments, the high level of the word line signal WL may be greater than Vdd.

The method 1600 proceeds to operation 1604, which is shown in fig. 16, where a plate line signal pulsed between 0V and a bias voltage is sequentially applied to each of the N plate lines in operation 1604. In one example, the bias voltage is Vdd. In another example, the bias voltage is greater than Vdd, such as 4/3 at Vdd. Method 1600 proceeds to operation 1606, which is shown in fig. 16, where in operation 1606, after each of the plate line signals at the bias voltage is applied to a respective plate line of the N plate lines, the respective bit line signal on the bit line read from the respective capacitor of the N capacitors is compared to a reference voltage to determine a valid state of the data stored in the N capacitors from among a plurality of valid states of the data. In one example where the bias voltage is Vdd, the data includes N +1 valid states. In another example where the bias voltage is greater than Vdd, such as 4/3 for Vdd, the data includes 2^NAn active state.

As shown in the timing chart in fig. 15, in the first part (t0 to t1) of the read cycle, a first plate line signal PL0 pulsed from a low level (e.g., "0") to a high level (e.g., "1") may be applied to the first plate line, and a second plate line signal PL1 at a low level (e.g., "0") may be applied to the second plate line. After the first plate line signal PL0 at a high level (e.g., "1") is applied to the first plate line, in a second portion (t1 to t2, i.e., a first sensing period) of the read cycle, the first bit line signal BL [0] read from the first capacitor C00 may be compared with the first reference voltage to determine a first bit of the valid state of the data stored in the first capacitor C00. In the first sensing period, the first plate line signal PL0 may be maintained at a high level (e.g., "1") and the second plate line signal PL1 may be maintained at a low level (e.g., "0"). At t1, the first reference voltage may be between the low level and the high level of the first bit line signal.

The same operation may be repeated for reading the second bit of the valid state of the data stored in the second capacitor C1. For example, after the first sensing period and in the fourth portion (t3 to t4) of the read cycle, the second plate line signal PL1 pulse-fluctuating from a low level (e.g., "0") to a high level (e.g., "1") may be applied to the second plate line, and the first plate line signal PL0 at a low level (e.g., "0") may be applied to the first plate line. After the second plate line signal PL1 at a high level (e.g., "1") is applied to the second plate line, in a fifth portion (t4 to t5, i.e., a second sensing period) of the read cycle, the second bit line signal BL [0] read from the second capacitor C1 may be compared with the second reference voltage to determine a second bit of the valid state of the data stored in the second capacitor C01. In the second sensing period, the second plate line signal PL1 may be maintained at a high level (e.g., "1") and the first plate line signal PL0 may be maintained at a low level (e.g., "0"). At t4, the second reference voltage may be between the low level and the high level of the second bit line signal. In some embodiments, the first and second plate line signals may be applied by plate line driver circuitry of peripheral device 908 through first and second plate lines PL0 and PL1, respectively. In some embodiments, the bit line signals are read by the peripheral devices 908 through a first bit line BL (0), the first and second reference voltages are generated by the peripheral devices 908, and each of the bit line signals is sequentially compared to a respective one of the reference voltages using one of the sense amplifiers in the peripheral devices 908. In some embodiments, the first reference voltage is the same as the second reference voltage.

As described above, the pulse sensing method may be used to sequentially compare each bit line signal read from a corresponding capacitor of the N capacitors with a corresponding reference voltage of the N reference voltages to distinguish N +1 valid states of data in order to determine one valid state of valid states of data stored in the N capacitors. Each of the N reference voltages may be preset based on high and low levels to which the corresponding bit line signal may be sequentially pulled up by N plate line signals pulsed to a bias signal (e.g., Vdd) at the beginning of the corresponding sensing period. In some embodiments, the N reference voltages are the same.

In some embodiments, after the valid state of the data is determined, the valid state of the data is written back to the N capacitors. To write the valid state of the data back to the N capacitors, another plate line signal pulsed between 0V and the bias voltage may be applied to each of the N plate lines according to plate line timing, and another bit line signal pulsed between 0V and Vdd may be applied to the bit lines according to bit line timing to write the valid state of the data into the N capacitors. For example, as shown in fig. 15, after a read cycle (e.g., after t6), the valid state of the data is written back to the first and second capacitors C00 and C01 simultaneously in a write back period to enhance the storage of the valid state of the data in the first and second capacitors C00 and C01. The write back operation may be substantially similar to the write operation described in detail above, and thus details thereof are not described again.

The foregoing detailed description of various specific embodiments is intended to disclose the general nature of the invention sufficiently that others can, by applying current knowledge within the field of application, readily modify/adapt it for various applications without undue experimentation and without departing from the basic concept of the invention. Thus, such modifications and adaptations are intended to be within the meaning and range of equivalents of the described embodiments of the invention, based on the teaching and guidance of the present invention. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and should not be regarded as limiting, since such terminology or phraseology will be regarded as limiting, since the terminology will be understood by those skilled in the art in light of the teachings and guidance presented herein.

The present invention realizes the description of the embodiments of the present invention by explaining specific functions and specific relationships with functional modules. For convenience of description, the definition of the functional modules is arbitrary. Other alternative definitions may be used so long as the specific function and relationship desired are achieved.