阅读说明：本技术 包括垂直堆叠式存储器阵列层及折叠式数字线连接的集成组合件 (Integrated assembly including vertically stacked memory array layers and folded digit line connections ) 是由 S·J·德尔纳 C·L·英戈尔斯 于 2019-06-04 设计创作，主要内容包括：本申请涉及包括垂直堆叠式存储器阵列层及折叠式数字线连接的集成组合件。一些实施例包含具有含感测放大器电路的基底的集成组合件。第一层在所述基底之上，且包含第一存储器单元的第一阵列。第二层在所述第一层之上，且包含第二存储器单元的第二阵列。第一数字线与所述第一阵列相关联，且第二数字线与所述第二阵列相关联。所述第一及第二数字线通过所述感测放大器电路彼此比较地耦合。(The present application relates to an integrated assembly including vertically stacked memory array layers and folded digit line connections. Some embodiments include integrated assemblies having a substrate with sense amplifier circuitry. A first layer is over the substrate and includes a first array of first memory cells. A second tier is above the first tier and includes a second array of second memory cells. A first digit line is associated with the first array and a second digit line is associated with the second array. The first and second digit lines are comparatively coupled to each other through the sense amplifier circuit.)

1. An integrated assembly, comprising:

a substrate including a sense amplifier circuit;

a first layer over the substrate and comprising a first array of first memory cells;

a second tier above the first tier and comprising a second array of second memory cells;

a first digit line associated with the first array;

a second digit line associated with the second array; and is

The first and second digit lines are comparatively coupled to each other through the sense amplifier circuit.

2. The integrated assembly of claim 1, wherein:

the first digit line is one of a number of digit lines of a first set of digit lines for addressing the first memory cell;

a first set of word lines is also used to address the first memory cell;

each of the first memory cells is uniquely addressed by one of the digit lines of the first set of digit lines and one of the word lines of the first set of word lines;

the second digit line is one of a number of digit lines of a second set of digit lines for addressing the second memory cell;

a second set of word lines is also used to address the second memory cells; and is

Each of the second memory cells is uniquely addressed by one of the digit lines of the second set of digit lines and one of the word lines of the second set of word lines.

3. The integrated assembly of claim 2, wherein:

the word lines of the first set of word lines are coupled with a first word line driver circuit associated only with the word lines of the first set of word lines; and is

The word lines of the second set of word lines are coupled with a second word line driver circuit associated only with the word lines of the second set of word lines.

4. The integrated assembly of claim 3, wherein:

the word lines of the first group are first word lines;

the word lines of the second group are second word lines;

the first word line driver circuit includes a first component along a first side of the first array and includes a second component along a second side of the first array;

the first set of first word lines comprises alternating even first word lines and odd first word lines;

the first component is coupled with the even first word lines; and is

The second component is coupled with the odd first word line.

5. The integrated assembly of claim 4, wherein:

the second word line driver circuit includes a third component along a first side of the second array and includes a fourth component along a second side of the second array;

the second set of second word lines comprises alternating even and odd second word lines;

the third component is coupled with the even second word lines; and is

The fourth component is coupled with the odd second word line.

6. An integrated assembly, comprising:

a substrate comprising a first sense amplifier circuit and a second sense amplifier circuit, wherein the second sense amplifier circuit is laterally displaced from the first sense amplifier circuit;

a first layer over the substrate and comprising a first array of first memory cells;

a second tier above the first tier and comprising a second array of second memory cells;

a first digit line associated with the first array, the first digit line alternating between even and odd first digit lines;

a second digit line associated with the second array, the second digit line alternating between even and odd second digit lines;

individual ones of the even first digit lines are comparatively coupled with individual ones of the even second digit lines by the first sense amplifier circuits; and is

Individual ones of the odd first digit lines are comparatively coupled with individual ones of the odd second digit lines through the second sense amplifier circuit.

7. The integrated assembly of claim 6, wherein:

the first digit line is used to address the first memory cell;

a first set of first word lines is also used to address the first memory cells;

each of the first memory cells is uniquely addressed by one of the first digit lines and one of the first word lines;

the second digit line is for addressing the second memory cell;

a second set of second word lines is also used to address the second memory cells; and is

Each of the second memory cells is uniquely addressed by one of the second digit lines and one of the second word lines.

8. The integrated assembly of claim 7, wherein:

the word lines of the first set of word lines are coupled with a first word line driver circuit associated only with the word lines of the first set of word lines; and is

The word lines of the second set of word lines are coupled with a second word line driver circuit associated only with the word lines of the second set of word lines.

9. The integrated assembly of claim 8, wherein:

the first word line driver circuit includes a first component along a first side of the first array and includes a second component along a second side of the first array;

the first set of first word lines comprises alternating even first word lines and odd first word lines;

the first component is coupled with the even first word lines;

the second component is coupled with the odd first word line;

the second word line driver circuit includes a third component along a first side of the second array and includes a fourth component along a second side of the second array;

the second set of second word lines comprises alternating even and odd second word lines;

the third component is coupled with the even second word lines; and is

The fourth component is coupled with the odd second word line.

10. The integration assembly of claim 6, wherein each of the memory cells comprises a charge storage device in combination with a transistor.

11. The integration assembly of claim 6, wherein each of the memory cells comprises a capacitor in combination with a transistor.

12. An integrated assembly, comprising:

a first sense amplifier circuit laterally displaced relative to a second sense amplifier circuit;

a first digit line vertically displaced from the first and second sense amplifier circuits and extending along a first memory array; the first digit lines are laterally displaced with respect to each other and alternate between even first digit lines and odd first digit lines;

a second digit line vertically displaced relative to the first and second sense amplifier circuits, vertically displaced relative to the first digit line, and extending along a second memory array; the second digit lines being laterally displaced relative to each other and alternating between even and odd second digit lines;

individual ones of the even first digit lines are mutually coupled with individual ones of the even second digit lines through the first sense amplifier circuits;

individual ones of the odd first digit lines are mutually coupled with individual ones of the odd second digit lines through the second sense amplifier circuits;

a first set of first word lines extending along the first memory array;

a second set of second word lines extending along the second memory array;

the first word line is coupled with a first word line driver circuit; and is

The second word line is coupled with a second word line driver circuit.

13. The integrated assembly of claim 12, wherein the first and second word line driver circuits are above the first and second sense amplifier circuits.

14. The integrated assembly of claim 12, wherein:

the first word line driver circuit includes a first component along a first side of the first memory array and includes a second component along a second side of the first memory array;

the first set of first word lines comprises alternating even first word lines and odd first word lines;

the first component is coupled with the even first word lines;

the second component is coupled with the odd first word line;

the second word line driver circuit includes a third component along a first side of the second memory array and includes a fourth component along a second side of the second memory array;

the second set of second word lines comprises alternating even and odd second word lines;

the third component is coupled with the even second word lines; and is

The fourth component is coupled with the odd second word line.

Technical Field

An integrated assembly including vertically stacked memory array layers and folded digit line connections.

Background

Memory is used in modern computing architectures to store data. One type of memory is Dynamic Random Access Memory (DRAM). DRAM may offer the advantages of simple structure, low cost, and high speed compared to alternative types of memory.

DRAM may utilize memory cells each having one capacitor in combination with one transistor (so-called 1T-1C memory cells), where the capacitor is coupled to the source/drain region of the transistor. Example 1T-1C memory cell 2 is shown in fig. 1, with the transistor labeled T and the capacitor labeled C. The capacitor has one node coupled to the source/drain region of the transistor and another node coupled to the common plate CP. The common plate can be coupled to any suitable voltage, such as a voltage ranging from greater than or equal to ground to less than or equal to VCC (i.e., ground ≦ CP ≦ VCC). In some applications, the common plate is at a voltage of about half VCC (i.e., about VCC/2). The transistor has a gate coupled to a word line WL (i.e., an access line) and has a source/drain region coupled to a bit line BL (i.e., a digit line or a sense line). In operation, an electric field generated by a voltage along a word line may gate couple a bit line to a capacitor during read/write operations.

Another prior art 1T-1C memory cell configuration is shown in FIG. 2. The configuration of FIG. 2 shows two memory cells 2a and 2 b; wherein memory cell 2a includes transistor T1 and capacitor C1, and wherein memory cell 2b includes transistor T2 and capacitor C2. Word lines WL0 and WL1 are electrically coupled to the gates of transistors T1 and T2, respectively. The connection to the bit line BL is shared by memory cells 2a and 2 b.

The memory cells described above may be incorporated into a memory array, and in some applications, the memory array may have an open bit line arrangement. An example integrated assembly 9 having an open bitline architecture is shown in fig. 3. The assembly 9 includes two laterally adjacent memory arrays ("array 1" and "array 2"), with each of the arrays including memory cells of the type described in figure 2 (not labeled in figure 3 in order to simplify the drawing). Word lines WL 0-WL 7 extend across the array and are coupled with word line drivers. The digit lines D0 to D8 are associated with the first array (array 1) and the digit lines D0 to D8 are associated with the second array (array 2). Sense amplifiers SA 0-SA 8 are provided between the first and second arrays. The digitlines at the same height are paired with each other and compared by the sense amplifier (e.g., digitlines D0 and D0 are paired with each other and compared with sense amplifier SA 0). In a read operation, one of the paired digit lines can be used as a reference in determining an electrical property (e.g., voltage) of the other of the paired digit lines.

A continuing goal of integrated circuit fabrication is to increase packing density and thus integration. It may be desirable to develop a three-dimensional arrangement with tightly packed memory.

Disclosure of Invention

In one aspect, the present application relates to an integrated assembly comprising: a substrate including a sense amplifier circuit; a first layer over the substrate and comprising a first array of first memory cells; a second tier above the first tier and comprising a second array of second memory cells; a first digit line associated with the first array; a second digit line associated with the second array; and the first and second digit lines are comparatively coupled to each other through the sense amplifier circuitry.

In another aspect, the present application relates to an integrated assembly comprising: a substrate comprising a first sense amplifier circuit and a second sense amplifier circuit, wherein the second sense amplifier circuit is laterally displaced from the first sense amplifier circuit; a first layer over the substrate and comprising a first array of first memory cells; a second tier above the first tier and comprising a second array of second memory cells; a first digit line associated with the first array, the first digit line alternating between even and odd first digit lines; a second digit line associated with the second array, the second digit line alternating between even and odd second digit lines; individual ones of the even first digit lines are comparatively coupled with individual ones of the even second digit lines by the first sense amplifier circuits; and individual ones of the odd first digit lines are comparatively coupled with individual ones of the odd second digit lines through the second sense amplifier circuits.

In another aspect, the present application relates to an integrated assembly comprising: a first sense amplifier circuit laterally displaced relative to a second sense amplifier circuit; a first digit line vertically displaced from the first and second sense amplifier circuits and extending along a first memory array; the first digit lines are laterally displaced with respect to each other and alternate between even first digit lines and odd first digit lines; a second digit line vertically displaced relative to the first and second sense amplifier circuits, vertically displaced relative to the first digit line, and extending along a second memory array; the second digit lines being laterally displaced relative to each other and alternating between even and odd second digit lines; individual ones of the even first digit lines are comparatively coupled with individual ones of the even second digit lines by the first sense amplifier circuits; individual ones of the odd first digit lines are comparatively coupled with individual ones of the odd second digit lines through the second sense amplifier circuitry; a first set of first word lines extending along the first memory array; a second set of second word lines extending along the second memory array; the first word line is coupled with a first word line driver circuit; and the second word line is coupled with a second word line driver circuit.

Drawings

FIG. 1 is a schematic diagram of a prior art memory cell having 1 transistor and 1 capacitor.

FIG. 2 is a schematic diagram of a pair of prior art memory cells each having 1 transistor and 1 capacitor and sharing a bitline connection.

FIG. 3 is a schematic diagram of a prior art integration assembly having an open bit line architecture.

FIG. 4A is a schematic diagram of an example integrated assembly having multiple layers vertically displaced relative to each other.

Fig. 4B and 4C are top views of the layers of the assembly of fig. 4A.

FIG. 5 is a diagrammatic top view of a layout of an example arrangement of a memory array and associated circuitry.

Fig. 6A and 6B are diagrammatic side views along lines a-a and B-B of fig. 4A, respectively, showing an example arrangement of circuit components.

Fig. 7A and 7B are diagrammatic side views along lines a-a and B-B of fig. 4A, respectively, showing an example arrangement of circuit components.

Fig. 8A and 8B are diagrammatic side views along lines a-a and B-B of fig. 4A, respectively, showing an example arrangement of circuit components.

FIG. 9 is a diagrammatic schematic of an example sense amplifier circuit.

Detailed Description

Some embodiments include an integrated assembly in which a first memory array is vertically offset relative to a second memory array, and in which sense amplifier circuitry is provided beneath the first and second memory arrays. A first digit line is associated with the first memory array and a second digit line is associated with the second memory array. The first digit line is comparatively coupled with the second digit line through the sense amplifier circuit. The first and second digit lines extend laterally (i.e., horizontally) along the memory array and then fold at the edges of the memory array to extend perpendicular to the sense amplifier circuitry. Thus, some embodiments may be considered to include folded digit line connections. Example embodiments are described with reference to fig. 4A, 4B, 4C, 5, 6A, 6B, 7A, 7B, 8A, 8B, and 9.

Referring to fig. 4A, the integrated assembly 10 includes a substrate 12, a first layer 14 over the substrate, and a second layer 16 over the first layer.

First tier 14 includes a first memory array 18, with the approximate periphery of such memory array illustrated with dashed lines 15. The first memory array includes first memory cells 20, illustrated as boxes within the memory array. Only a portion of the first memory cells are shown, but in practice the first memory cells may extend completely across the first memory array. The first memory array 18 may include any suitable number of first memory cells, and may include hundreds, thousands, millions, etc. of first memory cells in some embodiments. The first memory cells may be DRAM cells, and in some embodiments may be configured in an arrangement of the type described above with reference to prior art fig. 1-3.

The second tier 16 includes a second memory array 22, with the approximate periphery of this memory array illustrated with dashed lines 21. The second memory array includes second memory cells 24, illustrated as boxes within the memory array. Only a portion of the second memory cells are shown, but in practice the second memory cells may extend completely across the second memory array. The second memory array 22 may include any suitable number of memory cells, and may include hundreds, thousands, millions, etc. of second memory cells in some embodiments. The second memory cells may be DRAM cells, and in some embodiments may be configured in an arrangement of the type described above with reference to prior art fig. 1-3.

In some embodiments, the first and second tiers may be referred to as first and second memory tiers, respectively.

Substrate 12 may comprise a semiconductor material; and may, for example, comprise, consist essentially of, or consist of monocrystalline silicon. The base 12 may be referred to as a semiconductor substrate. The term "semiconductor substrate" means any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials), and semiconductive material layers (either alone or in assemblies comprising other materials). The term "substrate" refers to any supporting structure, including, but not limited to, the semiconductor substrates described above. In some applications, base 12 may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit fabrication. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, and the like. Each of layers 14 and 16 may also include a semiconductor material.

In the embodiment shown, the substrate 12 includes sense amplifier circuitry. In particular, the substrate includes a first sense amplifier circuit 26 and a second sense amplifier circuit 28, wherein the second sense amplifier circuit is laterally displaced relative to the first sense amplifier circuit. Dashed lines 23 and 25 are provided to illustrate the approximate boundaries of the first sense amplifier circuit 26 and the second sense amplifier circuit 28, respectively. Although the first and second sense amplifier circuits are shown as being laterally spaced from one another, in other embodiments, the first and second sense amplifier circuits may be directly adjacent to one another, and may even be interleaved with one another.

First sense amplifier circuit 26 is labeled "SA-E" to identify it as being associated with an "even" portion of the circuit, and second sense amplifier circuit 28 is labeled "SA-O" to identify it as being associated with an "odd" portion of the circuit. The terms "even" and "odd" are arbitrary and are used to distinguish the two sense amplifier circuits 26 and 28 from each other.

First digit lines D0 and D1 are associated with first memory array 18. In particular, first digit lines D0 and D1 extend along and are coupled with first memory cells 20 of the first memory array. Digit lines D0 and D1 are laterally spaced from one another and may represent a large number of substantially identical digit lines extending across the first memory array; wherein the term "substantially the same" means within reasonable tolerances for manufacturing and measurement. The first digit lines may alternate between even first digit lines and odd first digit lines, where digit line D0 represents an even first digit line and digit line D1 represents an odd first digit line. The even first digit lines (e.g., D0) are coupled with the first sense amplifier circuits 26 (i.e., SA-E) and the odd first digit lines (e.g., D1) are coupled with the second sense amplifier circuits 28 (i.e., SA-O). Fig. 4C shows a top view of layer 14 and shows a plurality of even digit lines (D0, D2, D4) alternating with a plurality of odd digit lines (D1, D3, D5) across memory array 18. The even digit lines are coupled to a first amplifier circuit 26(SA-E) and the odd digit lines are coupled to a second sense amplifier circuit 28 (SA-O).

Second digit lines D0 and D1 are associated with second memory array 22. In particular, second digit lines D0 and D1 extend along the second memory array and are coupled to second memory cells 24 of the second memory array. Digit lines D0 and D1 are laterally spaced from one another and may represent a plurality of substantially identical digit lines extending across the second memory array. The second digit lines may alternate between even second digit lines and odd second digit lines, wherein digit line D0 represents even second digit lines and digit line D1 represents odd second digit lines. Even second digit lines (e.g., D0) are coupled to the first sense amplifier circuits 26 (i.e., SA-E), and odd second digit lines (e.g., D1) are coupled to the second sense amplifier circuits 28 (i.e., SA-O). Fig. 4B shows a top view of layer 16 and shows a plurality of even numbered lines (D0, D2, D4) alternating with a plurality of odd numbered lines (D1, D3, D5) across memory array 22. The even digit lines are coupled to a first sense amplifier circuit 26(SA-E) and the odd digit lines are coupled to a second sense amplifier circuit 28 (SA-O).

The even first digit lines D0 are comparatively coupled with the even second digit lines D0 by the first sense amplifier circuits 26, and the odd first digit lines D1 are comparatively coupled with the odd second digit lines D1 by the second sense amplifier circuits 28. For purposes of understanding the present disclosure and the following claims, a first digit line is "comparatively coupled" with a second digit line by a sense amplifier circuit if the sense amplifier circuit is configured to compare an electrical property (e.g., voltage) of the first digit line and an electrical property of the second digit line to one another. Fig. 9 (discussed below) shows an example sense amplifier circuit 26, and shows an example application in which digit lines D0 and D0 are comparatively coupled through the example sense amplifier circuit.

Each of the first digit lines (e.g., D0-D5 of fig. 4C) is paired with one of the second digit lines (e.g., D0-D5 of fig. 4B) and is comparatively coupled to the paired second digit line by one of the sense amplifier circuits 26 and 28. In the application illustrated in fig. 4B and 4C, the digit line pairs will be D0/D0, D1/D1, D2/D2, D3/D3, D4/D4, and D5/D5. Odd digit line pairs (D1/D1, D3/D3, and D5/D5) are comparatively coupled through sense amplifier circuit 28(SA-O), and even digit line pairs (D0/D0, D2/D2, and D4/D4) are comparatively coupled through sense amplifier circuit 26 (SA-E).

In some embodiments, the first digit line (e.g., D0 and D1 of fig. 4A) may be considered vertically displaced relative to the first sense amplifier circuitry 26 and the second sense amplifier circuitry 28; and the second digit line (e.g., D0 and D1 of fig. 4A) may be considered vertically displaced relative to the first digit line and relative to the first and second sense amplifier circuits 26 and 28.

Fig. 4A shows row driver circuitry along layers 14 and 16. The first layer 14 is shown having a first side (i.e., left side) 31 and an opposing second side (i.e., right side) 33; and has a first row driver 30 along the left and a second row driver 32 along the right. The first row driver 30 is labeled "row driver S1 left", where S1 refers to stacking one, and refers to the first layer 14. The second row driver 32 is labeled "row driver S1 right". The second layer 16 is shown having a first side (i.e., left side) 35 and an opposing second side (i.e., right side) 37; and has a third row of drivers 34 along the left and a fourth row of drivers 36 along the right. The third row driver 34 is labeled "row driver S2 left", where S2 refers to Stack two, and refers to the second layer 16. The fourth row driver 36 is labeled "row driver S2 right".

First row driver 30 and second row driver 32 may together be considered a first word line driver circuit, and second row driver 34 and third row driver 36 may together be considered a second word line driver circuit. In the illustrated embodiment, the first and second word line driver circuits are physically separated from each other and vertically displaced relative to each other. In particular, the first layer 14 is shown at a first elevation, and the row drivers 30 and 32 of the first word line driver circuit are illustrated as being along this first elevation; and second layer 16 is shown at a second elevation above the first elevation, and row drivers 34 and 36 of the second word line driver circuit are shown at the second elevation. Using separate word line driver circuits for the first and second tiers advantageously avoids one or more multiplexers needed to direct data if a common word line driver circuit is used for both the first and second tiers.

The row drivers 30, 32, 34, and 36 may be placed in any suitable location, and in some embodiments, all may be at the same elevation as one another. For example, all of the row drivers 30, 32, 34, and 36 may be positioned below layer 14 and may be provided above the sense amplifiers of layer 12. In such embodiments, an additional layer may be provided between layers 12 and 14, where at least one purpose of this additional layer is to support row drivers 30, 32, 34, and 36.

A first set of word lines extends along the first memory array 18 of the first layer 14. Representative word lines of this first set are labeled WL0 and WL4 in FIG. 4A. Word line WL0 is coupled with a first row driver 30 and word line WL4 is coupled with a second row driver 32. A second set of word lines extends along the first memory array 22 of the second layer 16. Representative word lines of this second set are labeled WL8 and WL12 in FIG. 4A. Word line WL8 is coupled with third row driver 34, and word line WL12 is coupled with fourth row driver 36.

The row drivers 30 and 32 may be considered to be associated only with word lines of the first layer (e.g., WL0 and WL4) because they are specifically used to drive word lines of the first layer and not used to drive word lines of the other layer. Similarly, row drivers 34 and 36 may be considered to be associated only with the second tier's word lines (e.g., WL8 and WL12) because they are specifically used to drive the second tier's word lines and not used to drive the other tier's word lines.

Each of the first memory cells 20 within the first memory array 18 is uniquely addressed by one of the digit lines extending along the memory array 18 (e.g., one of the digit lines D0 and D1 of fig. 4A) and one of the word lines extending along the memory array 18 (e.g., one of the word lines WL0 and WL4 of fig. 4A). Similarly, each of the memory cells 24 within the second memory array 22 is uniquely addressed by one of the digitlines extending along the memory array 22 (e.g., one of the digitlines D0 and D1 of fig. 4A) and one of the wordlines extending along the memory array 22 (e.g., one of the wordlines WL8 and WL12 of fig. 4A). In some embodiments, the digit lines along the first memory array 18 may be referred to as a first set of digit lines, while the word lines along the second memory 22 are referred to as a second set of digit lines; and similarly, word lines along the first memory array 18 may be referred to as a first set of word lines, while word lines along the second memory 22 are referred to as a second set of word lines. Thus, each of the memory cells 20 of the memory array 18 can be considered to be uniquely addressed with a word line from the first set of word lines in combination with a digit line from the first set of digit lines; and each of the memory cells 24 of the memory array 22 can be considered to be uniquely addressed with a word line from the second set of word lines in conjunction with a digit line from the second set of digit lines.

In some embodiments, row drivers 30 and 32 may be considered first and second components, respectively, of a first word line driver circuit. Word lines along the memory array 18 of the first layer 14 may be considered first word lines of the first set of word lines, where such first word lines alternate between even first word lines and odd first word lines. Even first word lines are coupled with a first component of a first word line driver circuit (i.e., first row driver 30); where word line WL0 represents the even first word line. The odd first word lines are coupled with a second component of the first word line driver circuitry (i.e., row driver 32); where word line WL4 represents the odd first word line. The terms "even" and "odd" are arbitrary as applied to the first word line and are used to distinguish the word line coupled to the first row driver 30 from the word line coupled to the second row driver 32.

In some embodiments, row drivers 34 and 36 may be considered third and fourth components, respectively, of a second word line driver circuit (with the terms "third component" and "fourth component" being used to distinguish these components from the first and second components described above). Word lines along the memory array 22 of the second layer 16 may be considered second word lines of the second set of word lines, where such second word lines alternate between even-numbered second word lines and odd-numbered second word lines. Even second word lines are coupled with a third component of second word line driver circuitry (i.e., third row driver 34); where word line WL8 represents the even second word line. Odd second word lines are coupled with a fourth component of the second word line driver circuit (i.e., row driver 36); where word line WL12 represents an odd second word line. The terms "even" and "odd" are arbitrary as applied to the second word line and are used to distinguish word lines coupled with third row drivers 34 from word lines coupled with fourth row drivers 36.

An advantage of the configuration of FIG. 4A is that all of the sense amplifier circuitry is provided under the memory arrays 18 and 22, which may enable the memory arrays to be tightly packaged across a semiconductor substrate; or in other words, this may save valuable semiconductor real estate as compared to conventional configurations in which at least a portion of the sense amplifier circuitry is along the same elevational plane as the memory array. The vertical stacking of the memory arrays 18 and 22 may further save valuable semiconductor real estate.

In some embodiments, the configuration of fig. 4A may represent multiple configurations laterally displaced relative to each other across the semiconductor die. For example, FIG. 5 shows a top view of an area of an example die 40 having a plurality of memory arrays 22 (labeled elevations 22 a-d) laterally displaced relative to one another. Such memory arrays are illustrated as being associated with configurations 10 a-d, where such configurations are similar to configuration 10 of FIG. 4A.

Memory arrays 18 and 22 of figure 4A may include any suitable memory cells. Example configurations of such memory arrays are described with reference to fig. 6A, 6B, 7A, 7B, 8A, and 8B; wherein fig. 6A, 7A, and 8A are along line a-a of fig. 4A, and fig. 6B, 7B, and 8B are along line B-B of fig. 4A.

Referring to fig. 6A and 6B, memory cells 20 and 24 of memory arrays 18 and 20 are labeled MC. Each of the memory cells 20 of the memory array 18 is uniquely addressed by a digit line (D0 or D1) and a word line (WL 0-WL 7). Each of the memory cells 24 of the memory array 22 is uniquely addressed by a digit line (D0 or D1) and a word line (WL 8-WL 15). Digit lines D0 and D0 are comparatively coupled to each other through sense amplifier circuit 26, and digit lines D1 and D1 are comparatively coupled to each other through sense amplifier circuit 28.

In some embodiments, word lines WL 0-WL 7 may be considered a first set of word lines associated with the first memory array 18; with word lines WL 0-WL 3 being considered even word lines coupled with row driver 30 and word lines WL 4-WL 7 being considered odd word lines coupled with row driver 32. Similarly, word lines WL 8-WL 15 may be considered a second set of word lines associated with the second memory array 22; with word lines WL 8-WL 11 being considered even word lines coupled with row driver 34 and word lines WL 12-WL 15 being considered odd word lines coupled with row driver 36.

Referring to fig. 7A and 7B, example memory cells 20 and 24 of memory arrays 18 and 20 are shown in more detail than in fig. 6A and 6B. Each of the example memory cells 20 and 24 includes a transistor T coupled with a capacitor C. Each capacitor has a node coupled to a reference voltage 42. The reference voltage 42 may correspond to the Common Plate (CP) voltage described above with reference to fig. 1. The memory cells illustrated in FIGS. 7A and 7B are 1T-1C memory cells. In other embodiments, other memory cells may be utilized. The capacitors of the illustrated memory cells 20 and 24 are example charge storage devices, and in other embodiments, other suitable charge storage devices (e.g., phase change devices, conductive bridge devices, etc.) may be utilized.

Referring to fig. 8A and 8B, example memory cells 20 and 24 of memory arrays 18 and 20 are shown in more detail than in fig. 7A and 7B. The transistor T is shown as a vertically-extending pillar 50 comprising semiconductor material 52. Semiconductor material 52 may comprise any suitable composition; and in some embodiments may comprise, consist essentially of, or consist of silicon, germanium, III/V semiconductor material (e.g., gallium phosphide), semiconductor oxide, or the like; wherein the term III/V semiconductor material refers to a semiconductor material comprising an element selected from groups III and V of the periodic table (wherein groups III and V are old nomenclature and are now referred to as groups 13 and 15). Source/drain and channel regions (not shown) may be provided within the pillars 50. Gate dielectric material 54 is along the sidewalls of the pillars and conductive gate material 56 is along the gate dielectric material.

Gate dielectric material 54 may comprise any suitable composition; and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide.

Gate material 56 may comprise any suitable conductive composition; such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.).

Capacitor C includes a first conductive node 58, a second conductive node 60, and an insulating material 62 between the first and second conductive nodes. The first conductive node 60 and the second conductive node 62 may comprise any suitable conductive composition; such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). The first and second conductive nodes may comprise the same composition as one another, or may comprise different compositions from one another. The insulating material 62 can comprise any suitable composition, and in some embodiments can comprise, consist essentially of, or consist of silicon dioxide.

In the illustrated embodiment, the lower conductive node 58 is configured as an upwardly open container. In other embodiments, the lower conductive node may have other suitable shapes. The lower conductive node 58 may be referred to as a storage node, and the upper node 60 may be referred to as a plate electrode. In some embodiments, the plate electrodes within memory array 18 may all be coupled to one another, and the plate electrodes within memory array 22 may also all be coupled to one another.

The digit lines D0, D0, D1, and D1 are shown to include conductive materials 64, 66, 68, and 70, respectively. Such conductive materials may include any suitable conductive composition; such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and/or conductively-doped semiconductor materials (e.g., conductively-doped silicon, conductively-doped germanium, etc.). In some embodiments, conductive materials 64, 66, 68, and 70 may be the same composition as one another, or in other embodiments, at least one of the conductive materials may be different from another.

Sense amplifier circuits 26 and 28 may comprise any suitable configuration. An example sense amplifier circuit 26 is illustrated in fig. 9. Dashed line 71 is provided to show the approximate boundaries of the sense amplifier circuitry. Although the illustrated circuit is described as being the sense amplifier circuit 26, it is understood that the sense amplifier circuit 28 may include the same configuration as described with respect to the example configuration of fig. 9.

The sense amplifier circuit of FIG. 9 includes a p-sense amplifier 80 including a pair of cross-coupled pull-up transistors 82 and 84, and includes an n-sense amplifier 86 including a pair of cross-coupled pull-down transistors 88 and 90. The p sense amplifier 80 is coupled with an active pull-up circuit (labeled ACT) and the n sense amplifier 86 is coupled with a common node (labeled RNL). The illustrated sense amplifier circuit 26 is coupled with digit lines D0 and D0; or in other words, digit lines D0 and D0 are coupled in comparison to each other through the illustrated sense amplifier circuit 26. In operation, amplifiers 80 and 86 may be used together to detect the relative signal voltages of D0 and D0, and drive the higher signal voltage to VCC while driving the lower signal voltage to ground. Also, the inputs and outputs (labeled I/O) associated with the sense amplifiers may be used to output data regarding the relative signal voltages of D0 and D0, and/or to program the memory cells along one or both of D0 and D0.

The illustrated sense amplifier circuit also has a balancing circuit (labeled EQ) provided herein to balance electrical properties within the sense amplifier. Other circuitry (not shown) may also be provided within the sense amplifier circuitry. The sense amplifier circuit of FIG. 9 may comprise any suitable configuration, and in some embodiments may comprise a conventional configuration.

The assemblies and structures discussed above may be used within an integrated circuit (where the term "integrated circuit" means an electronic circuit supported by a semiconductor substrate); and may be incorporated into an electronic system. Such electronic systems may be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. Electronic systems may be any of a wide range of systems such as, for example, cameras, wireless devices, displays, chipsets, set-top boxes, gaming consoles, lighting devices, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, airplanes, and the like.

Unless otherwise specified, the various materials, substances, compositions, etc. described herein can be formed using any suitable method now known or yet to be developed, including, for example, Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), etc.

The terms "dielectric" and "insulating" may be used to describe a material having insulating electrical properties. In the present invention, the terms are considered synonymous. In some instances, using the term "dielectric," and in other instances, using the term "insulating" (or "electrically insulating"), language changes may be provided within the invention to simplify the preceding basis within the appended claims and not to indicate any significant chemical or electrical difference.

The particular orientation of the various embodiments in the figures is for illustrative purposes only, and in some applications, the embodiments may be rotated relative to the orientation shown. The description provided herein and the appended claims refer to any structure having a described relationship between various features, whether or not the structure is in a particular orientation in the figures or rotated relative to such orientation.

Unless otherwise specified, the cross-sectional views of the accompanying description only show features within the plane of the cross-section, and do not show material behind the plane of the cross-section, in order to simplify the figures.

When a structure is referred to above as being "on," "adjacent to," or "against" another structure, it can be directly on the other structure or intervening structures may also be present. In contrast, when a structure is referred to as being "directly on," "directly adjacent to," or "directly against" another structure, there are no intervening structures present.

Structures (e.g., layers, materials, etc.) may be referred to as "vertically extending" to indicate that the structures generally extend upward from an underlying base (e.g., substrate). The vertically extending structures may extend substantially orthogonal to the upper surface of the substrate, or not orthogonal to the upper surface of the substrate.

Some embodiments include an integrated assembly having: a substrate having a sense amplifier circuit. A first layer is over the substrate and includes a first array of first memory cells. A second tier is above the first tier and includes a second array of second memory cells. A first digit line is associated with the first array and a second digit line is associated with the second array. The first and second digit lines are comparatively coupled to each other through the sense amplifier circuit.

Some embodiments include an integrated assembly having: the substrate includes a first sense amplifier circuit and a second sense amplifier circuit. The second sense amplifier circuit is laterally displaced from the first sense amplifier circuit. A first layer is over the substrate and includes a first array of first memory cells. A second tier is above the first tier and includes a second array of second memory cells. A first digit line is associated with the first array. The first digit lines alternate between even first digit lines and odd first digit lines. A second digit line is associated with the second array. The second digit lines alternate between even and odd second digit lines. Individual ones of the even first digit lines are comparatively coupled with individual ones of the even second digit lines by the first sense amplifier circuits. Individual ones of the odd first digit lines are comparatively coupled with individual ones of the odd second digit lines through the second sense amplifier circuit.

Some embodiments include an integrated assembly, including: a first sense amplifier circuit laterally displaced relative to a second sense amplifier circuit. A first digit line is vertically displaced from the first and second sense amplifier circuits and extends along a first memory array. The first digit lines are laterally displaced with respect to each other and alternate between even numbered first digit lines and odd numbered first digit lines. A second digit line is vertically displaced relative to the first and second sense amplifier circuits, vertically displaced relative to the first digit line, and extends along a second memory array. The second digit lines are laterally displaced relative to each other and alternate between even and odd second digit lines. Individual ones of the even first digit lines are comparatively coupled with individual ones of the even second digit lines by the first sense amplifier circuits. Individual ones of the odd first digit lines are comparatively coupled with individual ones of the odd second digit lines through the second sense amplifier circuit. A first set of first word lines extends along the first memory array. A second set of second word lines extends along the second memory array. The first word line is coupled with a first word line driver circuit. The second word line is coupled with a second word line driver circuit.